[U-Boot] [PATCH 1/3] fsl/pci: fix leading whitespace of PCI_LTSSM_L0
Fix the whitespace of PCI_LTSSM_L0 in fsl_pci.h
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com --- arch/powerpc/include/asm/fsl_pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index cad341e72c..970f3a48d5 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -23,7 +23,7 @@ #define FSL_PROG_IF_AGENT 0x1
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ -#define PCI_LTSSM_L0 0x16 /* L0 state */ +#define PCI_LTSSM_L0 0x16 /* L0 state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose);
Adjust the code structure, detail the function module function, remove the redundancy code.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com --- arch/powerpc/include/asm/fsl_pci.h | 1 + drivers/pci/fsl_pci_init.c | 150 ++++++++++++++++++++----------------- 2 files changed, 83 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 970f3a48d5..70a5461709 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -24,6 +24,7 @@
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ +#define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index af20cf0f3e..be57e53811 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) #endif +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2
/* Setup one inbound ATMU window. * @@ -290,6 +292,80 @@ static void fsl_pcie_boot_master_release_slave(int port) } #endif
+static int fsl_is_pex_rev_3(struct fsl_pci_info *pci_info) +{ + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + u32 block_rev; + + block_rev = in_be32(&pci->block_rev1); + if (block_rev >= PEX_IP_BLK_REV_3_0) + return 1; + + return 0; +} + +static int fsl_get_ltssm(struct pci_controller *hose, + struct fsl_pci_info *pci_info) +{ + u16 ltssm = 0; + pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + + if (fsl_is_pex_rev_3(pci_info)) + ltssm = (in_be32(&pci->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + else + pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); + + return ltssm; +} + +static int fsl_pci_link_up(struct pci_controller *hose, + struct fsl_pci_info *pci_info) +{ + int enabled = 0; + u16 ltssm; + int i, pci_ltssm_l0; + + if (fsl_is_pex_rev_3(pci_info)) + pci_ltssm_l0 = PCI_LTSSM_L0_PEX_REV3; + else + pci_ltssm_l0 = PCI_LTSSM_L0; + + ltssm = fsl_get_ltssm(hose, pci_info); + + if (ltssm == pci_ltssm_l0) { + enabled = 1; + } else { + for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) { + ltssm = fsl_get_ltssm(hose, pci_info); + udelay(1000); + } + enabled = ltssm >= pci_ltssm_l0; + } + + return enabled; +} + +#if defined(CONFIG_FSL_PCIE_RESET) || \ + defined(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) +static void fsl_do_pcie_reset(struct fsl_pci_info *pci_info) +{ + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; + + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); +} +#endif + void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) { u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; @@ -298,7 +374,6 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) u32 temp32; u32 block_rev; int enabled, r, inbound = 0; - u16 ltssm; u8 temp8, pcie_cap; int pcie_cap_pos; int pci_dcr; @@ -438,63 +513,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { - if (block_rev >= PEX_IP_BLK_REV_3_0) { -#define PEX_CSR0_LTSSM_MASK 0xFC -#define PEX_CSR0_LTSSM_SHIFT 2 - ltssm = (in_be32(&pci->pex_csr0) - & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; - enabled = (ltssm == 0x11) ? 1 : 0; #ifdef CONFIG_FSL_PCIE_RESET - int i; - /* assert PCIe reset */ - setbits_be32(&pci->pdb_stat, 0x08000000); - (void) in_be32(&pci->pdb_stat); - udelay(1000); - /* clear PCIe reset */ - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, - <ssm); - udelay(1000); - } + fsl_do_pcie_reset(pci_info); + pci_hose_write_config_dword(hose, dev, + PCI_BASE_ADDRESS_0, pcicsrbar); #endif - } else { - /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ - /* enabled = ltssm >= PCI_LTSSM_L0; */ - pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); - enabled = ltssm >= PCI_LTSSM_L0; - -#ifdef CONFIG_FSL_PCIE_RESET - if (ltssm == 1) { - int i; - debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); - /* assert PCIe reset */ - setbits_be32(&pci->pdb_stat, 0x08000000); - (void) in_be32(&pci->pdb_stat); - udelay(100); - debug(" Asserting PCIe reset @%p = %x\n", - &pci->pdb_stat, in_be32(&pci->pdb_stat)); - /* clear PCIe reset */ - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, - <ssm); - udelay(1000); - debug("....PCIe link error. " - "LTSSM=0x%02x.\n", ltssm); - } - enabled = ltssm >= PCI_LTSSM_L0; - - /* we need to re-write the bar0 since a reset will - * clear it - */ - pci_hose_write_config_dword(hose, dev, - PCI_BASE_ADDRESS_0, pcicsrbar); - } -#endif - } + enabled = fsl_pci_link_up(hose, pci_info);
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { @@ -502,19 +526,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) temp32 = in_be32(&srds_regs->srdspccr0);
if ((temp32 >> 28) == 3) { - int i; - out_be32(&srds_regs->srdspccr0, 2 << 28); - setbits_be32(&pci->pdb_stat, 0x08000000); - in_be32(&pci->pdb_stat); - udelay(100); - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); - udelay(1000); - } - enabled = ltssm >= PCI_LTSSM_L0; + fsl_do_pcie_reset(pci_info); + enabled = fsl_pci_link_up(hose, pci_info); } } #endif
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com --- arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose, pci_ltssm_l0 = PCI_LTSSM_L0;
ltssm = fsl_get_ltssm(hose, pci_info); - - if (ltssm == pci_ltssm_l0) { + if (ltssm == LTSSM_PCIE_DETECT_QUIET || + ltssm == LTSSM_PCIE_DETECT_ACTIVE) { + enabled = 0; + } else if (ltssm == pci_ltssm_l0) { enabled = 1; } else { - for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) { + for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000); } - enabled = ltssm >= pci_ltssm_l0; + enabled = (ltssm == pci_ltssm_l0) ? 1 : 0; }
return enabled;
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com
arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose, pci_ltssm_l0 = PCI_LTSSM_L0;
ltssm = fsl_get_ltssm(hose, pci_info);
if (ltssm == pci_ltssm_l0) {
if (ltssm == LTSSM_PCIE_DETECT_QUIET ||ltssm == LTSSM_PCIE_DETECT_ACTIVE) {enabled = 0;} else if (ltssm == pci_ltssm_l0) { enabled = 1; } else {
for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000);
Do you really need this long loop here ? It causes a long delay in case the PCIe device is in permanent polling state. Our device is in polling state until clocks is configured and that will be done from user space in Linux
}
enabled = ltssm >= pci_ltssm_l0;
enabled = (ltssm == pci_ltssm_l0) ? 1 : 0; } return enabled;-- 2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
-----Original Message----- From: Joakim Tjernlund [mailto:Joakim.Tjernlund@infinera.com] Sent: Friday, October 20, 2017 9:13 PM To: wd@denx.de; Mingkai Hu mingkai.hu@nxp.com; tony.obrien@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; York Sun york.sun@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; hamish.martin@alliedtelesis.co.nz; M.h. Lian minghuan.lian@nxp.com Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com
arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose, pci_ltssm_l0 = PCI_LTSSM_L0;
ltssm = fsl_get_ltssm(hose, pci_info);
if (ltssm == pci_ltssm_l0) {
if (ltssm == LTSSM_PCIE_DETECT_QUIET ||ltssm == LTSSM_PCIE_DETECT_ACTIVE) {enabled = 0;} else if (ltssm == pci_ltssm_l0) { enabled = 1; } else {
for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000);
Do you really need this long loop here ? It causes a long delay in case the PCIe device is in permanent polling state. Our device is in polling state until clocks is configured and that will be done from user space in Linux
Yes, if the pcie device is in permanent polling state, it will take probably 100ms delay, but this case is occur very few special devices, if we want to use the pcie device in uboot, we have to wait the device link up state is ok, so need some time to wait the pcie device ready. if the pcie slot have no device, the function will return at once, will not bring delay.
}
enabled = ltssm >= pci_ltssm_l0;
enabled = (ltssm == pci_ltssm_l0) ? 1 : 0; } return enabled;-- 2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 10/22/2017 07:39 PM, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund [mailto:Joakim.Tjernlund@infinera.com] Sent: Friday, October 20, 2017 9:13 PM To: wd@denx.de; Mingkai Hu mingkai.hu@nxp.com; tony.obrien@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; York Sun york.sun@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; hamish.martin@alliedtelesis.co.nz; M.h. Lian minghuan.lian@nxp.com Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com
arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose, pci_ltssm_l0 = PCI_LTSSM_L0;
ltssm = fsl_get_ltssm(hose, pci_info);
if (ltssm == pci_ltssm_l0) {
if (ltssm == LTSSM_PCIE_DETECT_QUIET ||ltssm == LTSSM_PCIE_DETECT_ACTIVE) {enabled = 0;} else if (ltssm == pci_ltssm_l0) { enabled = 1; } else {
for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000);Do you really need this long loop here ? It causes a long delay in case the PCIe device is in permanent polling state. Our device is in polling state until clocks is configured and that will be done from user space in Linux
Yes, if the pcie device is in permanent polling state, it will take probably 100ms delay, but this case is occur very few special devices, if we want to use the pcie device in uboot, we have to wait the device link up state is ok, so need some time to wait the pcie device ready. if the pcie slot have no device, the function will return at once, will not bring delay.
Joakim,
Are we OK with this change? Can you test it to make sure no negative impact on your boards?
York
On Wed, 2017-11-08 at 21:05 +0000, York Sun wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
On 10/22/2017 07:39 PM, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund [mailto:Joakim.Tjernlund@infinera.com] Sent: Friday, October 20, 2017 9:13 PM To: wd@denx.de; Mingkai Hu mingkai.hu@nxp.com; tony.obrien@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; York Sun york.sun@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; hamish.martin@alliedtelesis.co.nz; M.h. Lian minghuan.lian@nxp.com Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com
arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose, pci_ltssm_l0 = PCI_LTSSM_L0;
ltssm = fsl_get_ltssm(hose, pci_info);
if (ltssm == pci_ltssm_l0) {
if (ltssm == LTSSM_PCIE_DETECT_QUIET ||ltssm == LTSSM_PCIE_DETECT_ACTIVE) {enabled = 0;} else if (ltssm == pci_ltssm_l0) { enabled = 1; } else {
for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000);Do you really need this long loop here ? It causes a long delay in case the PCIe device is in permanent polling state. Our device is in polling state until clocks is configured and that will be done from user space in Linux
Yes, if the pcie device is in permanent polling state, it will take probably 100ms delay, but this case is occur very few special devices, if we want to use the pcie device in uboot, we have to wait the device link up state is ok, so need some time to wait the pcie device ready. if the pcie slot have no device, the function will return at once, will not bring delay.
Joakim,
Are we OK with this change? Can you test it to make sure no negative impact on your boards?
Not really happy, what device needs 100 ms extra to exit polling state?
On 11/08/2017 01:30 PM, Joakim Tjernlund wrote:
On Wed, 2017-11-08 at 21:05 +0000, York Sun wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
On 10/22/2017 07:39 PM, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund [mailto:Joakim.Tjernlund@infinera.com] Sent: Friday, October 20, 2017 9:13 PM To: wd@denx.de; Mingkai Hu mingkai.hu@nxp.com; tony.obrien@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; York Sun york.sun@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; hamish.martin@alliedtelesis.co.nz; M.h. Lian minghuan.lian@nxp.com Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com
arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller *hose, pci_ltssm_l0 = PCI_LTSSM_L0;
ltssm = fsl_get_ltssm(hose, pci_info);
if (ltssm == pci_ltssm_l0) {
if (ltssm == LTSSM_PCIE_DETECT_QUIET ||ltssm == LTSSM_PCIE_DETECT_ACTIVE) {enabled = 0;} else if (ltssm == pci_ltssm_l0) { enabled = 1; } else {
for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++) { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000);Do you really need this long loop here ? It causes a long delay in case the PCIe device is in permanent polling state. Our device is in polling state until clocks is configured and that will be done from user space in Linux
Yes, if the pcie device is in permanent polling state, it will take probably 100ms delay, but this case is occur very few special devices, if we want to use the pcie device in uboot, we have to wait the device link up state is ok, so need some time to wait the pcie device ready. if the pcie slot have no device, the function will return at once, will not bring delay.
Joakim,
Are we OK with this change? Can you test it to make sure no negative impact on your boards?
Not really happy, what device needs 100 ms extra to exit polling state?
Joakim,
I understand your concern. I don't like the delay either.
Xiaowei,
You said this only occur for very few special devices. Can you explain more? How can you avoid this delay for general cases?
York
-----Original Message----- From: York Sun Sent: Thursday, November 09, 2017 5:46 AM To: Joakim Tjernlund Joakim.Tjernlund@infinera.com; Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Mingkai Hu mingkai.hu@nxp.com; tony.obrien@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; hamish.martin@alliedtelesis.co.nz; M.h. Lian minghuan.lian@nxp.com Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific
On 11/08/2017 01:30 PM, Joakim Tjernlund wrote:
On Wed, 2017-11-08 at 21:05 +0000, York Sun wrote:
CAUTION: This email originated from outside of the organization. Do not
click links or open attachments unless you recognize the sender and know the content is safe.
On 10/22/2017 07:39 PM, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund [mailto:Joakim.Tjernlund@infinera.com] Sent: Friday, October 20, 2017 9:13 PM To: wd@denx.de; Mingkai Hu mingkai.hu@nxp.com; tony.obrien@alliedtelesis.co.nz; u-boot@lists.denx.de; Z.q. Hou zhiqiang.hou@nxp.com; York Sun york.sun@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; hamish.martin@alliedtelesis.co.nz; M.h. Lian minghuan.lian@nxp.com Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific
On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote:
CAUTION: This email originated from outside of the organization. Do not
click links or open attachments unless you recognize the sender and know the content is safe.
For some special reset times for longer pcie devices, the pcie device may on polling compliance state, the RC considers the pcie device is link up, but the pcie device is not link up, only the L0 state is link up state.
Signed-off-by: Bao Xiaowei xiaowei.bao@nxp.com
arch/powerpc/include/asm/fsl_pci.h | 2 ++ drivers/pci/fsl_pci_init.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 70a5461..323b182 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -25,6 +25,8 @@ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine
*/
#define PCI_LTSSM_L0 0x16 /* L0 state */ #define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/ +#define LTSSM_PCIE_DETECT_QUIET 0x00 /* Detect state */ +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index be57e53..9b5f386 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -335,15 +335,17 @@ static int fsl_pci_link_up(struct pci_controller
*hose,
pci_ltssm_l0 = PCI_LTSSM_L0; ltssm = fsl_get_ltssm(hose, pci_info);
if (ltssm == pci_ltssm_l0) {
if (ltssm == LTSSM_PCIE_DETECT_QUIET ||ltssm == LTSSM_PCIE_DETECT_ACTIVE) {enabled = 0;} else if (ltssm == pci_ltssm_l0) { enabled = 1; } else {
for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
for (i = 0; i < 100 && ltssm != pci_ltssm_l0; i++)- { ltssm = fsl_get_ltssm(hose, pci_info); udelay(1000);
Do you really need this long loop here ? It causes a long delay in case the PCIe device is in permanent polling state. Our device is in polling state until clocks is configured and that will be done from user space in Linux
Yes, if the pcie device is in permanent polling state, it will take probably
100ms delay, but this case is occur very few special devices, if we want to use the pcie device in uboot, we have to wait the device link up state is ok, so need some time to wait the pcie device ready. if the pcie slot have no device, the function will return at once, will not bring delay.
Joakim,
Are we OK with this change? Can you test it to make sure no negative impact on your boards?
Not really happy, what device needs 100 ms extra to exit polling state?
Joakim,
I understand your concern. I don't like the delay either.
Xiaowei,
You said this only occur for very few special devices. Can you explain more? How can you avoid this delay for general cases?
York
Hi York,
For the general pcie devices, it will not bring delay, because the RC access these devices can get the link up state correctly, usually, if the slot have the device, return the L0 state, if the slot have not device, return DETECT state, but for a few device, the initial phase it may be polling state(this issue is feedback from customer, we have not this device), After a period of time, the device resume the L0 state, so for this type of device, we need wait a moment, and about the 1 ms delay, It is estimate value, in other words, if this type device resume the L0 state within the 1ms, we consider that it is link up.
On 11/08/2017 10:45 PM, Xiaowei Bao wrote:
Hi York,
For the general pcie devices, it will not bring delay, because the RC access these devices can get the link up state correctly, usually, if the slot have the device, return the L0 state, if the slot have not device, return DETECT state, but for a few device, the initial phase it may be polling state(this issue is feedback from customer, we have not this device), After a period of time, the device resume the L0 state, so for this type of device, we need wait a moment, and about the 1 ms delay, It is estimate value, in other words, if this type device resume the L0 state within the 1ms, we consider that it is link up.
Joakim,
Do you accept this reasoning? Can you test on your hardware?
York
On 11/29/2017 10:48 AM, York Sun wrote:
On 11/08/2017 10:45 PM, Xiaowei Bao wrote:
Hi York,
For the general pcie devices, it will not bring delay, because the RC access these devices can get the link up state correctly, usually, if the slot have the device, return the L0 state, if the slot have not device, return DETECT state, but for a few device, the initial phase it may be polling state(this issue is feedback from customer, we have not this device), After a period of time, the device resume the L0 state, so for this type of device, we need wait a moment, and about the 1 ms delay, It is estimate value, in other words, if this type device resume the L0 state within the 1ms, we consider that it is link up.
Joakim,
Do you accept this reasoning? Can you test on your hardware?
Guys,
I don't think we agreed on this patch. We either continue to discuss, or I will have to drop this set.
York
participants (4)
-
Bao Xiaowei -
Joakim Tjernlund -
Xiaowei Bao
-
York Sun