[U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support
This series adds Intel FSP support to IvyBridge processor and Panther Point chipset (aka Chief River platform), and is validated on Intel Cougar Canyon 2 board.
This only adds basic features like serial, keyboard, RTC, timer, SPI, GPIO, PCI, SATA, USB. Other features will be enabled in future patch set.
Bin Meng (10): fdtdec: Add compatible string for Intel IvyBridge FSP x86: ivybridge: Add FSP support tools: microcode-tool: Support parsing header file with a license block x86: ivybridge: Add microcode blobs for all the steppings superio: Add SMSC SIO1007 driver x86: ivybridge: Do not require HAVE_INTEL_ME x86: fsp: Make sure HOB list is not overwritten by U-Boot x86: fsp: Always use hex numbers in the hob command output x86: ivybridge: Add macros for LPC decode ranges x86: Add Intel Cougar Canyon 2 board
arch/x86/cpu/ivybridge/Kconfig | 9 +- arch/x86/cpu/ivybridge/Makefile | 4 + arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++ arch/x86/cpu/ivybridge/ivybridge.c | 22 + arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 96 +++ arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++ arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++ arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++ arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 +++++++++++++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 ++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 + arch/x86/include/asm/arch-ivybridge/pch.h | 10 + arch/x86/lib/fsp/cmd_fsp.c | 4 +- arch/x86/lib/fsp/fsp_support.c | 27 + board/google/chromebook_link/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + board/intel/Kconfig | 9 + board/intel/cougarcanyon2/Kconfig | 25 + board/intel/cougarcanyon2/MAINTAINERS | 6 + board/intel/cougarcanyon2/Makefile | 7 + board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++ board/intel/cougarcanyon2/start.S | 9 + configs/cougarcanyon2_defconfig | 21 + drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++ include/configs/cougarcanyon2.h | 34 + include/fdtdec.h | 1 + include/smsc_sio1007.h | 115 ++++ lib/fdtdec.c | 1 + tools/microcode-tool.py | 14 + 31 files changed, 3158 insertions(+), 3 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/configs/cougarcanyon2.h create mode 100644 include/smsc_sio1007.h
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..c515a3c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -169,6 +169,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..002594d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..c515a3c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -169,6 +169,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_COUNT,}; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..002594d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
1.8.2.1
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
We should create an FSP uclass I think.
Hi Simon,
On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..c515a3c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -169,6 +169,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_COUNT,}; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..002594d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
1.8.2.1
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
We should create an FSP uclass I think.
Maybe, I will add this in my todo list for next release.
Regards, Bin
Hi Simon,
On Mon, Dec 21, 2015 at 10:33 AM, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..c515a3c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -169,6 +169,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_COUNT,}; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..002594d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
1.8.2.1
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
We should create an FSP uclass I think.
Maybe, I will add this in my todo list for next release.
I looked into the FSP uclass today. Looks if want to do this, we have to move x86_fsp_init() call to a much later phase, ie: after initf_dm() is called. I am afraid this does not bring us a bigger benefits. What do you think?
Regards, Bin
Hi Bin,
On 5 February 2016 at 21:29, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Mon, Dec 21, 2015 at 10:33 AM, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..c515a3c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -169,6 +169,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_COUNT,}; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..002594d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
1.8.2.1
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
We should create an FSP uclass I think.
Maybe, I will add this in my todo list for next release.
I looked into the FSP uclass today. Looks if want to do this, we have to move x86_fsp_init() call to a much later phase, ie: after initf_dm() is called. I am afraid this does not bring us a bigger benefits. What do you think?
Yes I suspect you are right. But we do want eventually move all this compat stuff into drivers. I'm not sure sure of the best approach yet. Let's keep an eye on it.
Regards, Simon
On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..c515a3c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -169,6 +169,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_COUNT,}; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..002594d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
1.8.2.1
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/next, thanks!
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/ivybridge/Kconfig | 8 ++++ arch/x86/cpu/ivybridge/Makefile | 4 ++ arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++ 6 files changed, 131 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 56abd8f..36b74c2 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -72,4 +72,12 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very slowly.
+config FSP_ADDR + hex + default 0xfff80000 + +config FSP_USE_UPD + bool + default n + endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efae..d74635e 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -4,6 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ #
+ifdef CONFIG_HAVE_FSP +obj-y += fsp_configs.o ivybridge.o +else obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o @@ -22,3 +25,4 @@ obj-y += sata.o obj-y += sdram.o obj-y += usb_ehci.o obj-y += usb_xhci.o +endif diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c new file mode 100644 index 0000000..5d8b814 --- /dev/null +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: Intel + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct platform_config *plat_config = &config->plat_config; + struct memory_config *mem_config = &config->mem_config; + const void *blob = gd->fdt_blob; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IVYBRIDGE_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + plat_config->enable_ht = + fdtdec_get_bool(blob, node, "fsp,enable-ht"); + plat_config->enable_turbo = + fdtdec_get_bool(blob, node, "fsp,enable-turbo"); + plat_config->enable_memory_down = + fdtdec_get_bool(blob, node, "fsp,enable-memory-down"); + plat_config->enable_fast_boot = + fdtdec_get_bool(blob, node, "fsp,enable-fast-boot"); + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->stack_top = config->common.stack_top - 32; + rt_buf->boot_mode = config->common.boot_mode; + rt_buf->plat_config = plat_config; + + if (plat_config->enable_memory_down) + rt_buf->mem_config = mem_config; + else + rt_buf->mem_config = NULL; +} diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c new file mode 100644 index 0000000..afe7e57 --- /dev/null +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/post.h> +#include <asm/processor.h> + +int arch_cpu_init(void) +{ + int ret; + + post_code(POST_CPU_INIT); + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h new file mode 100644 index 0000000..24e2f2f --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct platform_config { + u8 enable_ht; + u8 enable_turbo; + u8 enable_memory_down; + u8 enable_fast_boot; +}; + +/* + * Dummy structure for now as currently only SPD is verified in U-Boot. + * + * We can add the missing parameters when adding support on a board with + * memory down configuration. + */ +struct memory_config { + u8 dummy; +}; + +struct fsp_config_data { + struct fsp_cfg_common common; + struct platform_config plat_config; + struct memory_config mem_config; +}; + +struct fspinit_rtbuf { + u32 stack_top; + u32 boot_mode; + struct platform_config *plat_config; + struct memory_config *mem_config; +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h new file mode 100644 index 0000000..be9f055 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_VPD_H__ +#define __FSP_VPD_H__ + +/* IvyBridge FSP does not support VPD/UPD */ + +#endif
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 8 ++++ arch/x86/cpu/ivybridge/Makefile | 4 ++ arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++ 6 files changed, 131 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
One question: why do we need an Intel license on this code?
- Simon
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 8 ++++ arch/x86/cpu/ivybridge/Makefile | 4 ++ arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++ 6 files changed, 131 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
One question: why do we need an Intel license on this code?
It was a copy and paste from other platform (queensbay and baytrail) files. Do you think we should change it to GPLv2+?
Regards, Bin
Hi Bin,
On 20 December 2015 at 19:27, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 8 ++++ arch/x86/cpu/ivybridge/Makefile | 4 ++ arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++ 6 files changed, 131 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
One question: why do we need an Intel license on this code?
It was a copy and paste from other platform (queensbay and baytrail) files. Do you think we should change it to GPLv2+?
Hmm - is it using this license because it was written by Intel, or because you modified it from the FSP code that was written by Intel? If so, then I suppose it is reasonable to use the Intel license.
Regards, Simon
Hi Simon,
On Thu, Dec 24, 2015 at 12:44 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 20 December 2015 at 19:27, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 8 ++++ arch/x86/cpu/ivybridge/Makefile | 4 ++ arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++ 6 files changed, 131 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
One question: why do we need an Intel license on this code?
It was a copy and paste from other platform (queensbay and baytrail) files. Do you think we should change it to GPLv2+?
Hmm - is it using this license because it was written by Intel, or because you modified it from the FSP code that was written by Intel? If so, then I suppose it is reasonable to use the Intel license.
The file was not written by Intel. Current U-Boot implementation is our own. I will change the license in v2.
Regards, Bin
The microcode header files in the Intel Chief River FSP package have a license comment block. Update the microcode-tool to support parsing it and extract the license text to the .dtsi file.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
tools/microcode-tool.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py index 71c2e91..790c27e 100755 --- a/tools/microcode-tool.py +++ b/tools/microcode-tool.py @@ -95,9 +95,23 @@ def ParseHeaderFiles(fname_list): name = os.path.splitext(name)[0] data = [] with open(fname) as fd: + license_start = False + license_end = False for line in fd: line = line.rstrip()
+ if len(line) >= 2: + if line[0] == '/' and line[1] == '*': + license_start = True + continue + if line[0] == '*' and line[1] == '/': + license_end = True + continue + if license_start and not license_end: + # Ignore blank line + if len(line) > 0: + license_text.append(line) + continue # Omit anything after the last comma words = line.split(',')[:-1] data += [word + ',' for word in words]
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The microcode header files in the Intel Chief River FSP package have a license comment block. Update the microcode-tool to support parsing it and extract the license text to the .dtsi file.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
tools/microcode-tool.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The microcode header files in the Intel Chief River FSP package have a license comment block. Update the microcode-tool to support parsing it and extract the license text to the .dtsi file.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
tools/microcode-tool.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/next, thanks!
This adds microcode blobs created from Intel FSP package for the Chief River platform. They are for all the Ivy Bridge steppings: 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the 306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++ arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++ arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++ arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++ 4 files changed, 2472 insertions(+) create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi new file mode 100644 index 0000000..6b35c39 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi @@ -0,0 +1,554 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x8>; +intel,date-code = <0x5182011>; +intel,processor-signature = <0x306a2>; +intel,checksum = <0xa0e51feb>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x08000000 0x11201805 0xa2060300 + 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000 + 0x00200000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x08000000 + 0x00000000 0x00000000 0x17051120 0xd1070000 + 0x01000000 0xa2060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e + 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi new file mode 100644 index 0000000..c39fbd3 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9082011>; +intel,processor-signature = <0x306a4>; +intel,checksum = <0x7e23e5af>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200809 0xa4060300 + 0xafe5237e 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x07091120 0xd1080000 + 0x01000000 0xa4060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d + 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a5_00000007.dtsi new file mode 100644 index 0000000..de50372 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9092011>; +intel,processor-signature = <0x306a5>; +intel,checksum = <0x8e38731>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200909 0xa5060300 + 0x3187e308 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x08091120 0x71080000 + 0x01000000 0xa5060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631 + 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a8_00000010.dtsi new file mode 100644 index 0000000..0672ff1 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi @@ -0,0 +1,682 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x10>; +intel,date-code = <0x2202012>; +intel,processor-signature = <0x306a8>; +intel,checksum = <0xe44a4ef2>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x10000000 0x12202002 0xa8060300 + 0xf24e4ae4 0x01000000 0x12000000 0xd0270000 + 0x00280000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x10000000 + 0x00000000 0x00000000 0x17021220 0xe1090000 + 0x01000000 0xa8060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6 + 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
This adds microcode blobs created from Intel FSP package for the Chief River platform. They are for all the Ivy Bridge steppings: 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the 306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++ arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++ arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++ arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++ 4 files changed, 2472 insertions(+) create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
This adds microcode blobs created from Intel FSP package for the Chief River platform. They are for all the Ivy Bridge steppings: 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the 306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++ arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++ arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++ arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++ 4 files changed, 2472 insertions(+) create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/next, thanks!
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..6952f8ce 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..79e9e15 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h> + +static inline u8 sio1007_read(int port, int reg) +{ + outb(reg, port); + + return inb(port + 1); +} + +static inline void sio1007_write(int port, int reg, int val) +{ + outb(reg, port); + outb(val, port + 1); +} + +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{ + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); +} + +void sio1007_enable_serial(int port, int num, int iobase, int irq) +{ + if (num < 0 || num > SIO1007_UART_NUM) + return; + + /* enter configuration state */ + outb(0x55, port); + + /* power on serial port and set up its i/o base & irq */ + if (!num) { + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON); + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2); + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4); + } else { + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON); + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2); + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq); + } + + /* exit configuration state */ + outb(0xaa, port); +} + +void sio1007_enable_runtime(int port, int iobase) +{ + /* enter configuration state */ + outb(0x55, port); + + /* set i/o base for the runtime register block */ + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4); + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12); + /* turn on address decoding for this block */ + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN); + + /* exit configuration state */ + outb(0xaa, port); +} + +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{ + int reg = GPIO0_DIR; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DIR; + gpio -= GPIO_NUM_PER_GROUP; + } + + /* enter configuration state */ + outb(0x55, port); + + /* set gpio pin direction, polority and type */ + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio); + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio); + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio); + + /* exit configuration state */ + outb(0xaa, port); +} + +int sio1007_gpio_get_value(int port, int gpio) +{ + int reg = GPIO0_DATA; + int val; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return -EINVAL; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DATA; + gpio -= GPIO_NUM_PER_GROUP; + } + + val = inb(port + reg); + if (val & (1 << gpio)) + return 1; + else + return 0; +} + +void sio1007_gpio_set_value(int port, int gpio, int val) +{ + int reg = GPIO0_DATA; + u8 data; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DATA; + gpio -= GPIO_NUM_PER_GROUP; + } + + data = inb(port + reg); + data &= ~(1 << gpio); + data |= (val << gpio); + outb(data, port + reg); +} diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..eff57a7 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_ + +/* + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0 + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of + * SYSOPT0 and SYSOPT1 determines one of the following addresses. + */ +#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e + +/* SIO1007 registers */ + +#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7) + +#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28 + +#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30 + +#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1 + +#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1 + +#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1 + +#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1) + +/* Runtime register offset */ + +#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe + +/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2 + +/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM) + +/** + * Configure the I/O port address of the specified serial device and + * enable the serial device. + * + * @port: SIO1007 I/O port address + * @num: serial device number (0 or 1) + * @iobase: processor I/O port address to assign to this serial device + * @irq: processor IRQ number to assign to this serial device + */ +void sio1007_enable_serial(int port, int num, int iobase, int irq); + +/** + * Configure the I/O port address of the runtime register block and + * enable the address decoding. + * + * @port: SIO1007 I/O port address + * @iobase: processor I/O port address to assign to the runtime registers + */ +void sio1007_enable_runtime(int port, int iobase); + +/** + * Configure the direction/polority/type of a specified GPIO pin + * + * @port: SIO1007 I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT + * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT + * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN + */ +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type); + +/** + * Get a GPIO pin value. + * This will work whether the GPIO is an input or an output. + * + * @port: runtime register block I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid + */ +int sio1007_gpio_get_value(int port, int gpio); + +/** + * Set a GPIO pin value. + * This will only work when the GPIO is configured as an output. + * + * @port: runtime register block I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @val: 0 if low, 1 if high + */ +void sio1007_gpio_set_value(int port, int gpio, int val); + +#endif /* _SMSC_SIO1007_H_ */
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..6952f8ce 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..79e9e15 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h>
+static inline u8 sio1007_read(int port, int reg) +{
outb(reg, port);return inb(port + 1);+}
+static inline void sio1007_write(int port, int reg, int val) +{
outb(reg, port);outb(val, port + 1);+}
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{
sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);+}
+void sio1007_enable_serial(int port, int num, int iobase, int irq) +{
if (num < 0 || num > SIO1007_UART_NUM)return;/* enter configuration state */outb(0x55, port);/* power on serial port and set up its i/o base & irq */if (!num) {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);} else {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);}/* exit configuration state */outb(0xaa, port);+}
+void sio1007_enable_runtime(int port, int iobase) +{
/* enter configuration state */outb(0x55, port);/* set i/o base for the runtime register block */sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);/* turn on address decoding for this block */sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);/* exit configuration state */outb(0xaa, port);+}
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{
int reg = GPIO0_DIR;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DIR;gpio -= GPIO_NUM_PER_GROUP;}/* enter configuration state */outb(0x55, port);/* set gpio pin direction, polority and type */sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);/* exit configuration state */outb(0xaa, port);+}
+int sio1007_gpio_get_value(int port, int gpio) +{
int reg = GPIO0_DATA;int val;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return -EINVAL;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}val = inb(port + reg);if (val & (1 << gpio))return 1;elsereturn 0;+}
+void sio1007_gpio_set_value(int port, int gpio, int val) +{
int reg = GPIO0_DATA;u8 data;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}data = inb(port + reg);data &= ~(1 << gpio);data |= (val << gpio);outb(data, port + reg);+}
This should be modeled as a GPIO driver in the GPIO uclass.
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..eff57a7 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_
+/*
- The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
- and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
- SYSOPT0 and SYSOPT1 determines one of the following addresses.
- */
+#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e
+/* SIO1007 registers */
+#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7)
+#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28
+#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30
+#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1
+#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1
+#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1
+#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1)
+/* Runtime register offset */
+#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe
+/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2
+/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+/**
- Configure the I/O port address of the specified serial device and
- enable the serial device.
- @port: SIO1007 I/O port address
- @num: serial device number (0 or 1)
- @iobase: processor I/O port address to assign to this serial device
- @irq: processor IRQ number to assign to this serial device
- */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
I wonder if we need a parent device which provides access to these features, and then a GPIO child device?
+/**
- Configure the I/O port address of the runtime register block and
- enable the address decoding.
- @port: SIO1007 I/O port address
- @iobase: processor I/O port address to assign to the runtime registers
- */
+void sio1007_enable_runtime(int port, int iobase);
+/**
- Configure the direction/polority/type of a specified GPIO pin
- @port: SIO1007 I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
- @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
- @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
- */
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
+/**
- Get a GPIO pin value.
- This will work whether the GPIO is an input or an output.
- @port: runtime register block I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
- */
+int sio1007_gpio_get_value(int port, int gpio);
+/**
- Set a GPIO pin value.
- This will only work when the GPIO is configured as an output.
- @port: runtime register block I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @val: 0 if low, 1 if high
- */
+void sio1007_gpio_set_value(int port, int gpio, int val);
+#endif /* _SMSC_SIO1007_H_ */
1.8.2.1
Regards, Simon
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..6952f8ce 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..79e9e15 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h>
+static inline u8 sio1007_read(int port, int reg) +{
outb(reg, port);return inb(port + 1);+}
+static inline void sio1007_write(int port, int reg, int val) +{
outb(reg, port);outb(val, port + 1);+}
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{
sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);+}
+void sio1007_enable_serial(int port, int num, int iobase, int irq) +{
if (num < 0 || num > SIO1007_UART_NUM)return;/* enter configuration state */outb(0x55, port);/* power on serial port and set up its i/o base & irq */if (!num) {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);} else {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);}/* exit configuration state */outb(0xaa, port);+}
+void sio1007_enable_runtime(int port, int iobase) +{
/* enter configuration state */outb(0x55, port);/* set i/o base for the runtime register block */sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);/* turn on address decoding for this block */sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);/* exit configuration state */outb(0xaa, port);+}
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{
int reg = GPIO0_DIR;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DIR;gpio -= GPIO_NUM_PER_GROUP;}/* enter configuration state */outb(0x55, port);/* set gpio pin direction, polority and type */sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);/* exit configuration state */outb(0xaa, port);+}
+int sio1007_gpio_get_value(int port, int gpio) +{
int reg = GPIO0_DATA;int val;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return -EINVAL;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}val = inb(port + reg);if (val & (1 << gpio))return 1;elsereturn 0;+}
+void sio1007_gpio_set_value(int port, int gpio, int val) +{
int reg = GPIO0_DATA;u8 data;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}data = inb(port + reg);data &= ~(1 << gpio);data |= (val << gpio);outb(data, port + reg);+}
This should be modeled as a GPIO driver in the GPIO uclass.
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..eff57a7 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_
+/*
- The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
- and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
- SYSOPT0 and SYSOPT1 determines one of the following addresses.
- */
+#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e
+/* SIO1007 registers */
+#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7)
+#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28
+#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30
+#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1
+#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1
+#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1
+#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1)
+/* Runtime register offset */
+#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe
+/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2
+/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+/**
- Configure the I/O port address of the specified serial device and
- enable the serial device.
- @port: SIO1007 I/O port address
- @num: serial device number (0 or 1)
- @iobase: processor I/O port address to assign to this serial device
- @irq: processor IRQ number to assign to this serial device
- */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
I wonder if we need a parent device which provides access to these features, and then a GPIO child device?
I was thinking we create a superio uclass for this, but I found it's not generic enough to abstract the ops for this uclass, if we take a look at the existing SMSC LPC47M and this new one. Given these routines will only need to be called just once during boot up, I decided not to use driver model on this type of device.
+/**
- Configure the I/O port address of the runtime register block and
- enable the address decoding.
- @port: SIO1007 I/O port address
- @iobase: processor I/O port address to assign to the runtime registers
- */
+void sio1007_enable_runtime(int port, int iobase);
+/**
- Configure the direction/polority/type of a specified GPIO pin
- @port: SIO1007 I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
- @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
- @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
- */
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
+/**
- Get a GPIO pin value.
- This will work whether the GPIO is an input or an output.
- @port: runtime register block I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
- */
+int sio1007_gpio_get_value(int port, int gpio);
+/**
- Set a GPIO pin value.
- This will only work when the GPIO is configured as an output.
- @port: runtime register block I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @val: 0 if low, 1 if high
- */
+void sio1007_gpio_set_value(int port, int gpio, int val);
+#endif /* _SMSC_SIO1007_H_ */
1.8.2.1
Regards, Bin
Hi Bin,
On 20 December 2015 at 19:42, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..6952f8ce 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..79e9e15 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h>
+static inline u8 sio1007_read(int port, int reg) +{
outb(reg, port);return inb(port + 1);+}
+static inline void sio1007_write(int port, int reg, int val) +{
outb(reg, port);outb(val, port + 1);+}
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{
sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);+}
+void sio1007_enable_serial(int port, int num, int iobase, int irq) +{
if (num < 0 || num > SIO1007_UART_NUM)return;/* enter configuration state */outb(0x55, port);/* power on serial port and set up its i/o base & irq */if (!num) {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);} else {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);}/* exit configuration state */outb(0xaa, port);+}
+void sio1007_enable_runtime(int port, int iobase) +{
/* enter configuration state */outb(0x55, port);/* set i/o base for the runtime register block */sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);/* turn on address decoding for this block */sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);/* exit configuration state */outb(0xaa, port);+}
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{
int reg = GPIO0_DIR;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DIR;gpio -= GPIO_NUM_PER_GROUP;}/* enter configuration state */outb(0x55, port);/* set gpio pin direction, polority and type */sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);/* exit configuration state */outb(0xaa, port);+}
+int sio1007_gpio_get_value(int port, int gpio) +{
int reg = GPIO0_DATA;int val;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return -EINVAL;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}val = inb(port + reg);if (val & (1 << gpio))return 1;elsereturn 0;+}
+void sio1007_gpio_set_value(int port, int gpio, int val) +{
int reg = GPIO0_DATA;u8 data;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}data = inb(port + reg);data &= ~(1 << gpio);data |= (val << gpio);outb(data, port + reg);+}
This should be modeled as a GPIO driver in the GPIO uclass.
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..eff57a7 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_
+/*
- The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
- and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
- SYSOPT0 and SYSOPT1 determines one of the following addresses.
- */
+#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e
+/* SIO1007 registers */
+#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7)
+#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28
+#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30
+#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1
+#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1
+#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1
+#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1)
+/* Runtime register offset */
+#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe
+/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2
+/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+/**
- Configure the I/O port address of the specified serial device and
- enable the serial device.
- @port: SIO1007 I/O port address
- @num: serial device number (0 or 1)
- @iobase: processor I/O port address to assign to this serial device
- @irq: processor IRQ number to assign to this serial device
- */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
I wonder if we need a parent device which provides access to these features, and then a GPIO child device?
I was thinking we create a superio uclass for this, but I found it's not generic enough to abstract the ops for this uclass, if we take a look at the existing SMSC LPC47M and this new one. Given these routines will only need to be called just once during boot up, I decided not to use driver model on this type of device.
But won't we want to use the 'gpio' command to access these GPIOs?
+/**
- Configure the I/O port address of the runtime register block and
- enable the address decoding.
- @port: SIO1007 I/O port address
- @iobase: processor I/O port address to assign to the runtime registers
- */
+void sio1007_enable_runtime(int port, int iobase);
+/**
- Configure the direction/polority/type of a specified GPIO pin
- @port: SIO1007 I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
- @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
- @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
- */
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
+/**
- Get a GPIO pin value.
- This will work whether the GPIO is an input or an output.
- @port: runtime register block I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
- */
+int sio1007_gpio_get_value(int port, int gpio);
+/**
- Set a GPIO pin value.
- This will only work when the GPIO is configured as an output.
- @port: runtime register block I/O port address
- @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
- @val: 0 if low, 1 if high
- */
+void sio1007_gpio_set_value(int port, int gpio, int val);
+#endif /* _SMSC_SIO1007_H_ */
1.8.2.1
Regards, Bin
Regards, Simon
Hi Simon,
On Wed, Jan 6, 2016 at 8:24 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 20 December 2015 at 19:42, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..6952f8ce 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..79e9e15 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h>
+static inline u8 sio1007_read(int port, int reg) +{
outb(reg, port);return inb(port + 1);+}
+static inline void sio1007_write(int port, int reg, int val) +{
outb(reg, port);outb(val, port + 1);+}
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{
sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);+}
+void sio1007_enable_serial(int port, int num, int iobase, int irq) +{
if (num < 0 || num > SIO1007_UART_NUM)return;/* enter configuration state */outb(0x55, port);/* power on serial port and set up its i/o base & irq */if (!num) {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);} else {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);}/* exit configuration state */outb(0xaa, port);+}
+void sio1007_enable_runtime(int port, int iobase) +{
/* enter configuration state */outb(0x55, port);/* set i/o base for the runtime register block */sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);/* turn on address decoding for this block */sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);/* exit configuration state */outb(0xaa, port);+}
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{
int reg = GPIO0_DIR;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DIR;gpio -= GPIO_NUM_PER_GROUP;}/* enter configuration state */outb(0x55, port);/* set gpio pin direction, polority and type */sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);/* exit configuration state */outb(0xaa, port);+}
+int sio1007_gpio_get_value(int port, int gpio) +{
int reg = GPIO0_DATA;int val;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return -EINVAL;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}val = inb(port + reg);if (val & (1 << gpio))return 1;elsereturn 0;+}
+void sio1007_gpio_set_value(int port, int gpio, int val) +{
int reg = GPIO0_DATA;u8 data;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}data = inb(port + reg);data &= ~(1 << gpio);data |= (val << gpio);outb(data, port + reg);+}
This should be modeled as a GPIO driver in the GPIO uclass.
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..eff57a7 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_
+/*
- The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
- and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
- SYSOPT0 and SYSOPT1 determines one of the following addresses.
- */
+#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e
+/* SIO1007 registers */
+#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7)
+#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28
+#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30
+#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1
+#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1
+#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1
+#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1)
+/* Runtime register offset */
+#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe
+/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2
+/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+/**
- Configure the I/O port address of the specified serial device and
- enable the serial device.
- @port: SIO1007 I/O port address
- @num: serial device number (0 or 1)
- @iobase: processor I/O port address to assign to this serial device
- @irq: processor IRQ number to assign to this serial device
- */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
I wonder if we need a parent device which provides access to these features, and then a GPIO child device?
I was thinking we create a superio uclass for this, but I found it's not generic enough to abstract the ops for this uclass, if we take a look at the existing SMSC LPC47M and this new one. Given these routines will only need to be called just once during boot up, I decided not to use driver model on this type of device.
But won't we want to use the 'gpio' command to access these GPIOs?
I don't see value of accessing them after boot. Also as you can see, these superio chipsets are really not good candidates to model. To operate on a specific GPIO pin, we need access two IO ports which looks quite weird, but unfortunately that is how the chipset was designed :(
[snip]
Regards, Bin
Hi Bin,
On 26 January 2016 at 01:29, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Jan 6, 2016 at 8:24 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 20 December 2015 at 19:42, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..6952f8ce 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..79e9e15 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h>
+static inline u8 sio1007_read(int port, int reg) +{
outb(reg, port);return inb(port + 1);+}
+static inline void sio1007_write(int port, int reg, int val) +{
outb(reg, port);outb(val, port + 1);+}
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{
sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);+}
+void sio1007_enable_serial(int port, int num, int iobase, int irq) +{
if (num < 0 || num > SIO1007_UART_NUM)return;/* enter configuration state */outb(0x55, port);/* power on serial port and set up its i/o base & irq */if (!num) {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);} else {sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);}/* exit configuration state */outb(0xaa, port);+}
+void sio1007_enable_runtime(int port, int iobase) +{
/* enter configuration state */outb(0x55, port);/* set i/o base for the runtime register block */sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);/* turn on address decoding for this block */sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);/* exit configuration state */outb(0xaa, port);+}
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{
int reg = GPIO0_DIR;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DIR;gpio -= GPIO_NUM_PER_GROUP;}/* enter configuration state */outb(0x55, port);/* set gpio pin direction, polority and type */sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);/* exit configuration state */outb(0xaa, port);+}
+int sio1007_gpio_get_value(int port, int gpio) +{
int reg = GPIO0_DATA;int val;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return -EINVAL;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}val = inb(port + reg);if (val & (1 << gpio))return 1;elsereturn 0;+}
+void sio1007_gpio_set_value(int port, int gpio, int val) +{
int reg = GPIO0_DATA;u8 data;if (gpio < 0 || gpio > SIO1007_GPIO_NUM)return;if (gpio >= GPIO_NUM_PER_GROUP) {reg = GPIO1_DATA;gpio -= GPIO_NUM_PER_GROUP;}data = inb(port + reg);data &= ~(1 << gpio);data |= (val << gpio);outb(data, port + reg);+}
This should be modeled as a GPIO driver in the GPIO uclass.
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..eff57a7 --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_
+/*
- The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
- and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
- SYSOPT0 and SYSOPT1 determines one of the following addresses.
- */
+#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e
+/* SIO1007 registers */
+#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7)
+#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28
+#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30
+#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1
+#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1
+#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1
+#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1)
+/* Runtime register offset */
+#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe
+/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2
+/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+/**
- Configure the I/O port address of the specified serial device and
- enable the serial device.
- @port: SIO1007 I/O port address
- @num: serial device number (0 or 1)
- @iobase: processor I/O port address to assign to this serial device
- @irq: processor IRQ number to assign to this serial device
- */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
I wonder if we need a parent device which provides access to these features, and then a GPIO child device?
I was thinking we create a superio uclass for this, but I found it's not generic enough to abstract the ops for this uclass, if we take a look at the existing SMSC LPC47M and this new one. Given these routines will only need to be called just once during boot up, I decided not to use driver model on this type of device.
But won't we want to use the 'gpio' command to access these GPIOs?
I don't see value of accessing them after boot. Also as you can see, these superio chipsets are really not good candidates to model. To operate on a specific GPIO pin, we need access two IO ports which looks quite weird, but unfortunately that is how the chipset was designed :(
I'm not sure why the access method matters, and I don't understand why a GPIO would only be used on boot. But clearly you do, so I'm OK with it.
[snip]
Regards, Bin
Regards, Simon
Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/ivybridge/Kconfig | 1 - board/google/chromebook_link/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + 3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 36b74c2..b9f290a 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select HAVE_INTEL_ME select X86_RAMTEST
config SMM_TSEG_SIZE diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 6b13939..fa12f33 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index ae96d23..2af3aa9 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 1 - board/google/chromebook_link/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + 3 files changed, 2 insertions(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 1 - board/google/chromebook_link/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + 3 files changed, 2 insertions(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/next, thanks!
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail.
To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 875c96a..d6bbe1a 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -223,7 +223,9 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) { const struct hob_header *hdr; struct hob_res_desc *res_desc; + struct hob_mem_alloc *res_mem; phys_addr_t phys_start; + phys_addr_t mem_base = 0; u32 top;
/* Get the HOB list for processing */ @@ -242,9 +244,34 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) top += (u32)(res_desc->len); } } + + /* + * Find out the lowest memory base address allocated by FSP + * for the boot service data + */ + if (hdr->type == HOB_TYPE_MEM_ALLOC) { + res_mem = (struct hob_mem_alloc *)hdr; + if (!mem_base) + mem_base = res_mem->mem_base; + if (res_mem->mem_base < mem_base) + mem_base = res_mem->mem_base; + } + hdr = get_next_hob(hdr); }
+ /* + * Check whether the memory top address is below the FSP HOB list. + * If not, use the lowest memory base address allocated by FSP as + * the memory top address. This is to prevent U-Boot relocation + * overwrites the important boot service data which is used by FSP, + * otherwise the subsequent call to fsp_notify() will fail. + */ + if (top > (u32)hob_list) { + debug("Adjust memory top address due to a buggy FSP\n"); + top = (u32)mem_base; + } + return top; }
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail.
To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
But if this is a bug I'd prefer to have it behind an #iffdef, or with a large comment in the code. Otherwise we might think it is an important feature for all platforms.
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 875c96a..d6bbe1a 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -223,7 +223,9 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) { const struct hob_header *hdr; struct hob_res_desc *res_desc;
struct hob_mem_alloc *res_mem; phys_addr_t phys_start;phys_addr_t mem_base = 0; u32 top; /* Get the HOB list for processing */@@ -242,9 +244,34 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) top += (u32)(res_desc->len); } }
/** Find out the lowest memory base address allocated by FSP* for the boot service data*/if (hdr->type == HOB_TYPE_MEM_ALLOC) {res_mem = (struct hob_mem_alloc *)hdr;if (!mem_base)mem_base = res_mem->mem_base;if (res_mem->mem_base < mem_base)mem_base = res_mem->mem_base;}hdr = get_next_hob(hdr); }/** Check whether the memory top address is below the FSP HOB list.* If not, use the lowest memory base address allocated by FSP as* the memory top address. This is to prevent U-Boot relocation* overwrites the important boot service data which is used by FSP,* otherwise the subsequent call to fsp_notify() will fail.*/if (top > (u32)hob_list) {debug("Adjust memory top address due to a buggy FSP\n");top = (u32)mem_base;}return top;}
-- 1.8.2.1
Regards, Simon
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail.
To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
But if this is a bug I'd prefer to have it behind an #iffdef, or with a large comment in the code. Otherwise we might think it is an important feature for all platforms.
Yep, will change to use #ifdef in v2.
Regards, Bin
In the 'fsp hob' command output, decimal numbers and hexadecimal numbers are used mixedly. Now change to always use hex numbers to keep consistency.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/lib/fsp/cmd_fsp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c index 4959edf..2554663 100644 --- a/arch/x86/lib/fsp/cmd_fsp.c +++ b/arch/x86/lib/fsp/cmd_fsp.c @@ -69,7 +69,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("---|----------|-----------|------|-"); printf("------------------------------------------\n"); while (!end_of_hob(hdr)) { - printf("%-2d | %08x | ", i, (unsigned int)hdr); + printf("%02x | %08x | ", i, (unsigned int)hdr); type = hdr->type; if (type == HOB_TYPE_UNUSED) desc = "*Unused*"; @@ -79,7 +79,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) desc = hob_type[type]; else desc = "*Invalid*"; - printf("%-9s | %-4d | ", desc, hdr->len); + printf("%-9s | %04x | ", desc, hdr->len);
if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || type == HOB_TYPE_GUID_EXT) {
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
In the 'fsp hob' command output, decimal numbers and hexadecimal numbers are used mixedly. Now change to always use hex numbers to keep consistency.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/lib/fsp/cmd_fsp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
In the 'fsp hob' command output, decimal numbers and hexadecimal numbers are used mixedly. Now change to always use hex numbers to keep consistency.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/lib/fsp/cmd_fsp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/next, thanks!
Add several macros for LPC decode registers on PCH.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083..31437c8 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GPIO_ROUT 0xb8
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ +#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ @@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) +#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ +#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ +#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ +#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ +#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ +#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ +#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ +#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
/* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Add several macros for LPC decode registers on PCH.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
Add several macros for LPC decode registers on PCH.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/next, thanks!
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 96 +++++++++++++++++++++++++++++++ board/intel/Kconfig | 9 +++ board/intel/cougarcanyon2/Kconfig | 25 ++++++++ board/intel/cougarcanyon2/MAINTAINERS | 6 ++ board/intel/cougarcanyon2/Makefile | 7 +++ board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++ board/intel/cougarcanyon2/start.S | 9 +++ configs/cougarcanyon2_defconfig | 21 +++++++ include/configs/cougarcanyon2.h | 34 +++++++++++ 10 files changed, 256 insertions(+) create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 include/configs/cougarcanyon2.h
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 64e5694..84feb19 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -5,6 +5,7 @@ dtb-y += bayleybay.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ + cougarcanyon2.dtb \ crownbay.dtb \ efi.dtb \ galileo.dtb \ diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts new file mode 100644 index 0000000..486999e --- /dev/null +++ b/arch/x86/dts/cougarcanyon2.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Cougar Canyon 2"; + compatible = "intel,cougarcanyon2", "intel,chiefriver"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + microcode { + update@0 { +#include "microcode/m12306a2_00000008.dtsi" + }; + update@1 { +#include "microcode/m12306a4_00000007.dtsi" + }; + update@2 { +#include "microcode/m12306a5_00000007.dtsi" + }; + update@3 { +#include "microcode/m12306a8_00000010.dtsi" + }; + update@4 { +#include "microcode/m12306a9_0000001b.dtsi" + }; + }; + + fsp { + compatible = "intel,ivybridge-fsp"; + fsp,enable-ht; + }; + + pci { + #address-cells = <3>; + #size-cells = <2>; + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64bv", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + +}; diff --git a/board/intel/Kconfig b/board/intel/Kconfig index f7d71c3..4d341aa 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, PCIe and some other sensor interfaces.
+config TARGET_COUGARCANYON2 + bool "Cougar Canyon 2" + help + This is the Intel Cougar Canyon 2 Customer Reference Board. It + is built on the Chief River platform with Intel Ivybridge Processor + and Panther Point chipset. The board has 4GB RAM, with some other + peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI. + config TARGET_CROWNBAY bool "Crown Bay" help @@ -54,6 +62,7 @@ config TARGET_MINNOWMAX endchoice
source "board/intel/bayleybay/Kconfig" +source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig new file mode 100644 index 0000000..95a617b --- /dev/null +++ b/board/intel/cougarcanyon2/Kconfig @@ -0,0 +1,25 @@ +if TARGET_COUGARCANYON2 + +config SYS_BOARD + default "cougarcanyon2" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "cougarcanyon2" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_FSP + select BOARD_ROMSIZE_KB_2048 + +endif diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS new file mode 100644 index 0000000..a486739 --- /dev/null +++ b/board/intel/cougarcanyon2/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL COUGAR CANYON 2 BOARD +M: Bin Meng bmeng.cn@gmail.com +S: Maintained +F: board/intel/cougarcanyon2/ +F: include/configs/cougarcanyon2.h +F: configs/cougarcanyon2_defconfig diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile new file mode 100644 index 0000000..807f284 --- /dev/null +++ b/board/intel/cougarcanyon2/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cougarcanyon2.o start.o diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c new file mode 100644 index 0000000..4cc47fb --- /dev/null +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/ibmpc.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> +#include <pci.h> +#include <smsc_sio1007.h> + +#define SIO1007_RUNTIME_IOPORT 0x180 + +int board_early_init_f(void) +{ + /* Initialize LPC interface to turn on superio chipset decode range */ + x86_pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, + COMA_DEC_RANGE | COMB_DEC_RANGE); + x86_pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | COMA_LPC_EN); + x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | + (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN); + x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | + SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN); + + /* Enable legacy serial port at 0x3f8 */ + sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ); + + /* Enable SIO1007 runtime I/O port at 0x180 */ + sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT); + + /* + * On Cougar Canyon 2 board, the RS232 transiver connected to serial + * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007. + * Set the pin value to 1 to enable the RS232 transiver. + */ + sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT, + GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL); + sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S new file mode 100644 index 0000000..a71db69 --- /dev/null +++ b/board/intel/cougarcanyon2/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig new file mode 100644 index 0000000..2d23dc3 --- /dev/null +++ b/configs/cougarcanyon2_defconfig @@ -0,0 +1,21 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" +CONFIG_TARGET_COUGARCANYON2=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_VSNPRINTF=y diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h new file mode 100644 index 0000000..faac552 --- /dev/null +++ b/include/configs/cougarcanyon2.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (2 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SMSC_SIO1007 + +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +/* Environment configuration */ +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x5ff000 + +/* Video is not supported for now */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 96 +++++++++++++++++++++++++++++++ board/intel/Kconfig | 9 +++ board/intel/cougarcanyon2/Kconfig | 25 ++++++++ board/intel/cougarcanyon2/MAINTAINERS | 6 ++ board/intel/cougarcanyon2/Makefile | 7 +++ board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++ board/intel/cougarcanyon2/start.S | 9 +++ configs/cougarcanyon2_defconfig | 21 +++++++ include/configs/cougarcanyon2.h | 34 +++++++++++ 10 files changed, 256 insertions(+) create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 include/configs/cougarcanyon2.h
Acked-by: Simon Glass sjg@chromium.org
A few nits though: - Include order - <asm/... should go after the normal includes - can we drop the calls to x86_pci_...? Please check it on top of the u-boot-dm/pcif-working series
- Simon
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng bmeng.cn@gmail.com wrote:
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 96 +++++++++++++++++++++++++++++++ board/intel/Kconfig | 9 +++ board/intel/cougarcanyon2/Kconfig | 25 ++++++++ board/intel/cougarcanyon2/MAINTAINERS | 6 ++ board/intel/cougarcanyon2/Makefile | 7 +++ board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++ board/intel/cougarcanyon2/start.S | 9 +++ configs/cougarcanyon2_defconfig | 21 +++++++ include/configs/cougarcanyon2.h | 34 +++++++++++ 10 files changed, 256 insertions(+) create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 include/configs/cougarcanyon2.h
Acked-by: Simon Glass sjg@chromium.org
A few nits though:
- Include order - <asm/... should go after the normal includes
- can we drop the calls to x86_pci_...? Please check it on top of the
u-boot-dm/pcif-working series
Yep, I plan to do v2 after all your previous DM patches are applied.
Regards, Bin
participants (2)
-
Bin Meng -
Simon Glass