The CoreNet style platforms can have a L3 cache that fronts the memory controllers. Enable that cache as well as add information into the device tree about it.

Signed-off-by: Kumar Gala galak@kernel.crashing.org Signed-off-by: Dave Liu daveliu@freescale.com Signed-off-by: Becky Bruce beckyb@kernel.crashing.org Signed-off-by: Roy Zang tie-fei.zang@freescale.com Signed-off-by: Timur Tabi timur@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 45 ++++++++++++++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/fdt.c | 24 ++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e957677..b257a0f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -127,6 +127,44 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif

+#ifdef CONFIG_SYS_FSL_CPC +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + + out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); + /* Read back to sync write */ + in_be32(&cpc->cpccsr0); + + } + + printf("Corenet Platform Cache: %d KB enabled\n", size); +} + +void invalidate_cpc(void) +{ + int i; + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* Flash invalidate the CPC and clear all the locks */ + out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); + while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) + ; + } +} +#else +#define enable_cpc() +#define invalidate_cpc() +#endif /* CONFIG_SYS_FSL_CPC */ + /* * Breathe some life into the CPU... * @@ -242,6 +280,9 @@ void cpu_init_f (void) corenet_tb_init(); #endif init_used_tlb_cams(); + + /* Invalidate the CPC before DDR gets enabled */ + invalidate_cpc(); }

@@ -252,7 +293,6 @@ void cpu_init_f (void) * use the same bit-encoding as the older 8555, etc, parts. * */ - int cpu_init_r(void) { #ifdef CONFIG_SYS_LBC_LCRR @@ -373,6 +413,9 @@ int cpu_init_r(void) #else puts("disabled\n"); #endif + + enable_cpc(); + #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ qe_init(qe_base); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 932466e..6c5fb36 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/processor.h> #include <linux/ctype.h> +#include <asm/io.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif @@ -80,7 +81,30 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif

+#ifdef CONFIG_SYS_FSL_CPC +static inline void ft_fixup_l3cache(void *blob, int off) +{ + u32 line_size, num_ways, size, num_sets; + cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; + u32 cfg0 = in_be32(&cpc->cpccfg0); + + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + num_ways = CPC_CFG0_NUM_WAYS(cfg0); + line_size = CPC_CFG0_LINE_SZ(cfg0); + num_sets = size / (line_size * num_ways); + + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 3); +#ifdef CONFIG_SYS_CACHE_STASHING + fdt_setprop_cell(blob, off, "cache-stash-id", 1); +#endif +} +#else #define ft_fixup_l3cache(x, y) +#endif

#if defined(CONFIG_L2_CACHE) /* return size in kilobytes */