[U-Boot] [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms
Includes changes in u-boot framework to support TF-A for NXP Chassis 2 platforms. A new defconfig is added namely ls*_ram_defconfig which will be used for all boot sources when TF-A is used.
Tested on LS1043A, LS1046A and LS1012A platforms.
Changes in v2: - Patch subject and description changes - Removed extra CONFIG_TFABOOT flag usage - Merged board specific TFA boot support patches - Checked compilation using buildman tool for each commit
Pankit Garg (5): armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 drivers: ifc: dynamic chipselect mapping support armv8: fsl-layerscape: bootcmd identification for TFABOOT armv8: fsl-layerscape: add support of MC framework for TFA armv8: sec_firmware: return job ring status as true in TFABOOT
Rajesh Bhagat (18): env: allow flash and nand env driver to compile together env: sf: define API to override sf environment address env: nand: remove unnecessary env_ptr definition driver/ifc: replace __ilog2 with LOG2 macro armv8: fsl-layerscape: identify boot source from PORSR register armv8: layerscape: remove EL3 specific erratas for TFABOOT armv8: layerscape: secure boot support for environment selection armv8: layerscape: add SMC calls for DDR size and bank info armv8: layerscape: skip OCRAM init for TFABOOT armv8: sec_firmware: change el2_to_aarch32 SMC ID net: fm: add TFABOOT support drivers: qe: add TFABOOT support armv8: ls1046ardb: Add TFABOOT support armv8: ls1046aqds: Add TFABOOT support armv8: ls1043ardb: Add TFABOOT support armv8: ls1043aqds: Add TFABOOT support armv8: ls1012ardb: Add TFABOOT support armv8: ls1012aqds: Add TFABOOT support
Vinitha V Pillai (7): armv8: ls1046ardb: Add TFABOOT defconfig for secure boot armv8: ls1046aqds: Add TFABOOT defconfig for secure boot armv8: ls1043ardb: Add TFABOOT defconfig for secure boot armv8: ls1043aqds: Add TFABOOT defconfig for secure boot armv8: ls1012ardb: Add TFABOOT defconfig for secure boot armv8: ls1012aqds: Add TFABOOT defconfig for secure boot armv8: ls1012a: fix ls1012aqds secure boot compilation
York Sun (3): move data structure out of cpu.h armv8: layerscape: Enable routing SError exception armv8: fsl-layerscape: Update parsing boot source
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 31 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 613 +++++++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 12 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 128 ++++ arch/arm/cpu/armv8/sec_firmware.c | 4 + arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 --------- .../asm/arch-fsl-layerscape/immap_lsch2.h | 20 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 49 ++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 22 + board/freescale/ls1012aqds/Kconfig | 10 + board/freescale/ls1012aqds/ls1012aqds.c | 23 +- board/freescale/ls1012ardb/Kconfig | 4 + board/freescale/ls1012ardb/ls1012ardb.c | 16 +- board/freescale/ls1043aqds/ddr.c | 11 + board/freescale/ls1043aqds/ls1043aqds.c | 147 ++++- board/freescale/ls1043ardb/ddr.c | 14 + board/freescale/ls1043ardb/ls1043ardb.c | 110 ++++ board/freescale/ls1046aqds/ddr.c | 11 + board/freescale/ls1046aqds/ls1046aqds.c | 148 ++++- board/freescale/ls1046ardb/ddr.c | 12 + configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 65 ++ configs/ls1012aqds_tfa_defconfig | 62 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 63 ++ configs/ls1012ardb_tfa_defconfig | 56 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 58 ++ configs/ls1043aqds_tfa_defconfig | 54 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 51 ++ configs/ls1043ardb_tfa_defconfig | 49 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 58 ++ configs/ls1046aqds_tfa_defconfig | 57 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 52 ++ configs/ls1046ardb_tfa_defconfig | 49 ++ drivers/misc/fsl_ifc.c | 488 ++++++++++---- drivers/net/fm/fm.c | 102 ++- drivers/qe/qe.c | 81 +++ env/flash.c | 4 +- env/nand.c | 6 +- env/sf.c | 9 +- include/configs/B4860QDS.h | 2 +- include/configs/T102xQDS.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T4240QDS.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/ls1012a_common.h | 16 +- include/configs/ls1012aqds.h | 1 + include/configs/ls1012ardb.h | 6 + include/configs/ls1043a_common.h | 27 +- include/configs/ls1043aqds.h | 50 +- include/configs/ls1043ardb.h | 29 + include/configs/ls1046a_common.h | 12 + include/configs/ls1046aqds.h | 59 +- include/configs/ls1046ardb.h | 15 + include/environment.h | 1 - include/fsl_ifc.h | 27 +- 56 files changed, 2819 insertions(+), 487 deletions(-) create mode 100644 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1012aqds_tfa_defconfig create mode 100644 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1012ardb_tfa_defconfig create mode 100644 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1043aqds_tfa_defconfig create mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1043ardb_tfa_defconfig create mode 100644 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1046aqds_tfa_defconfig create mode 100644 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1046ardb_tfa_defconfig
From: York Sun york.sun@nxp.com
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun york.sun@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 +++++++++++++++++ .../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 ------------------ 2 files changed, 297 insertions(+), 300 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 052e0708d4..bae50f68d8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -33,6 +33,303 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct cpu_type cpu_type_list[] = { + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), + CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), + CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), + CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), + CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), + CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), + CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), +}; + +#define EARLY_PGTABLE_SIZE 0x5000 +static struct mm_region early_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, +#ifdef CONFIG_FSL_IFC + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#ifdef CONFIG_FSL_IFC + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif + {}, /* list terminator */ +}; + +static struct mm_region final_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_ARCH_LS2080A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, + CONFIG_SYS_FSL_BOOTROM_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + {}, /* space holder for secure mem */ +#endif + {}, +}; + struct mm_region *mem_map = early_map;
void cpu_name(char *name) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 48d0ab163a..3926aa3039 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -7,30 +7,6 @@ #ifndef _FSL_LAYERSCAPE_CPU_H #define _FSL_LAYERSCAPE_CPU_H
-static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), - CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), - CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), - CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), - CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), - CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), - CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), - CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), - CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), - CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), - CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), - CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), - CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), - CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), - CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), - CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), - CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), - CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), - CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), -}; - -#ifndef CONFIG_SYS_DCACHE_OFF - #ifdef CONFIG_FSL_LSCH3 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 @@ -90,282 +66,6 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif
-#define EARLY_PGTABLE_SIZE 0x5000 -static struct mm_region early_map[] = { -#ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, -#ifdef CONFIG_FSL_IFC - /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | -#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | -#endif - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | -#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | -#endif - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#endif - {}, /* list terminator */ -}; - -static struct mm_region final_map[] = { -#ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_ARCH_LS2080A - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - {}, /* space holder for secure mem */ -#endif - {}, -}; -#endif /* !CONFIG_SYS_DCACHE_OFF */ - int fsl_qoriq_core_to_cluster(unsigned int core); u32 cpu_mask(void);
On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
From: York Sun york.sun@nxp.com
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun york.sun@nxp.com
Change in v2: None
Rajesh,
Did you send your patch set twice? I received two copies. The first one has Message-Id: 20181007095929.17876-2-rajesh.bhagat@nxp.com, sent on 7 Oct 2018 15:28:57 +0530. The second one has Message-Id: 20181007102131.19159-2-rajesh.bhagat@nxp.com, sent on 7 Oct 2018 15:50:59 +0530. You also sent two copies of your v1 patch. Please do not send more than one. If some error happened and you have to send them again, make sure you put "resend" in the subject to be easily identified.
York
-----Original Message----- From: York Sun Sent: Monday, October 8, 2018 8:08 PM To: Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH v2 01/33] move data structure out of cpu.h
On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
From: York Sun york.sun@nxp.com
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun york.sun@nxp.com
Change in v2: None
Rajesh,
Did you send your patch set twice? I received two copies. The first one has Message-Id: 20181007095929.17876-2-rajesh.bhagat@nxp.com, sent on 7 Oct 2018 15:28:57 +0530. The second one has Message-Id: 20181007102131.19159-2-rajesh.bhagat@nxp.com, sent on 7 Oct 2018 15:50:59 +0530. You also sent two copies of your v1 patch. Please do not send more than one. If some error happened and you have to send them again, make sure you put "resend" in the subject to be easily identified.
Hi York,
I faced some issue in sending patch, will prefix the subject with RESEND in case same issue occurs next time.
Regards, Rajesh Bhagat
York
Define env_ptr as static in flash and nand env driver to allow these to compile together.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
env/flash.c | 4 ++-- env/nand.c | 6 +++--- include/environment.h | 1 - 3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/env/flash.c b/env/flash.c index 32236c716e..33b199f05b 100644 --- a/env/flash.c +++ b/env/flash.c @@ -45,13 +45,13 @@ DECLARE_GLOBAL_DATA_PTR; #endif
#ifdef ENV_IS_EMBEDDED -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment;
static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; +static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; #endif /* ENV_IS_EMBEDDED */
diff --git a/env/nand.c b/env/nand.c index 3698e68957..4d04bbb164 100644 --- a/env/nand.c +++ b/env/nand.c @@ -40,11 +40,11 @@ #endif
#if defined(ENV_IS_EMBEDDED) -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) -env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; +static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; #else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr; +static env_t *env_ptr; #endif /* ENV_IS_EMBEDDED */
DECLARE_GLOBAL_DATA_PTR; diff --git a/include/environment.h b/include/environment.h index 5e90f157e8..7da1291d5b 100644 --- a/include/environment.h +++ b/include/environment.h @@ -157,7 +157,6 @@ extern env_t environment; #endif /* ENV_IS_EMBEDDED */
extern const unsigned char default_environment[]; -extern env_t *env_ptr;
#if defined(CONFIG_NEEDS_MANUAL_RELOC) extern void env_reloc(void);
Defines env_sf_get_env_addr API to override sf environment address, required to support multiple environment.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
env/sf.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c index 494510533a..df22fd520b 100644 --- a/env/sf.c +++ b/env/sf.c @@ -297,10 +297,17 @@ out: } #endif
+#ifdef CONFIG_ENV_ADDR +__weak void *env_sf_get_env_addr(void) +{ + return (void *)CONFIG_ENV_ADDR; +} +#endif + #if defined(INITENV) && defined(CONFIG_ENV_ADDR) static int env_sf_init(void) { - env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR); + env_t *env_ptr = (env_t *)env_sf_get_env_addr();
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&(env_ptr->data);
env_ptr is not used when ENV_IS_EMBEDDED and CONFIG_NAND_ENV_DST is not defined. Hence, remove it.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
env/nand.c | 2 -- 1 file changed, 2 deletions(-)
diff --git a/env/nand.c b/env/nand.c index 4d04bbb164..29eda66fad 100644 --- a/env/nand.c +++ b/env/nand.c @@ -43,8 +43,6 @@ static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; -#else /* ! ENV_IS_EMBEDDED */ -static env_t *env_ptr; #endif /* ENV_IS_EMBEDDED */
DECLARE_GLOBAL_DATA_PTR;
Replaces __ilog2 function call with LOG2 macro, required to use macros in global variables.
Also, corrects the value passed in LOG2 for some PowerPC platforms. Minimum value that can be configured is is 64K for IFC IP.
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
include/configs/B4860QDS.h | 2 +- include/configs/T102xQDS.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T4240QDS.h | 2 +- include/configs/T4240RDB.h | 2 +- include/fsl_ifc.h | 10 +++++----- 7 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c37864c139..be7ee8e433 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -286,7 +286,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 8a38c5e19c..e4a14792a2 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -299,7 +299,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index e890860b7e..0498d7891b 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -225,7 +225,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 7d9354b360..8d358c9285 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -275,7 +275,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index f85881fc3c..0b469b1477 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -201,7 +201,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9d8834a3be..27bd145b52 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -470,7 +470,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_MSEL_GPCM \ | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0de8..17697c7341 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0xFFFF0000 #define IFC_AMASK_SHIFT 16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT))
/* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK 0x0000001C #define CSOR_NAND_TRHZ_SHIFT 2 @@ -164,7 +164,7 @@ /* GPCM Timeout Count */ #define CSOR_GPCM_GPTO_MASK 0x0F000000 #define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) /* GPCM External Access Termination mode for read access */ #define CSOR_GPCM_RGETA_EXT 0x00080000 /* GPCM External Access Termination mode for write access */ @@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes { */ #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) +#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
/* * NAND_AUTOBOOT_TRGR @@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes { /* Sequence Timeout Count */ #define IFC_NORCR_STOCNT_MASK 0x000F0000 #define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) +#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
/* * GPCM Machine specific registers
From: York Sun york.sun@nxp.com
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken.
Signed-off-by: York Sun york.sun@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index ef3987ea84..11b5fb2ec3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */
+ /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1:
From: Pankit Garg pankit.garg@nxp.com
Change tlb base address from OCRAM to DDR when exception level is less than 3.
Signed-off-by: Ruchika Gupta ruchika.gupta@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bae50f68d8..6304825180 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -371,7 +371,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el();
/* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
From: Pankit Garg pankit.garg@nxp.com
IFC driver changes to implement the chipselect mappings at run time.
Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot.
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
drivers/misc/fsl_ifc.c | 488 +++++++++++++++++++++++++++++------------ include/fsl_ifc.h | 17 ++ 2 files changed, 369 insertions(+), 136 deletions(-)
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 7d66c3cf76..2e3b43356e 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -7,185 +7,401 @@ #include <common.h> #include <fsl_ifc.h>
-void print_ifc_regs(void) -{ - int i, j; - - printf("IFC Controller Registers\n"); - for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { - printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", - i, get_ifc_cspr(i), i, get_ifc_amask(i), - i, get_ifc_csor(i)); - for (j = 0; j < 4; j++) - printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); - } -} - -void init_early_memctl_regs(void) -{ +struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "cs0", #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); - -#ifndef CONFIG_A003399_NOR_WORKAROUND + CONFIG_SYS_CSPR0, #ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); -#endif + CONFIG_SYS_CSPR0_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK0 + CONFIG_SYS_AMASK0, +#else + 0, +#endif + CONFIG_SYS_CSOR0, + { + CONFIG_SYS_CS0_FTIM0, + CONFIG_SYS_CS0_FTIM1, + CONFIG_SYS_CS0_FTIM2, + CONFIG_SYS_CS0_FTIM3, + }, #ifdef CONFIG_SYS_CSOR0_EXT - set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); + CONFIG_SYS_CSOR0_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR0_FINAL + CONFIG_SYS_CSPR0_FINAL, +#else + 0, #endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); +#ifdef CONFIG_SYS_AMASK0_FINAL + CONFIG_SYS_AMASK0_FINAL, +#else + 0, #endif #endif + },
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2 + { + "cs1", +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + CONFIG_SYS_CSPR1, #ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); -#endif + CONFIG_SYS_CSPR1_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK1 + CONFIG_SYS_AMASK1, +#else + 0, +#endif + CONFIG_SYS_CSOR1, + { + CONFIG_SYS_CS1_FTIM0, + CONFIG_SYS_CS1_FTIM1, + CONFIG_SYS_CS1_FTIM2, + CONFIG_SYS_CS1_FTIM3, + }, #ifdef CONFIG_SYS_CSOR1_EXT - set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); + CONFIG_SYS_CSOR1_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); - - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); +#ifdef CONFIG_SYS_CSPR1_FINAL + CONFIG_SYS_CSPR1_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK1_FINAL + CONFIG_SYS_AMASK1_FINAL, +#else + 0, +#endif +#endif + }, #endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3 + { + "cs2", +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + CONFIG_SYS_CSPR2, #ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); -#endif + CONFIG_SYS_CSPR2_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK2 + CONFIG_SYS_AMASK2, +#else + 0, +#endif + CONFIG_SYS_CSOR2, + { + CONFIG_SYS_CS2_FTIM0, + CONFIG_SYS_CS2_FTIM1, + CONFIG_SYS_CS2_FTIM2, + CONFIG_SYS_CS2_FTIM3, + }, #ifdef CONFIG_SYS_CSOR2_EXT - set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); + CONFIG_SYS_CSOR2_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR2_FINAL + CONFIG_SYS_CSPR2_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK2_FINAL + CONFIG_SYS_AMASK2_FINAL, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); - - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); +#endif + }, #endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4 + { + "cs3", +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + CONFIG_SYS_CSPR3, #ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); -#endif + CONFIG_SYS_CSPR3_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK3 + CONFIG_SYS_AMASK3, +#else + 0, +#endif + CONFIG_SYS_CSOR3, + { + CONFIG_SYS_CS3_FTIM0, + CONFIG_SYS_CS3_FTIM1, + CONFIG_SYS_CS3_FTIM2, + CONFIG_SYS_CS3_FTIM3, + }, #ifdef CONFIG_SYS_CSOR3_EXT - set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); + CONFIG_SYS_CSOR3_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); - - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); +#ifdef CONFIG_SYS_CSPR3_FINAL + CONFIG_SYS_CSPR3_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK3_FINAL + CONFIG_SYS_AMASK3_FINAL, +#else + 0, +#endif +#endif + }, #endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5 + { + "cs4", +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) + CONFIG_SYS_CSPR4, #ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); -#endif + CONFIG_SYS_CSPR4_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK4 + CONFIG_SYS_AMASK4, +#else + 0, +#endif + CONFIG_SYS_CSOR4, + { + CONFIG_SYS_CS4_FTIM0, + CONFIG_SYS_CS4_FTIM1, + CONFIG_SYS_CS4_FTIM2, + CONFIG_SYS_CS4_FTIM3, + }, #ifdef CONFIG_SYS_CSOR4_EXT - set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); + CONFIG_SYS_CSOR4_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); - - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); +#ifdef CONFIG_SYS_CSPR4_FINAL + CONFIG_SYS_CSPR4_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK4_FINAL + CONFIG_SYS_AMASK4_FINAL, +#else + 0, +#endif +#endif + }, #endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6 + { + "cs5", +#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) + CONFIG_SYS_CSPR5, #ifdef CONFIG_SYS_CSPR5_EXT - set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); -#endif + CONFIG_SYS_CSPR5_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK5 + CONFIG_SYS_AMASK5, +#else + 0, +#endif + CONFIG_SYS_CSOR5, + { + CONFIG_SYS_CS5_FTIM0, + CONFIG_SYS_CS5_FTIM1, + CONFIG_SYS_CS5_FTIM2, + CONFIG_SYS_CS5_FTIM3, + }, #ifdef CONFIG_SYS_CSOR5_EXT - set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); + CONFIG_SYS_CSOR5_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) - set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); - set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); - set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); - set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); - - set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); - set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); - set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); +#ifdef CONFIG_SYS_CSPR5_FINAL + CONFIG_SYS_CSPR5_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK5_FINAL + CONFIG_SYS_AMASK5_FINAL, +#else + 0, +#endif +#endif + }, #endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7 + { + "cs6", +#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) + CONFIG_SYS_CSPR6, #ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); -#endif + CONFIG_SYS_CSPR6_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK6 + CONFIG_SYS_AMASK6, +#else + 0, +#endif + CONFIG_SYS_CSOR6, + { + CONFIG_SYS_CS6_FTIM0, + CONFIG_SYS_CS6_FTIM1, + CONFIG_SYS_CS6_FTIM2, + CONFIG_SYS_CS6_FTIM3, + }, #ifdef CONFIG_SYS_CSOR6_EXT - set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); + CONFIG_SYS_CSOR6_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); - - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); +#ifdef CONFIG_SYS_CSPR6_FINAL + CONFIG_SYS_CSPR6_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK6_FINAL + CONFIG_SYS_AMASK6_FINAL, +#else + 0, +#endif +#endif + }, #endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8 + { + "cs7", +#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) + CONFIG_SYS_CSPR7, #ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); + CONFIG_SYS_CSPR7_EXT, +#else + 0, #endif -#ifdef CONFIG_SYS_CSOR7_EXT - set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#ifdef CONFIG_SYS_AMASK7 + CONFIG_SYS_AMASK7, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); + CONFIG_SYS_CSOR7, +#ifdef CONFIG_SYS_CSOR7_EXT + CONFIG_SYS_CSOR7_EXT, +#else + 0, +#endif + { + CONFIG_SYS_CS7_FTIM0, + CONFIG_SYS_CS7_FTIM1, + CONFIG_SYS_CS7_FTIM2, + CONFIG_SYS_CS7_FTIM3, + }, +#ifdef CONFIG_SYS_CSPR7_FINAL + CONFIG_SYS_CSPR7_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK7_FINAL + CONFIG_SYS_AMASK7_FINAL, +#else + 0, +#endif +#endif + }, +#endif +};
- set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); -#endif +__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + regs_info->regs = ifc_cfg_default_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ + int i, j; + struct ifc_regs *regs; + struct ifc_regs_info regs_info = {0}; + + ifc_cfg_boot_info(®s_info); + regs = regs_info.regs; + + for (i = 0 ; i < regs_info.cs_size; i++) { + if (regs[i].pr && (regs[i].pr & CSPR_V)) { + /* skip setting cspr/csor_ext in below condition */ + if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) && \ + i == 0 && \ + ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) { + if (regs[i].pr_ext) + set_ifc_cspr_ext(i, regs[i].pr_ext); + if (regs[i].or_ext) + set_ifc_csor_ext(i, regs[i].or_ext); + } + + for (j = 0; j < ARRAY_SIZE(regs->ftim); j++) + set_ifc_ftim(i, j, regs[i].ftim[j]); + + set_ifc_csor(i, regs[i].or); + set_ifc_amask(i, regs[i].amask); + set_ifc_cspr(i, regs[i].pr); + } + } }
void init_final_memctl_regs(void) { -#ifdef CONFIG_SYS_CSPR0_FINAL - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK0_FINAL - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); -#endif -#ifdef CONFIG_SYS_CSPR1_FINAL - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK1_FINAL - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); -#endif -#ifdef CONFIG_SYS_CSPR2_FINAL - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK2_FINAL - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); -#endif -#ifdef CONFIG_SYS_CSPR3_FINAL - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK3_FINAL - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); -#endif + int i; + struct ifc_regs *regs; + struct ifc_regs_info regs_info; + + ifc_cfg_boot_info(®s_info); + regs = regs_info.regs; + + for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) { + if (!(regs[i].pr_final & CSPR_V)) + continue; + if (regs[i].pr_final) + set_ifc_cspr(i, regs[i].pr_final); + if (regs[i].amask_final) + set_ifc_amask(i, (i == 1) ? regs[i].amask_final : + regs[i].amask); + } } diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 17697c7341..c42affcf1f 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -1031,6 +1031,23 @@ struct fsl_ifc { struct fsl_ifc_runtime *rregs; };
+struct ifc_regs { + const char *name; + uint32_t pr; + uint32_t pr_ext; + uint32_t amask; + uint32_t or; + uint32_t ftim[4]; + uint32_t or_ext; + uint32_t pr_final; + uint32_t amask_final; +}; + +struct ifc_regs_info { + struct ifc_regs *regs; + uint32_t cs_size; +}; + #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #undef CSPR_MSEL_NOR #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
PORSR register holds the cfg_rcw_src field which can be used to identify boot source.
Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 190 ++++++++++++++++++ .../asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++ .../asm/arch-fsl-layerscape/immap_lsch3.h | 49 +++++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 17 ++ 4 files changed, 276 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 6304825180..f72e23e0de 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -31,6 +31,10 @@ #include <hwconfig.h> #include <fsl_qbman.h>
+#ifdef CONFIG_TFABOOT +#include <environment.h> +#endif + DECLARE_GLOBAL_DATA_PTR;
static struct cpu_type cpu_type_list[] = { @@ -579,7 +583,193 @@ void enable_caches(void) icache_enable(); dcache_enable(); } +#endif /* CONFIG_SYS_DCACHE_OFF */ + +#ifdef CONFIG_TFABOOT +enum boot_src __get_boot_src(u32 porsr1) +{ + enum boot_src src = BOOT_SOURCE_RESERVED; + uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; +#if !defined(CONFIG_FSL_LSCH3_2) + uint32_t val; +#endif + debug("%s: rcw_src 0x%x\n", __func__, rcw_src); + +#if defined(CONFIG_FSL_LSCH3) +#if defined(CONFIG_FSL_LSCH3_2) + switch (rcw_src) { + case RCW_SRC_SDHC1_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_SDHC2_VAL: + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + case RCW_SRC_FLEXSPI_NAND2K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_FLEXSPI_NAND4K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_RESERVED_1_VAL: + src = BOOT_SOURCE_RESERVED; + break; + case RCW_SRC_FLEXSPI_NOR_24B: + src = BOOT_SOURCE_XSPI_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } +#else + val = rcw_src & RCW_SRC_TYPE_MASK; + if (val == RCW_SRC_NOR_VAL) { + val = rcw_src & NOR_TYPE_MASK; + + switch (val) { + case NOR_16B_VAL: + case NOR_32B_VAL: + src = BOOT_SOURCE_IFC_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } else { + /* RCW SRC Serial Flash */ + val = rcw_src & RCW_SRC_SERIAL_MASK; + switch (val) { + case RCW_SRC_QSPI_VAL: + /* RCW SRC Serial NOR (QSPI) */ + src = BOOT_SOURCE_QSPI_NOR; + break; + case RCW_SRC_SD_CARD_VAL: + /* RCW SRC SD Card */ + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_EMMC_VAL: + /* RCW SRC EMMC */ + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + /* RCW SRC I2C1 Extended */ + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } +#endif +#elif defined(CONFIG_FSL_LSCH2) + /* RCW SRC NAND */ + val = rcw_src & RCW_SRC_NAND_MASK; + if (val == RCW_SRC_NAND_VAL) { + val = rcw_src & NAND_RESERVED_MASK; + if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) { + src = BOOT_SOURCE_IFC_NAND; + } + } else { + /* RCW SRC NOR */ + val = rcw_src & RCW_SRC_NOR_MASK; + if (val == NOR_8B_VAL || val == NOR_16B_VAL) { + src = BOOT_SOURCE_IFC_NOR; + } else { + switch (rcw_src) { + case QSPI_VAL1: + case QSPI_VAL2: + src = BOOT_SOURCE_QSPI_NOR; + break; + case SD_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } + } #endif + debug("%s: src 0x%x\n", __func__, src); + return src; +} + +enum boot_src get_boot_src(void) +{ + u32 porsr1; + +#if defined(CONFIG_FSL_LSCH3) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + porsr1 = in_be32(&gur->porsr1); +#endif + debug("%s: porsr1 0x%x\n", __func__, porsr1); + + return __get_boot_src(porsr1); +} + +#ifdef CONFIG_ENV_IS_IN_MMC +int mmc_get_env_dev(void) +{ + enum boot_src src = get_boot_src(); + int dev = CONFIG_SYS_MMC_ENV_DEV; + + switch (src) { + case BOOT_SOURCE_SD_MMC: + dev = 0; + break; + case BOOT_SOURCE_SD_MMC2: + dev = 1; + break; + default: + break; + } + + return dev; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_src src = get_boot_src(); + enum env_location env_loc = ENVL_NOWHERE; + + if (prio) + return ENVL_UNKNOWN; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + env_loc = ENVL_FLASH; + break; + case BOOT_SOURCE_QSPI_NOR: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NOR: + env_loc = ENVL_SPI_FLASH; + break; + case BOOT_SOURCE_IFC_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_QSPI_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NAND: + env_loc = ENVL_NAND; + break; + case BOOT_SOURCE_SD_MMC: + /* FALLTHROUGH */ + case BOOT_SOURCE_SD_MMC2: + env_loc = ENVL_MMC; + break; + case BOOT_SOURCE_I2C1_EXTENDED: + /* FALLTHROUGH */ + default: + break; + } + + + return env_loc; +} +#endif /* CONFIG_TFABOOT */
u32 initiator_type(u32 cluster, int init_id) { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index be0a6ae363..16528911d7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -675,6 +675,26 @@ struct ccsr_gpio { #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400
+#ifdef CONFIG_TFABOOT +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 + +/* RCW SRC NAND */ +#define RCW_SRC_NAND_MASK (0x100) +#define RCW_SRC_NAND_VAL (0x100) +#define NAND_RESERVED_MASK (0xFC) +#define NAND_RESERVED_1 (0x0) +#define NAND_RESERVED_2 (0x80) + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_MASK (0x1F0) +#define NOR_8B_VAL (0x10) +#define NOR_16B_VAL (0x20) +#define SD_VAL (0x40) +#define QSPI_VAL1 (0x44) +#define QSPI_VAL2 (0x45) +#endif + uint get_svr(void);
#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b0cec74db0..816d960b2f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -82,6 +82,55 @@ #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#ifdef CONFIG_TFABOOT +#ifdef CONFIG_FSL_LSCH3_2 +/* RCW_SRC field in Power-On Reset Control Register 1 */ +#define RCW_SRC_MASK 0x07800000 +#define RCW_SRC_BIT 23 + +/* CFG_RCW_SRC[3:0] */ +#define RCW_SRC_TYPE_MASK 0x8 +#define RCW_SRC_ADDR_OFFSET_8MB 0x800000 + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ + +#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ +#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ +#define RCW_SRC_I2C1_VAL 0xa /* 0xa */ +#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ +#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ +#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ +#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ +#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ +#else +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 +/* CFG_RCW_SRC[6:0] */ +#define RCW_SRC_TYPE_MASK (0x70) + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ +/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_VAL (0x20) +#define NOR_TYPE_MASK (0x10) +#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ +#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ + +/* RCW SRC Serial Flash + * 1. SERIAL NOR (QSPI) + * 2. OTHERS (SD/MMC, SPI, I2C1 + */ +#define RCW_SRC_SERIAL_MASK (0x7F) +#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ +#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ +#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ +#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ +#endif +#endif + /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 61b6e4bf07..d327c7ba1f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -53,6 +53,23 @@ struct cpu_type {
#define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#ifdef CONFIG_TFABOOT +enum boot_src { + BOOT_SOURCE_RESERVED = 0, + BOOT_SOURCE_IFC_NOR, + BOOT_SOURCE_IFC_NAND, + BOOT_SOURCE_QSPI_NOR, + BOOT_SOURCE_QSPI_NAND, + BOOT_SOURCE_XSPI_NOR, + BOOT_SOURCE_XSPI_NAND, + BOOT_SOURCE_SD_MMC, + BOOT_SOURCE_SD_MMC2, + BOOT_SOURCE_I2C1_EXTENDED, +}; + +enum boot_src get_boot_src(void); +#endif #endif #define SVR_WO_E 0xFFFFFE #define SVR_LS1012A 0x870400
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.
ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803 SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fadc0..1b84da5f66 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -62,17 +62,17 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2
On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.
ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803 SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fadc0..1b84da5f66 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
- select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES
@@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
- select ARM_ERRATA_855873 if !TFABOOT
This seems to be an error of reordering the patches. TFABOOT has not beed added at this point.
York
-----Original Message----- From: York Sun Sent: Monday, October 8, 2018 8:19 PM To: Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH v2 10/33] armv8: layerscape: remove EL3 specific erratas for TFABOOT
On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.
ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850,
SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803 SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fadc0..1b84da5f66 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
- select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES
@@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
- select ARM_ERRATA_855873 if !TFABOOT
This seems to be an error of reordering the patches. TFABOOT has not beed added at this point.
Will take care in next version.
York
From: Pankit Garg pankit.garg@nxp.com
Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 78 +++++++++++++++++++++++++ 1 file changed, 78 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3f15cb08ff..d6c336548f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -24,6 +24,10 @@ #include <fsl_validate.h> #endif #include <fsl_immap.h> +#ifdef CONFIG_TFABOOT +#include <environment.h> +DECLARE_GLOBAL_DATA_PTR; +#endif
bool soc_has_dp_ddr(void) { @@ -679,12 +683,86 @@ int qspi_ahb_init(void) } #endif
+#ifdef CONFIG_TFABOOT +#define MAX_BOOTCMD_SIZE 256 + +int fsl_setenv_bootcmd(void) +{ + int ret; + enum boot_src src = get_boot_src(); + char bootcmd_str[MAX_BOOTCMD_SIZE]; + + switch (src) { +#ifdef IFC_NOR_BOOTCOMMAND + case BOOT_SOURCE_IFC_NOR: + sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NOR: + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NOR: + sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef IFC_NAND_BOOTCOMMAND + case BOOT_SOURCE_IFC_NAND: + sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NAND: + sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NAND: + sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef SD_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC: + sprintf(bootcmd_str, SD_BOOTCOMMAND); + break; +#endif +#ifdef SD2_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC2: + sprintf(bootcmd_str, SD2_BOOTCOMMAND); + break; +#endif + default: +#ifdef QSPI_NOR_BOOTCOMMAND + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); +#endif + break; + } + + ret = env_set("bootcmd", bootcmd_str); + if (ret) { + printf("Failed to set bootcmd: ret = %d\n", ret); + return ret; + } + return 0; +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif +#ifdef CONFIG_TFABOOT + /* + * check if gd->env_addr is default_environment; then setenv bootcmd + */ + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { + fsl_setenv_bootcmd(); + } +#endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); #endif
Add secure boot support for environment selection.
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index f72e23e0de..2b511ebe6d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -33,6 +33,9 @@
#ifdef CONFIG_TFABOOT #include <environment.h> +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif #endif
DECLARE_GLOBAL_DATA_PTR; @@ -739,6 +742,14 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN;
+#ifdef CONFIG_CHAIN_OF_TRUST + /* Check Boot Mode + * If Boot Mode is Secure, return ENVL_NOWHERE + */ + if (fsl_check_boot_mode_secure() == 1) + goto done; +#endif + switch (src) { case BOOT_SOURCE_IFC_NOR: env_loc = ENVL_FLASH; @@ -766,6 +777,9 @@ enum env_location env_get_location(enum env_operation op, int prio) break; }
+#ifdef CONFIG_CHAIN_OF_TRUST +done: +#endif
return env_loc; }
Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++++++++++++++++++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 4 + 2 files changed, 88 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2b511ebe6d..153ae43b29 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1228,12 +1228,96 @@ phys_size_t get_effective_memsize(void) return ea_size; }
+#ifdef CONFIG_TFABOOT +phys_size_t tfa_get_dram_size(void) +{ + struct pt_regs regs; + phys_size_t dram_size = 0; + + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = -1; + + smc_call(®s); + if (regs.regs[0]) + return 0; + + dram_size = regs.regs[1]; + return dram_size; +} + +static int tfa_dram_init_banksize(void) +{ + int i = 0, ret = 0; + struct pt_regs regs; + phys_size_t dram_size = tfa_get_dram_size(); + + debug("dram_size %llx\n", dram_size); + + if (!dram_size) + return -EINVAL; + + do { + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = i; + + smc_call(®s); + if (regs.regs[0]) { + ret = -EINVAL; + break; + } + + debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], + regs.regs[2]); + gd->bd->bi_dram[i].start = regs.regs[1]; + gd->bd->bi_dram[i].size = regs.regs[2]; + + dram_size -= gd->bd->bi_dram[i].size; + + i++; + } while (dram_size); + + if (i > 0) + ret = 0; + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + + return ret; +} +#endif + int dram_init_banksize(void) { #ifdef CONFIG_SYS_DP_DDR_BASE_PHY phys_size_t dp_ddr_size; #endif
+#ifdef CONFIG_TFABOOT + if (!tfa_dram_init_banksize()) + return 0; +#endif /* * gd->ram_size has the total size of DDR memory, less reserved secure * memory. The DDR extends from low region to high region(s) presuming diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index d327c7ba1f..ef228b6443 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -55,6 +55,10 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#ifdef CONFIG_TFABOOT +#define SMC_DRAM_BANK_INFO (0xC200FF12) + +phys_size_t tfa_get_dram_size(void); + enum boot_src { BOOT_SOURCE_RESERVED = 0, BOOT_SOURCE_IFC_NOR,
OCRAM initialization is performed by TFA, Hence skipped from u-boot.
Signed-off-by: Ruchika Gupta ruchika.gupta@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 11b5fb2ec3..cbc9112eb1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -304,7 +304,8 @@ ENTRY(lowlevel_init) 100: #endif
-#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_TFABOOT) && \ + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) bl fsl_ocram_init #endif
From: York Sun york.sun@nxp.com
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared.
Signed-off-by: York Sun york.sun@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 26 ++++++++++++++++--- .../arm/include/asm/arch-fsl-layerscape/soc.h | 1 + 2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 153ae43b29..335f609eaa 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -691,23 +691,41 @@ enum boot_src __get_boot_src(u32 porsr1) } } #endif + + if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src) + src = BOOT_SOURCE_QSPI_NOR; + debug("%s: src 0x%x\n", __func__, src); return src; }
enum boot_src get_boot_src(void) { - u32 porsr1; + struct pt_regs regs; + u32 porsr1 = 0;
#if defined(CONFIG_FSL_LSCH3) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - - porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); #elif defined(CONFIG_FSL_LSCH2) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#endif + + if (current_el() == 2) { + regs.regs[0] = SIP_SVC_RCW;
- porsr1 = in_be32(&gur->porsr1); + smc_call(®s); + if (!regs.regs[0]) + porsr1 = regs.regs[1]; + } + + if (current_el() == 3 || !porsr1) { +#ifdef CONFIG_FSL_LSCH3 + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + porsr1 = in_be32(&gur->porsr1); #endif + } + debug("%s: porsr1 0x%x\n", __func__, porsr1);
return __get_boot_src(porsr1); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index ef228b6443..daa1c70b3a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -56,6 +56,7 @@ struct cpu_type {
#ifdef CONFIG_TFABOOT #define SMC_DRAM_BANK_INFO (0xC200FF12) +#define SIP_SVC_RCW 0xC200FF18
phys_size_t tfa_get_dram_size(void);
From: Pankit Garg pankit.garg@nxp.com
Add support of MC framework for TFA Make MC framework independent of boot source.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 50 +++++++++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d6c336548f..8a9e39f7d9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -747,6 +747,54 @@ int fsl_setenv_bootcmd(void) } return 0; } + +int fsl_setenv_mcinitcmd(void) +{ + int ret = 0; + enum boot_src src = get_boot_src(); + + switch (src) { +#ifdef IFC_MC_INIT_CMD + case BOOT_SOURCE_IFC_NAND: + case BOOT_SOURCE_IFC_NOR: + ret = env_set("mcinitcmd", IFC_MC_INIT_CMD); + break; +#endif +#ifdef QSPI_MC_INIT_CMD + case BOOT_SOURCE_QSPI_NAND: + case BOOT_SOURCE_QSPI_NOR: + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); + break; +#endif +#ifdef XSPI_MC_INIT_CMD + case BOOT_SOURCE_XSPI_NAND: + case BOOT_SOURCE_XSPI_NOR: + ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD); + break; +#endif +#ifdef SD_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC: + ret = env_set("mcinitcmd", SD_MC_INIT_CMD); + break; +#endif +#ifdef SD2_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC2: + ret = env_set("mcinitcmd", SD2_MC_INIT_CMD); + break; +#endif + default: +#ifdef QSPI_MC_INIT_CMD + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); +#endif + break; + } + + if (ret) { + printf("Failed to set mcinitcmd: ret = %d\n", ret); + return ret; + } + return 0; +} #endif
#ifdef CONFIG_BOARD_LATE_INIT @@ -758,9 +806,11 @@ int board_late_init(void) #ifdef CONFIG_TFABOOT /* * check if gd->env_addr is default_environment; then setenv bootcmd + * and mcinitcmd. */ if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { fsl_setenv_bootcmd(); + fsl_setenv_mcinitcmd(); } #endif #ifdef CONFIG_QSPI_AHB_INIT
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 1c0f963e18..af1b2da072 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -68,7 +68,7 @@ ENTRY(armv8_el2_to_aarch32) mov x3, x2 mov x2, x1 mov x1, x4 - ldr x0, =0xc000ff04 + ldr x0, =0xc200ff17 smc #0 ret ENDPROC(armv8_el2_to_aarch32)
From: Pankit Garg pankit.garg@nxp.com
Returns job ring status as true in TFABOOT, as one job ring is always reserved.
Signed-off-by: Ruchika Gupta ruchika.gupta@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com --- Change in v2: None
arch/arm/cpu/armv8/sec_firmware.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index a13c92e246..8dc0ac9266 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void) */ bool sec_firmware_support_hwrng(void) { +#ifdef CONFIG_TFABOOT + /* return true as TFA has one job ring reserved */ + return true; +#endif if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { return true; }
Adds TFABOOT support and allows to pick FMAN firmware on basis of boot source.
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
drivers/net/fm/fm.c | 102 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 98 insertions(+), 4 deletions(-)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 3327073bf1..8c6eec3c08 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -11,13 +11,13 @@ #include "fm.h" #include <fsl_qe.h> /* For struct qe_firmware */
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include <nand.h> -#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) #include <spi_flash.h> -#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) #include <mmc.h> -#endif +/* required to include IFC and QSPI base address */ +#include <asm/armv8/mmu.h> +#include <asm/arch/cpu.h> +#include <environment.h>
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
@@ -347,6 +347,99 @@ static void fm_init_qmi(struct fm_qmi_common *qmi) }
/* Init common part of FM, index is fm num# like fm as above */ +#ifdef CONFIG_TFABOOT +int fm_init_common(int index, struct ccsr_fman *reg) +{ + int rc; + void *addr = NULL; + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NOR) { + addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR + + CONFIG_SYS_FSL_IFC_BASE); + } else if (src == BOOT_SOURCE_IFC_NAND) { + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + + rc = nand_read(get_nand_dev_by_index(0), + (loff_t)CONFIG_SYS_FMAN_FW_ADDR, + &fw_length, (u_char *)addr); + if (rc == -EUCLEAN) { + printf("NAND read of FMAN firmware at offset 0x%x\ + failed %d\n", CONFIG_SYS_FMAN_FW_ADDR, rc); + } + } else if (src == BOOT_SOURCE_QSPI_NOR) { + struct spi_flash *ucode_flash; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + int ret = 0; + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + /* speed and mode will be read from DT */ + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, 0, 0, &new); + + ucode_flash = dev_get_uclass_priv(new); +#else + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE); +#endif + if (!ucode_flash) + printf("SF: probe for ucode failed\n"); + else { + ret = spi_flash_read(ucode_flash, + CONFIG_SYS_FMAN_FW_ADDR + + CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_QE_FMAN_FW_LENGTH, + addr); + if (ret) + printf("SF: read for ucode failed\n"); + spi_flash_free(ucode_flash); + } + } else if (src == BOOT_SOURCE_SD_MMC) { + int dev = CONFIG_SYS_MMC_ENV_DEV; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) + printf("\nMMC cannot find device for ucode\n"); + else { + printf("\nMMC read: dev # %u, block # %u, count %u \ + ...\n", dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, + cnt, addr); + } + } else + addr = NULL; + + /* Upload the Fman microcode if it's present */ + rc = fman_upload_firmware(index, ®->fm_imem, addr); + if (rc) + return rc; + env_set_addr("fman_ucode", addr); + + fm_init_muram(index, ®->muram); + fm_init_qmi(®->fm_qmi_common); + fm_init_fpm(®->fm_fpm); + + /* clear DMA status */ + setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL); + + /* set DMA mode */ + setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER); + + return fm_init_bmi(index, ®->fm_bmi_common); +} +#else int fm_init_common(int index, struct ccsr_fman *reg) { int rc; @@ -429,3 +522,4 @@ int fm_init_common(int index, struct ccsr_fman *reg)
return fm_init_bmi(index, ®->fm_bmi_common); } +#endif
Adds TFABOOT support and allows to pick QE firmware on basis of boot source.
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: None
drivers/qe/qe.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7654df8008..d7e3a1b923 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -17,9 +17,17 @@ #include <asm/arch/immap_ls102xa.h> #endif
+#ifdef CONFIG_TFABOOT +#include <mmc.h> +/* required to include IFC and QSPI base address */ +#include <asm/armv8/mmu.h> +#include <asm/arch/cpu.h> +#include <environment.h> +#else #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC #include <mmc.h> #endif +#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
@@ -170,6 +178,33 @@ void qe_put_snum(u8 snum) } }
+#ifdef CONFIG_TFABOOT +void qe_init(uint qe_base) +{ + enum boot_src src = get_boot_src(); + + /* Init the QE IMMR base */ + qe_immr = (qe_map_t *)qe_base; + + if (src == BOOT_SOURCE_IFC_NOR) { + /* + * Upload microcode to IRAM for those SOCs + * which do not have ROM in QE. + */ + qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR + + CONFIG_SYS_FSL_IFC_BASE)); + + /* enable the microcode in IRAM */ + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); + } + + gd->arch.mp_alloc_base = QE_DATAONLY_BASE; + gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE; + + qe_sdma_init(); + qe_snums_init(); +} +#else void qe_init(uint qe_base) { /* Init the QE IMMR base */ @@ -192,8 +227,53 @@ void qe_init(uint qe_base) qe_snums_init(); } #endif +#endif
#ifdef CONFIG_U_QE +#ifdef CONFIG_TFABOOT +void u_qe_init(void) +{ + enum boot_src src = get_boot_src(); + + qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); + + void *addr = (void *)CONFIG_SYS_QE_FW_ADDR; + + if (src == BOOT_SOURCE_IFC_NOR) { + addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE); + } + if (src == BOOT_SOURCE_QSPI_NOR) { + addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE); + } + if (src == BOOT_SOURCE_SD_MMC) { + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_QE_FW_ADDR / 512; + + if (mmc_initialize(gd->bd)) { + printf("%s: mmc_initialize() failed\n", __func__); + return; + } + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + free(addr); + printf("\nMMC cannot find device for ucode\n"); + } else { + printf("\nMMC read: dev # %u, block # %u,\ + count %u ...\n", dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, + cnt, addr); + } + } + if (!u_qe_upload_firmware(addr)) + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); + if (src == BOOT_SOURCE_SD_MMC) + free(addr); +} +#else void u_qe_init(void) { qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); @@ -229,6 +309,7 @@ void u_qe_init(void) #endif } #endif +#endif
#ifdef CONFIG_U_QE void u_qe_resume(void)
TFABOOT support includes: - ls1046ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT
Signed-off-by: York Sun york.sun@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: - Merged ls1046ardb TFA boot support patches - Removed extra CONFIG_TFABOOT flag usage
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++-- board/freescale/ls1046ardb/ddr.c | 12 ++++++ configs/ls1046ardb_tfa_defconfig | 49 +++++++++++++++++++++++ include/configs/ls1046a_common.h | 12 ++++++ include/configs/ls1046ardb.h | 15 +++++++ 6 files changed, 101 insertions(+), 3 deletions(-) create mode 100644 configs/ls1046ardb_tfa_defconfig
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1b84da5f66..1872c66dcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB help For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use pins, select it when the pins are assigned to USB. + +config TFABOOT + bool "Support for booting from TFA" + default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via TFA. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f609eaa..2e3494bee4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -95,7 +95,8 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -146,7 +147,8 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -1542,7 +1544,8 @@ void update_early_mmu_table(void) __weak int dram_init(void) { fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index 82b1b1d9ea..321222d68d 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -97,6 +97,17 @@ found: popts->cpo_sample = 0x61; }
+#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -117,3 +128,4 @@ int fsl_initdram(void)
return 0; } +#endif diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig new file mode 100644 index 0000000000..5bc80ed24e --- /dev/null +++ b/configs/ls1046ardb_tfa_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index cdb73f644a..6e36c9339b 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -33,7 +33,11 @@ #include <asm/arch/stream_id_lsch2.h>
/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -165,6 +169,13 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#else #ifdef CONFIG_SD_BOOT /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -187,6 +198,7 @@ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index ffca410b1a..cc1f5f5f55 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -160,6 +160,13 @@ #define CONFIG_ENV_OVERWRITE #endif
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#else #if defined(CONFIG_SD_BOOT) #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) @@ -169,6 +176,7 @@ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #endif +#endif
#define AQR105_IRQ_MASK 0x80000000 /* FMan */ @@ -208,6 +216,12 @@
#ifndef SPL_NO_MISC #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;;" @@ -216,6 +230,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif
#include <asm/fsl_secure_boot.h>
On 10/07/2018 03:22 AM, Rajesh Bhagat wrote:
TFABOOT support includes:
- ls1046ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: York Sun york.sun@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com
Change in v2:
- Merged ls1046ardb TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++-- board/freescale/ls1046ardb/ddr.c | 12 ++++++ configs/ls1046ardb_tfa_defconfig | 49 +++++++++++++++++++++++ include/configs/ls1046a_common.h | 12 ++++++ include/configs/ls1046ardb.h | 15 +++++++ 6 files changed, 101 insertions(+), 3 deletions(-) create mode 100644 configs/ls1046ardb_tfa_defconfig
Separate changes to add TFABOOT and put it into a standalone patch. Leave the rest in this patch, and squash with patch #22.
Do the same squash for every board, i.e. to keep on patch per board. This reduces the total number of compiling tests.
York
-----Original Message----- From: York Sun Sent: Monday, October 8, 2018 8:35 PM To: Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Pankit Garg pankit.garg@nxp.com Subject: Re: [PATCH v2 21/33] armv8: ls1046ardb: Add TFABOOT support
On 10/07/2018 03:22 AM, Rajesh Bhagat wrote:
TFABOOT support includes:
- ls1046ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: York Sun york.sun@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com
Change in v2:
- Merged ls1046ardb TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++-- board/freescale/ls1046ardb/ddr.c | 12 ++++++ configs/ls1046ardb_tfa_defconfig | 49 +++++++++++++++++++++++ include/configs/ls1046a_common.h | 12 ++++++ include/configs/ls1046ardb.h | 15 +++++++ 6 files changed, 101 insertions(+), 3 deletions(-) create mode 100644 configs/ls1046ardb_tfa_defconfig
Hi York,
Thanks for the review.
Separate changes to add TFABOOT and put it into a standalone patch. Leave the rest in this patch, and squash with patch #22.
Will take care in next version.
Do the same squash for every board, i.e. to keep on patch per board. This reduces the total number of compiling tests.
Will take care in next version.
York
From: Vinitha V Pillai vinitha.pillai@nxp.com
This defconfig is for Secure TFABOOT, to be loaded by trusted firmware
Signed-off-by: Vinitha V Pillai vinitha.pillai@nxp.com --- Change in v2: None
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 52 ++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..8102d13d7d --- /dev/null +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_USB=y +CONFIG_FSL_QSPI=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y
TFABOOT support includes: - ls1046aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: - Merged ls1046aqds TFA boot support patches - Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1046aqds/ddr.c | 11 ++ board/freescale/ls1046aqds/ls1046aqds.c | 148 +++++++++++++++++++++++- configs/ls1046aqds_tfa_defconfig | 57 +++++++++ include/configs/ls1046aqds.h | 59 +++++++++- 4 files changed, 272 insertions(+), 3 deletions(-) create mode 100644 configs/ls1046aqds_tfa_defconfig
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 08f7610e69..45b1f373a7 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -92,6 +92,16 @@ found: popts->cpo_sample = 0x70; }
+#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -116,3 +126,4 @@ int fsl_initdram(void)
return 0; } +#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 0da82381af..b71c1746bb 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -13,6 +13,7 @@ #include <asm/arch/ppa.h> #include <asm/arch/fdt.h> #include <asm/arch/mmu.h> +#include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <ahci.h> @@ -32,12 +33,140 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif + enum { MUX_TYPE_GPIO, };
int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -45,6 +174,12 @@ int checkboard(void)
puts("Board: LS1046AQDS, boot from ");
+#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -63,6 +198,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif
+#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch));
@@ -153,7 +291,8 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif @@ -342,3 +481,10 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_TFABOOT +void *env_sf_get_env_addr(void) +{ + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig new file mode 100644 index 0000000000..c91bb76edf --- /dev/null +++ b/configs/ls1046aqds_tfa_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 8edaf190d0..6f292a0af9 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -50,7 +50,8 @@ unsigned long get_board_ddr_clk(void); #endif
/* QSPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -230,7 +231,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT #endif @@ -285,6 +287,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -352,6 +388,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif
/* * I2C bus multiplexer @@ -402,6 +439,14 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -418,10 +463,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif
#define CONFIG_CMDLINE_TAG
#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \ + "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ "e0000 f00000 && bootm $kernel_load" @@ -429,6 +483,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #endif +#endif
#include <asm/fsl_secure_boot.h>
From: Vinitha V Pillai vinitha.pillai@nxp.com
This defconfig is for Secure TFABOOT, to be loaded by trusted firmware
Signed-off-by: Vinitha V Pillai vinitha.pillai@nxp.com --- Change in v2: None
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 58 ++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..1a20d0becf --- /dev/null +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_DM=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_CAAM=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y
TFABOOT support includes: - ls1043ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN and QE address changes for TFABOOT - define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: - Merged ls1043ardb TFA boot support patches - Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1043ardb/ddr.c | 14 +++ board/freescale/ls1043ardb/ls1043ardb.c | 110 ++++++++++++++++++++++++ configs/ls1043ardb_tfa_defconfig | 49 +++++++++++ include/configs/ls1043a_common.h | 27 +++++- include/configs/ls1043ardb.h | 29 +++++++ 5 files changed, 228 insertions(+), 1 deletion(-) create mode 100644 configs/ls1043ardb_tfa_defconfig
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 7bc0f568ff..784e482f32 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -205,6 +205,19 @@ phys_size_t fixed_sdram(void) } #endif
+#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) +#ifdef CONFIG_SYS_DDR_RAW_TIMING + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = 0x80000000; +#endif + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -236,3 +249,4 @@ int fsl_initdram(void)
return 0; } +#endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index e7d8650d27..cbbf9a0ec0 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -26,6 +26,104 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif int board_early_init_f(void) { fsl_lsch2_early_init_f(); @@ -37,6 +135,9 @@ int board_early_init_f(void)
int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; @@ -46,6 +147,12 @@ int checkboard(void)
printf("Board: LS1043ARDB, boot from ");
+#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -63,6 +170,9 @@ int checkboard(void) printf("Invalid setting of SW4\n"); #endif
+#ifdef CONFIG_TFABOOT + } +#endif printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig new file mode 100644 index 0000000000..a15cb524d3 --- /dev/null +++ b/configs/ls1043ardb_tfa_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 656d10dffb..7875bf4bba 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -33,7 +33,11 @@ #include <asm/arch/config.h>
/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -119,7 +123,8 @@
/* IFC */ #ifndef SPL_NO_IFC -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -185,6 +190,16 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_SYS_QE_FW_ADDR 0x940000 + +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 + +#else #ifdef CONFIG_NAND_BOOT /* Store Fman ucode at offeset 0x900000(72 blocks). */ #define CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -211,6 +226,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif @@ -303,6 +319,14 @@
#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -314,6 +338,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index bc639e586f..704ecd734a 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -162,6 +162,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -199,6 +218,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -227,6 +247,14 @@ #define CONFIG_ENV_OVERWRITE #endif
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #if defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -239,6 +267,7 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif
/* FMan */ #ifndef SPL_NO_FMAN
From: Vinitha V Pillai vinitha.pillai@nxp.com
This defconfig is for Secure TFABOOT, to be loaded by trusted firmware
Signed-off-by: Vinitha V Pillai vinitha.pillai@nxp.com --- Change in v2: None
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 51 ++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..71adda87f1 --- /dev/null +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_SECURE_BOOT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_TFABOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_CAAM=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y
armv8: ls1043ardb: Add TFABOOT support
TFABOOT support includes: - ls1043aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg pankit.garg@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- Change in v2: - Merged ls1043aqds TFA boot support patches - Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1043aqds/ddr.c | 11 ++ board/freescale/ls1043aqds/ls1043aqds.c | 147 +++++++++++++++++++++++- configs/ls1043aqds_tfa_defconfig | 54 +++++++++ include/configs/ls1043aqds.h | 50 +++++++- 4 files changed, 259 insertions(+), 3 deletions(-) create mode 100644 configs/ls1043aqds_tfa_defconfig
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index efc441a917..d29a3ad797 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -108,6 +108,16 @@ found: #endif }
+#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -131,3 +141,4 @@ int fsl_initdram(void)
return 0; } +#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 4fba57242b..9a1ff8034f 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -13,6 +13,7 @@ #include <asm/arch/ppa.h> #include <asm/arch/fdt.h> #include <asm/arch/mmu.h> +#include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -45,8 +46,135 @@ enum { #define CFG_UART_MUX_SHIFT 1 #define CFG_LPUART_EN 0x1
+#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} +#endif + int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -54,6 +182,12 @@ int checkboard(void)
puts("Board: LS1043AQDS, boot from ");
+#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -72,6 +206,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif
+#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch));
@@ -155,7 +292,8 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif @@ -383,3 +521,10 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_TFABOOT +void *env_sf_get_env_addr(void) +{ + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig new file mode 100644 index 0000000000..149a26ef33 --- /dev/null +++ b/configs/ls1043aqds_tfa_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 68f202f97a..ed07d9f28e 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -196,7 +196,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT #endif @@ -251,6 +252,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -318,6 +353,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif
/* * I2C bus multiplexer @@ -349,7 +385,8 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MAX 1212
/* QSPI device */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION @@ -381,6 +418,14 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -397,6 +442,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif
#define CONFIG_CMDLINE_TAG
From: Vinitha V Pillai vinitha.pillai@nxp.com
This defconfig is for Secure TFABOOT, to be loaded by trusted firmware
Signed-off-by: Vinitha V Pillai vinitha.pillai@nxp.com --- Change in v2: None
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 58 ++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..268be5df83 --- /dev/null +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_DM=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_CAAM=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y
TFABOOT support includes: - ls1012ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Pankit Garg pankit.garg@nxp.com --- Change in v2: - Merged ls1012ardb TFA boot support patches - Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1012ardb/ls1012ardb.c | 16 ++++++- configs/ls1012ardb_tfa_defconfig | 56 +++++++++++++++++++++++++ include/configs/ls1012a_common.h | 16 ++++++- include/configs/ls1012ardb.h | 6 +++ 4 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 configs/ls1012ardb_tfa_defconfig
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 888f8500d4..f648a9040b 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -87,8 +87,19 @@ int checkboard(void) return 0; }
+#ifdef CONFIG_TFABOOT int dram_init(void) { + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#else +int dram_init(void) +{ +#ifndef CONFIG_TFABOOT static const struct fsl_mmdc_info mparam = { 0x05180000, /* mdctl */ 0x00030035, /* mdpdc */ @@ -106,6 +117,7 @@ int dram_init(void) };
mmdc_init(&mparam); +#endif
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) @@ -115,6 +127,7 @@ int dram_init(void)
return 0; } +#endif
int board_early_init_f(void) @@ -132,7 +145,8 @@ int board_init(void) * Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig new file mode 100644 index 0000000000..e594bd6b21 --- /dev/null +++ b/configs/ls1012ardb_tfa_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 787adbc382..324dba2b7e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -16,7 +16,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -34,7 +38,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*SPI device */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_ENV_SPI_BUS 0 @@ -58,7 +62,11 @@ #define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 0x40000 /* 256KB */ +#ifdef CONFIG_TFABOOT +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#else #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#endif #define CONFIG_ENV_SECT_SIZE 0x40000 #endif
@@ -106,9 +114,15 @@ "kernel_size=0x2800000\0" \
#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ + "$kernel_start $kernel_size && "\ + "bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" +#endif
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 17554ea955..f149a604cf 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -112,8 +112,14 @@ "bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else #define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" +#endif
#include <asm/fsl_secure_boot.h>
On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
Includes changes in u-boot framework to support TF-A for NXP Chassis 2 platforms. A new defconfig is added namely ls*_ram_defconfig which will be used for all boot sources when TF-A is used.
Tested on LS1043A, LS1046A and LS1012A platforms.
Changes in v2:
- Patch subject and description changes
- Removed extra CONFIG_TFABOOT flag usage
- Merged board specific TFA boot support patches
- Checked compilation using buildman tool for each commit
Please check again. I see compiling warning on ls2080aqds_nand ls1046aqds_nand ls1043aqds_nand ls1043ardb_nand ls2080ardb_nand after patch #2, seems to be fix by patch #4. You may squash these two patches.
York
-----Original Message----- From: York Sun Sent: Monday, October 8, 2018 10:11 PM To: Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms
On 10/07/2018 03:21 AM, Rajesh Bhagat wrote:
Includes changes in u-boot framework to support TF-A for NXP Chassis 2 platforms. A new defconfig is added namely ls*_ram_defconfig which will be used for all boot sources when TF-A is used.
Tested on LS1043A, LS1046A and LS1012A platforms.
Changes in v2:
- Patch subject and description changes
- Removed extra CONFIG_TFABOOT flag usage
- Merged board specific TFA boot support patches
- Checked compilation using buildman tool for each commit
Please check again. I see compiling warning on ls2080aqds_nand ls1046aqds_nand ls1043aqds_nand ls1043ardb_nand ls2080ardb_nand after patch #2, seems to be fix by patch #4. You may squash these two patches.
Will take care in next version, will check for other warnings too.
Regards, Rajesh Bhagat
York
participants (2)
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Rajesh Bhagat -
York Sun