[U-Boot] [PATCH v2 1/3] rockchip: rk3399: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF.
The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: - add update for leez board - add other related patch
configs/evb-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/leez-rk3399_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/roc-rk3399-pc_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - 13 files changed, 13 deletions(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index a0d215a5f1..48836c7b88 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index d022631465..4828f0ccac 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index acfd91dbe7..19e1350285 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index b71fd3a286..c10f710b42 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 0a789872dc..9b3b6bf634 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 4757aaaec4..35f3a8cfd8 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 1d4c8f8a02..b266b3ff41 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 7375b758a2..c78dd106e8 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 874ee5efb6..48413cfe61 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 7b02c59f08..28f5ae18b1 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig index 28b18333d7..79c128a929 100644 --- a/configs/roc-rk3399-pc_defconfig +++ b/configs/roc-rk3399-pc_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 554945dd19..dbff125bf1 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 22b8bc503b..e876533304 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config; default to 0x4000000(64MB) instead of 0x80000(512KB) for this address can support all the SoCs including those may have only 64MB memory, and also reserve enough space for atf, kernel(in falcon mode) loading.
After the ATF entry move to 0x40000, the stack from 0x80000 may be override when loading ATF bl31.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: None
arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/leez-rk3399_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/roc-rk3399-pc_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - 18 files changed, 3 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 6660d05349..f781eacd16 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -91,6 +91,9 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000
+config SPL_STACK_R_ADDR + default 0x04000000 + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 8059c633ce..b6e31a4c49 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -8,7 +8,6 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC_SUPPORT is not set CONFIG_TARGET_CHROMEBOOK_BOB=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 48836c7b88..c1d7d613a9 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 05bbfbf381..0dcc9a760d 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 4828f0ccac..ba57fbd527 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 19e1350285..80d92e1aad 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index c10f710b42..9ba25b7d57 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 9b3b6bf634..424dec1fba 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 35f3a8cfd8..c671879d9a 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index b266b3ff41..ae09273a48 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index c78dd106e8..e1a61e5a57 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 48413cfe61..c3a592d8fe 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 28f5ae18b1..296fd5f0a0 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 30b0f4ac6c..351b0ea3d0 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -6,7 +6,6 @@ CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_TARGET_PUMA_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig index 79c128a929..809f522236 100644 --- a/configs/roc-rk3399-pc_defconfig +++ b/configs/roc-rk3399-pc_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index dbff125bf1..f4bb3818ce 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index cb3c68db6b..0d6c55ce74 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index e876533304..68f0dca7b2 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: None
include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 3ff3331c80..e51e1b0e0e 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -18,7 +18,7 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x2000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index e4b2114a0d..e57d0efa7f 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -27,7 +27,7 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00280000
-#define CONFIG_SPL_MAX_SIZE 0x60000 +#define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x400000 #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 #define CONFIG_SPL_STACK 0x00188000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 126c34763e..7331c6dc02 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -21,7 +21,7 @@
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) #define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x00400000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #else
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang kever.yang@rock-chips.com I tested this
series on top of v2019.10 with rockpro64-rk3399_defconfig. While it builds fine, it does not work properly: U-Boot TPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53 +0200) Trying to boot from MMC1 U-Boot TPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53) [boot loop] Size of u-boot-spl-nodtb.bin is 387k, so it does not fit in 256K. (Overlap in data section?) Earlier I tried the same u-boot version without this series but with bl31 entry point patched to 0x80000. This loads fine. One question, just for me to understand: Why do we load u-boot SPL into limited space below bl31? Since we do not return to SPL from bl31, we should not need to place SPL in secure DRAM. What do I miss here? Thanks, Soeren
On 2019/10/21 下午6:06, Soeren Moch wrote:
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang kever.yang@rock-chips.com I tested this
series on top of v2019.10 with rockpro64-rk3399_defconfig. While it builds fine, it does not work properly: U-Boot TPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53 +0200) Trying to boot from MMC1 U-Boot TPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53) [boot loop] Size of u-boot-spl-nodtb.bin is 387k, so it does not fit in 256K. (Overlap in data section?)
If CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 is removed, the size should be much smaller,
could you help to check the .config?
Earlier I tried the same u-boot version without this series but with bl31 entry point patched to 0x80000. This loads fine.
This series is to adapt the BL31 entry move to 0x40000.
One question, just for me to understand: Why do we load u-boot SPL into limited space below bl31? Since we do not return to SPL from bl31, we should not need to place SPL in secure DRAM. What do I miss here?
The SPL is load by BootRom, and it always load/entry at offset 0 of DRAM, if we don't want to do
any relocate, it always below bl31.
Since the CPU is in secure move when running SPL, so it's fine to place it in secure DRAM,
the memory is secure or non secure is defined in bl31 and later.
Thanks,
- Kever
Thanks, Soeren
On 21.10.19 12:15, Kever Yang wrote:
On 2019/10/21 下午6:06, Soeren Moch wrote:
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang kever.yang@rock-chips.com I tested
this series on top of v2019.10 with rockpro64-rk3399_defconfig. While it builds fine, it does not work properly: U-Boot TPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53 +0200) Trying to boot from MMC1 U-Boot TPL 2019.10-00005-g7a0826a4f7-dirty (Oct 21 2019 - 10:12:53) [boot loop] Size of u-boot-spl-nodtb.bin is 387k, so it does not fit in 256K. (Overlap in data section?)
If CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 is removed, the size should be much smaller,
could you help to check the .config?
Yes, indeed, thanks. My mistake in merging. SPL is much smaller now.
When I tried to start this newly built idbloader, unfortunately my RockPro64 board died. It also is not able to start with other SD cards and images anymore. Very sad.
Earlier I tried the same u-boot version without this series but with bl31 entry point patched to 0x80000. This loads fine.
This series is to adapt the BL31 entry move to 0x40000.
Of course. I tried this before you sent this series.
One question, just for me to understand: Why do we load u-boot SPL into limited space below bl31? Since we do not return to SPL from bl31, we should not need to place SPL in secure DRAM. What do I miss here?
The SPL is load by BootRom, and it always load/entry at offset 0 of DRAM, if we don't want to do
any relocate, it always below bl31.
Ah, BootRom can load TPL to arbitrary places, but then SPL can only be loaded to address zero!? Anyway, with the smaller SPL it should be fine this way.
Unfortunately I cannot test since my board broke down.
Regards, Soeren
Since the CPU is in secure move when running SPL, so it's fine to place it in secure DRAM,
the memory is secure or non secure is defined in bl31 and later.
Thanks,
- Kever
Thanks, Soeren
participants (2)
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Kever Yang -
Soeren Moch