[U-Boot] i.MX6 Solo and Dual Lite
Hi all,
We're preparing to launch i.MX6 Solo/Dual-Lite and Dual versions of our Nitrogen6X product line.
We made a couple of stabs at patches to support these processor variants in September and October last year.
The first attempt added run-time detection using i.MX plugins: http://lists.denx.de/pipermail/u-boot/2012-September/#134442
It was soundly rejected.
The second attempt added preprocessor support to imximage in order to allow a single board definition file to be compiled for each processor variant. http://lists.denx.de/pipermail/u-boot/2012-September/#134442
We think the approach was generally agreed to based on this comment from Tom: http://lists.denx.de/pipermail/u-boot/2012-October/137611.html
And a follow-up patch from Troy: http://lists.denx.de/pipermail/u-boot/2012-October/138162.html
But things seemed to stall here: http://lists.denx.de/pipermail/u-boot/2012-November/139918.html
Troy submitted a number of other patches, including some fixes to the DDR initialization, but they were all made based on a 'preprocessorized' version of mx6q_4x_mt41j128.cfg.
Troy and I also had some discussion surrounding **how** the preprocessor was used to define the differences between processors: http://lists.denx.de/pipermail/u-boot/2012-October/136751.html
In a nutshell, the current patch set uses a set of preprocessor macros to configure things for each. For example, this macro call in the file mx6q_4x_mt41j128.cfg will write either 0x48254A36 (Quad or Dual) or 0x3F3F3035 (Dual-Lite/Solo) to register MMDC_P1_MPWRDLCTL:
WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
Nobody else seemed to comment on this, and it seems pretty critical.
Can we get some feedback before we prepare V2/V3 patches?
Our expectation is that we'll submit patches for each of the following configurations of Nitrogen6X:
nitrogen6q - Dual/Quad 1GB nitrogen6q2g - Dual/Quad 2GB nitrogen6solo - Solo 512MB nitrogen6duallite - Dual Lite 512MB nitrogen6solo1G - Solo 1GB nitrogen6duallite1G - Dual Lite 1GB
Our hope is that we can do this with essentially one code base but a separate .cfg file or #ifdefs for each.
A single include/config/nitrogen6x.h with #ifdefs should allow us to exclude those features (e.g. SATA) on the Solo and Dual-Lite.
Please advise,
Eric
On 16/01/2013 23:33, Eric Nelson wrote:
Hi all,
Hi Eric,
We're preparing to launch i.MX6 Solo/Dual-Lite and Dual versions of our Nitrogen6X product line.
We made a couple of stabs at patches to support these processor variants in September and October last year.
The first attempt added run-time detection using i.MX plugins: http://lists.denx.de/pipermail/u-boot/2012-September/#134442
It was soundly rejected.
The second attempt added preprocessor support to imximage in order to allow a single board definition file to be compiled for each processor variant. http://lists.denx.de/pipermail/u-boot/2012-September/#134442
We think the approach was generally agreed to based on this comment from Tom: http://lists.denx.de/pipermail/u-boot/2012-October/137611.html
And a follow-up patch from Troy: http://lists.denx.de/pipermail/u-boot/2012-October/138162.html
But things seemed to stall here: http://lists.denx.de/pipermail/u-boot/2012-November/139918.html
Right, also if the issue (where adding rule for a single SOC or SOC family) is marginal for this patchset.
Troy submitted a number of other patches, including some fixes to the DDR initialization, but they were all made based on a 'preprocessorized' version of mx6q_4x_mt41j128.cfg.
Troy and I also had some discussion surrounding **how** the preprocessor was used to define the differences between processors: http://lists.denx.de/pipermail/u-boot/2012-October/136751.html
In a nutshell, the current patch set uses a set of preprocessor macros to configure things for each. For example, this macro call in the file mx6q_4x_mt41j128.cfg will write either 0x48254A36 (Quad or Dual) or 0x3F3F3035 (Dual-Lite/Solo) to register MMDC_P1_MPWRDLCTL:
WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
I read the patch and your comment on ML and agree with your comment. It seems to me that it is very tricky to add this macro to make possible to have a single imximage.cfg file. And, as you remark, this will work now with these set on boards, but things can be different with new SOC version.
The concept here is that the processors use a different internal base address, and depending on this address, the macro does its work, writing on the selected address. But again, IMHO it is tricky, and it is strictly bound to i.MX6 when imximage is thought for all i.MX processors.
Let's say, instead of it, I prefer the solution using the preprocessor or as you suggest, using different .cfg files for the memory configurations.
Nobody else seemed to comment on this, and it seems pretty critical.
Can we get some feedback before we prepare V2/V3 patches?
Our expectation is that we'll submit patches for each of the following configurations of Nitrogen6X:
nitrogen6q - Dual/Quad 1GB nitrogen6q2g - Dual/Quad 2GB nitrogen6solo - Solo 512MB nitrogen6duallite - Dual Lite 512MB nitrogen6solo1G - Solo 1GB nitrogen6duallite1G - Dual Lite 1GBOur hope is that we can do this with essentially one code base but a separate .cfg file or #ifdefs for each.
I agree on this, but then do we still need WRITE_ENTRY2() ? I miss why we need if you use separate .cfg files.
A single include/config/nitrogen6x.h with #ifdefs should allow us to exclude those features (e.g. SATA) on the Solo and Dual-Lite.
Right, I think it is a good solution.
Best regards, Stefano Babic
Thanks for the feedback Stefano.
On 01/18/2013 06:55 AM, Stefano Babic wrote:
On 16/01/2013 23:33, Eric Nelson wrote:
Hi all,
<snip>
Troy and I also had some discussion surrounding **how** the preprocessor was used to define the differences between processors: http://lists.denx.de/pipermail/u-boot/2012-October/136751.html
In a nutshell, the current patch set uses a set of preprocessor macros to configure things for each. For example, this macro call in the file mx6q_4x_mt41j128.cfg will write either 0x48254A36 (Quad or Dual) or 0x3F3F3035 (Dual-Lite/Solo) to register MMDC_P1_MPWRDLCTL:
WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)I read the patch and your comment on ML and agree with your comment. It seems to me that it is very tricky to add this macro to make possible to have a single imximage.cfg file. And, as you remark, this will work now with these set on boards, but things can be different with new SOC version.
Or even a different memory configuration. For example, this line in the updated mx6q_4x_mt41j128.cfg file sets a value of 0x831A0000 to the MMDC_MDCTL register for Quad/Dual or Dual-Lite devices, but a value of 0x83190000 on Solo-Lite.
In English, this sets up a 64-bit memory bus except on Solo-Lite. Since designs like ours do allow the use of a 32-bit bus on a Quad Core machine, trying to represent all of the choices in a single file doesn't scale.
WRITE_ENTRY3(MMDC_P0 + MMDC_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
The concept here is that the processors use a different internal base address, and depending on this address, the macro does its work, writing on the selected address. But again, IMHO it is tricky, and it is strictly bound to i.MX6 when imximage is thought for all i.MX processors.
Let's say, instead of it, I prefer the solution using the preprocessor or as you suggest, using different .cfg files for the memory configurations.
Yep. We'll proceed with the separate file approach.
Nobody else seemed to comment on this, and it seems pretty critical.
Can we get some feedback before we prepare V2/V3 patches?
Our expectation is that we'll submit patches for each of the following configurations of Nitrogen6X:
nitrogen6q - Dual/Quad 1GB nitrogen6q2g - Dual/Quad 2GB nitrogen6solo - Solo 512MB nitrogen6duallite - Dual Lite 512MB nitrogen6solo1G - Solo 1GB nitrogen6duallite1G - Dual Lite 1GBOur hope is that we can do this with essentially one code base but a separate .cfg file or #ifdefs for each.
I agree on this, but then do we still need WRITE_ENTRY2() ? I miss why we need if you use separate .cfg files.
No. We don't.
A single include/config/nitrogen6x.h with #ifdefs should allow us to exclude those features (e.g. SATA) on the Solo and Dual-Lite.
Right, I think it is a good solution.
Thanks again. I think we have a plan.
Regards,
Eric
On 19/01/2013 20:09, Eric Nelson wrote:
Or even a different memory configuration. For example, this line in the updated mx6q_4x_mt41j128.cfg file sets a value of 0x831A0000 to the MMDC_MDCTL register for Quad/Dual or Dual-Lite devices, but a value of 0x83190000 on Solo-Lite.
Right - this is not strictly related to i.MX6, and we have also in the past, for example when different revisions of the same board have different memory chips, and different cfg files were used.
In English, this sets up a 64-bit memory bus except on Solo-Lite. Since designs like ours do allow the use of a 32-bit bus on a Quad Core machine, trying to represent all of the choices in a single file doesn't scale.
WRITE_ENTRY3(MMDC_P0 + MMDC_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
Right
The concept here is that the processors use a different internal base address, and depending on this address, the macro does its work, writing on the selected address. But again, IMHO it is tricky, and it is strictly bound to i.MX6 when imximage is thought for all i.MX processors.
Let's say, instead of it, I prefer the solution using the preprocessor or as you suggest, using different .cfg files for the memory configurations.
Yep. We'll proceed with the separate file approach.
Nice, I will wait for your patches !
Best regards, Stefano Babic
participants (2)
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Eric Nelson -
Stefano Babic