[U-Boot] [PATCH v2 1/4] efikamx: move and rename Efika MX directories and config files to prepare for new boards
* Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory * Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/{efikamx => genesi/mx51_efikamx}/Makefile | 0 .../{efikamx => genesi/mx51_efikamx}/efikamx-usb.c | 2 +- board/{efikamx => genesi/mx51_efikamx}/efikamx.c | 0 .../mx51_efikamx}/imximage_mx.cfg | 0 .../mx51_efikamx}/imximage_sb.cfg | 0 boards.cfg | 4 ++-- include/configs/{efikamx.h => mx51_efikamx.h} | 0 7 files changed, 3 insertions(+), 3 deletions(-) rename board/{efikamx => genesi/mx51_efikamx}/Makefile (100%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx-usb.c (99%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx.c (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_mx.cfg (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_sb.cfg (100%) rename include/configs/{efikamx.h => mx51_efikamx.h} (100%)
diff --git a/board/efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile similarity index 100% rename from board/efikamx/Makefile rename to board/genesi/mx51_efikamx/Makefile diff --git a/board/efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c similarity index 99% rename from board/efikamx/efikamx-usb.c rename to board/genesi/mx51_efikamx/efikamx-usb.c index 618b39d..e9273d0 100644 --- a/board/efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -33,7 +33,7 @@ #include <usb/ulpi.h> #include <errno.h>
-#include "../../drivers/usb/host/ehci.h" +#include "../../../drivers/usb/host/ehci.h"
/* USB pin configuration */ #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ diff --git a/board/efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c similarity index 100% rename from board/efikamx/efikamx.c rename to board/genesi/mx51_efikamx/efikamx.c diff --git a/board/efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg similarity index 100% rename from board/efikamx/imximage_mx.cfg rename to board/genesi/mx51_efikamx/imximage_mx.cfg diff --git a/board/efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg similarity index 100% rename from board/efikamx/imximage_sb.cfg rename to board/genesi/mx51_efikamx/imximage_sb.cfg diff --git a/boards.cfg b/boards.cfg index edd750c..a9ec44b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -215,8 +215,8 @@ integratorcp_cm946es arm arm946es integrator armltd ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx highbank arm armv7 highbank - highbank -efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg -efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg +mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg +mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg diff --git a/include/configs/efikamx.h b/include/configs/mx51_efikamx.h similarity index 100% rename from include/configs/efikamx.h rename to include/configs/mx51_efikamx.h
Efika MX boards configure their DDR pad settings twice, one in the DCD generated from imximage_*.cfg and again in init_drive_strength called before relocation.
Rather than doing this, roll the changes it makes into the DCD so DDR is set up before a single line of code in U-Boot is run.
The settings are identical with this DCD block which is shorter (by 7 entries) than the old one, and after the output of init_drive_strength since a lot of the functionality in the existing DCD and init_drive_strength function was just setting the POR defaults. This goes to explain some now-missing entries.
Several hundred rounds of mtest have been run to test the settings before and after to confirm DDR is stable and no ill-effects have been found.
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/genesi/mx51_efikamx/efikamx.c | 77 ----------------------------- board/genesi/mx51_efikamx/imximage_mx.cfg | 42 +++++++--------- 2 files changed, 18 insertions(+), 101 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index e88b2ed..12371c9 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -597,85 +597,8 @@ void efikamx_toggle_led(uint32_t mask) /* * Board initialization */ -static void init_drive_strength(void) -{ - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); - - /* Setting pad options */ - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} - int board_early_init_f(void) { - init_drive_strength(); - setup_iomux_uart(); setup_iomux_spi(); setup_iomux_led(); diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ea6b271 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,5 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com +# Copyright (C) 2009-2012 Genesi USA, Inc. # # BASED ON: imx51evk # @@ -43,30 +45,22 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
-# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4 - -DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa84ac 0xc5 # SDWE +DATA 4 0x73fa84b0 0xc5 # SDCKE0 +DATA 4 0x73fa84b4 0xc5 # SDCKE1 +DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 +DATA 4 0x73fa882c 0x2 # DRAM_B4 +DATA 4 0x73fa88a4 0x2 # DRAM_B0 +DATA 4 0x73fa88ac 0x2 # DRAM_B1 +DATA 4 0x73fa88b8 0x2 # DRAM_B2 +DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 +DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 +DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 +DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
# Setting DDR for micron # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
On 22/08/2012 21:25, Matt Sealey wrote:
Efika MX boards configure their DDR pad settings twice, one in the DCD generated from imximage_*.cfg and again in init_drive_strength called before relocation.
Rather than doing this, roll the changes it makes into the DCD so DDR is set up before a single line of code in U-Boot is run.
The settings are identical with this DCD block which is shorter (by 7 entries) than the old one, and after the output of init_drive_strength since a lot of the functionality in the existing DCD and init_drive_strength function was just setting the POR defaults. This goes to explain some now-missing entries.
Several hundred rounds of mtest have been run to test the settings before and after to confirm DDR is stable and no ill-effects have been found.
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/genesi/mx51_efikamx/efikamx.c | 77 ----------------------------- board/genesi/mx51_efikamx/imximage_mx.cfg | 42 +++++++--------- 2 files changed, 18 insertions(+), 101 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index e88b2ed..12371c9 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -597,85 +597,8 @@ void efikamx_toggle_led(uint32_t mask) /*
- Board initialization
*/ -static void init_drive_strength(void) -{
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
- /* Setting pad options */
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);-}
int board_early_init_f(void) {
- init_drive_strength();
- setup_iomux_uart(); setup_iomux_spi(); setup_iomux_led();
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ea6b271 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,5 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com +# Copyright (C) 2009-2012 Genesi USA, Inc. # # BASED ON: imx51evk # @@ -43,30 +45,22 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
-# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4
-DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa84ac 0xc5 # SDWE +DATA 4 0x73fa84b0 0xc5 # SDCKE0 +DATA 4 0x73fa84b4 0xc5 # SDCKE1 +DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 +DATA 4 0x73fa882c 0x2 # DRAM_B4 +DATA 4 0x73fa88a4 0x2 # DRAM_B0 +DATA 4 0x73fa88ac 0x2 # DRAM_B1 +DATA 4 0x73fa88b8 0x2 # DRAM_B2 +DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 +DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 +DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 +DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
# Setting DDR for micron # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 22/08/2012 21:25, Matt Sealey wrote:
Efika MX boards configure their DDR pad settings twice, one in the DCD generated from imximage_*.cfg and again in init_drive_strength called before relocation.
Rather than doing this, roll the changes it makes into the DCD so DDR is set up before a single line of code in U-Boot is run.
The settings are identical with this DCD block which is shorter (by 7 entries) than the old one, and after the output of init_drive_strength since a lot of the functionality in the existing DCD and init_drive_strength function was just setting the POR defaults. This goes to explain some now-missing entries.
Several hundred rounds of mtest have been run to test the settings before and after to confirm DDR is stable and no ill-effects have been found.
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/genesi/mx51_efikamx/efikamx.c | 77 ----------------------------- board/genesi/mx51_efikamx/imximage_mx.cfg | 42 +++++++--------- 2 files changed, 18 insertions(+), 101 deletions(-)
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
PCBID pads seem to need time to settle due to external pulldowns, otherwise we are reading floating GPIO pins with implicit pad pullups and get the wrong data. However we can't "wait" at the time we need them before relocation, since timers are not available. The time taken to get from DCD to the code requiring the pads set seems to be more than long enough (even with caches enabled).
We have space in the DCD due to the DDR settings changes to configure all the pad settings we need for this, plus the LED pad settings too which reduces the amount of code required later on.
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/genesi/mx51_efikamx/imximage_mx.cfg | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index ea6b271..38fa760 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -45,6 +45,16 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
+# Essential GPIO settings to be done as early as possible +# PCBIDn pad settings are all the defaults except #2 which needs HVE off +DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 +DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 +DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 +DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE +DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 +DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 +DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15 + # DDR bus IOMUX PAD settings DATA 4 0x73fa850c 0x20c5 # SDODT1 DATA 4 0x73fa8510 0x20c5 # SDODT0
On 22/08/2012 21:25, Matt Sealey wrote:
PCBID pads seem to need time to settle due to external pulldowns, otherwise we are reading floating GPIO pins with implicit pad pullups and get the wrong data. However we can't "wait" at the time we need them before relocation, since timers are not available. The time taken to get from DCD to the code requiring the pads set seems to be more than long enough (even with caches enabled).
We have space in the DCD due to the DDR settings changes to configure all the pad settings we need for this, plus the LED pad settings too which reduces the amount of code required later on.
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/genesi/mx51_efikamx/imximage_mx.cfg | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index ea6b271..38fa760 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -45,6 +45,16 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
+# Essential GPIO settings to be done as early as possible +# PCBIDn pad settings are all the defaults except #2 which needs HVE off +DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 +DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 +DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 +DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE +DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 +DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 +DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
# DDR bus IOMUX PAD settings DATA 4 0x73fa850c 0x20c5 # SDODT1 DATA 4 0x73fa8510 0x20c5 # SDODT0
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 22/08/2012 21:25, Matt Sealey wrote:
PCBID pads seem to need time to settle due to external pulldowns, otherwise we are reading floating GPIO pins with implicit pad pullups and get the wrong data. However we can't "wait" at the time we need them before relocation, since timers are not available. The time taken to get from DCD to the code requiring the pads set seems to be more than long enough (even with caches enabled).
We have space in the DCD due to the DDR settings changes to configure all the pad settings we need for this, plus the LED pad settings too which reduces the amount of code required later on.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
This is a rework of a previously submitted patchset and bundles the main board support and USB support into a single commit.
It requires the patch "mx5: add iomux-mx51.h include"
* Use iomux-mx51.h include to simplify board configuration. * Simplify LED support (remove efikamx_toggle_led, change lit LEDs). * Simplify MMC support for CD and WP pin differences. * Fix broken CPU voltage setting - comment said 1.1V but the code set to 1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and all available Linux kernels would drop the voltage to 1.1V anyway and work reliably. This should lower power consumption during the boot process. * Function renames for readability. * Some board identification string changes to match actual product names.
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/genesi/mx51_efikamx/efikamx-usb.c | 159 ++++---- board/genesi/mx51_efikamx/efikamx.c | 603 ++++++++++++------------------- 2 files changed, 298 insertions(+), 464 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index e9273d0..abd358a 100644 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -1,7 +1,7 @@ /* + * Copyright (C) 2009 Freescale Semiconductor, Inc. * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2012 Genesi USA, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,9 +25,7 @@ #include <common.h> #include <usb.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <usb/ehci-fsl.h> #include <usb/ulpi.h> @@ -35,103 +33,93 @@
#include "../../../drivers/usb/host/ehci.h"
-/* USB pin configuration */ -#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ - PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) - -/* - * Configure the USB H1 and USB H2 IOMUX - */ -void setup_iomux_usb(void) -{ - setup_iomux_usb_h1(); - - if (machine_is_efikasb()) - setup_iomux_usb_h2(); - - /* USB PHY reset */ - mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* USB HUB reset */ - mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* WIFI EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0); - /* WIFI RESET */ - mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0); - /* BT EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0); -} - -/* - * Enable devices connected to USB BUSes - */ -static void efika_usb_enable_devices(void) +static iomux_v3_cfg_t efikamx_usbh1_pads[] = { + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, +}; + +static iomux_v3_cfg_t efikasb_usbh2_pads[] = { + MX51_PAD_EIM_A24__USBH2_CLK, + MX51_PAD_EIM_A25__USBH2_DIR, + MX51_PAD_EIM_A26__USBH2_STP, + MX51_PAD_EIM_A27__USBH2_NXT, + MX51_PAD_EIM_D16__USBH2_DATA0, + MX51_PAD_EIM_D17__USBH2_DATA1, + MX51_PAD_EIM_D18__USBH2_DATA2, + MX51_PAD_EIM_D19__USBH2_DATA3, + MX51_PAD_EIM_D20__USBH2_DATA4, + MX51_PAD_EIM_D21__USBH2_DATA5, + MX51_PAD_EIM_D22__USBH2_DATA6, + MX51_PAD_EIM_D23__USBH2_DATA7, +}; + +static iomux_v3_cfg_t efikamx_usbctrl_pads[] = { + MX51_PAD_EIM_D27__GPIO2_9, + MX51_PAD_GPIO1_5__GPIO1_5, +}; + +#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) +#define EFIKAMX_USB_PHY_RESET IMX_GPIO_NR(2, 9) + +void efikamx_usb_setup_pads(void) { - /* Enable Bluetooth */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0); - udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1); + imx_iomux_v3_setup_multiple_pads(efikamx_usbh1_pads, ARRAY_SIZE(efikamx_usbh1_pads));
- /* Enable WiFi */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1); - udelay(10000); + if (machine_is_efikasb()) { + imx_iomux_v3_setup_multiple_pads(efikasb_usbh2_pads, ARRAY_SIZE(efikasb_usbh2_pads)); + }
- /* Reset the WiFi chip */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0); - udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1); + imx_iomux_v3_setup_multiple_pads(efikamx_usbctrl_pads, ARRAY_SIZE(efikamx_usbctrl_pads)); }
/* * Reset USB HUB (or HUBs on EfikaSB) */ -static void efika_usb_hub_reset(void) +static void efikamx_usb_hub_reset(void) { - /* HUB reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0); + gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); }
/* * Reset USB PHY (or PHYs on EfikaSB) */ -static void efika_usb_phy_reset(void) +static void efikamx_usb_phy_reset(void) { /* SMSC 3317 PHY reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0); + gpio_direction_output(EFIKAMX_USB_PHY_RESET, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1); + gpio_set_value(EFIKAMX_USB_PHY_RESET, 1); }
-static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, - uint32_t alt0, uint32_t alt1) +static void efikamx_usb_init(struct usb_ehci *ehci, + iomux_v3_cfg_t stp_pad, + iomux_v3_cfg_t gpio_pad, + u32 gpio_nr) { int ret; struct ulpi_regs *ulpi = (struct ulpi_regs *)0; struct ulpi_viewport ulpi_vp;
- mxc_request_iomux(stp_gpio, alt0); - mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0); + imx_iomux_v3_setup_pad(gpio_pad); + gpio_direction_output(gpio_nr, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1); + gpio_set_value(gpio_nr, 1); udelay(1000); - - mxc_request_iomux(stp_gpio, alt1); - mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG); + imx_iomux_v3_setup_pad(stp_pad); udelay(10000);
ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; @@ -159,18 +147,18 @@ static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, /* * Set VBusChrg * - * NOTE: This violates USB specification, but otherwise, USB on Efika + * NOTE: This violates USB specification, but otherwise, USB on Efika MX * doesn't work. */ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); + + mdelay(10); }
int board_ehci_hcd_init(int port) { - /* Init iMX51 EHCI */ - efika_usb_phy_reset(); - efika_usb_hub_reset(); - efika_usb_enable_devices(); + efikamx_usb_phy_reset(); + efikamx_usb_hub_reset();
return 0; } @@ -204,13 +192,12 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) tmp = (tmp & ~0x3) | 0x01; writel(tmp, OTG_BASE_ADDR + 0x80c); } else if (port == 1) { - efika_ehci_init(ehci, MX51_PIN_USBH1_STP, - IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0); + efikamx_usb_init(ehci, MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_STP__GPIO1_27, + IMX_GPIO_NR(1, 27)); } else if ((port == 2) && machine_is_efikasb()) { - efika_ehci_init(ehci, MX51_PIN_EIM_A26, - IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2); + efikamx_usb_init(ehci, MX51_PAD_EIM_A26__USBH2_STP, + MX51_PAD_EIM_A26__GPIO2_20, + IMX_GPIO_NR(2, 20)); } - - if (port) - mdelay(10); } diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 12371c9..b9064fb 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -1,7 +1,7 @@ /* + * Copyright (C) 2009 Freescale Semiconductor, Inc. * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2012 Genesi USA, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -24,9 +24,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> @@ -48,16 +46,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif
/* - * Shared variables / local defines + * Board revisions */ -/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4 - -void efikamx_toggle_led(uint32_t mask); - -/* Board revisions */ #define EFIKAMX_BOARD_REV_11 0x1 #define EFIKAMX_BOARD_REV_12 0x2 #define EFIKAMX_BOARD_REV_13 0x3 @@ -69,66 +59,67 @@ void efikamx_toggle_led(uint32_t mask); /* * Board identification */ -u32 get_efikamx_rev(void) +static u32 get_mx_rev(void) { u32 rev = 0; /* * Retrieve board ID: - * rev1.1: 1,1,1 - * rev1.2: 1,1,0 - * rev1.3: 1,0,1 - * rev1.4: 1,0,0 + * + * gpio: 16 17 11 + * ============== + * r1.1: 1+ 1 1 + * r1.2: 1 1 0 + * r1.3: 1 0 1 + * r1.4: 1 0 0 + * + * + note: r1.1 does not strap this pin properly so it needs to + * be hacked or ignored. */ - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - /* set to 1 in order to get correct value on board rev1.1 */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; + /* set to 1 in order to get correct value on board rev 1.1 */ + gpio_direction_output(IMX_GPIO_NR(3, 16), 1); + gpio_direction_input(IMX_GPIO_NR(3, 11)); + gpio_direction_input(IMX_GPIO_NR(3, 16)); + gpio_direction_input(IMX_GPIO_NR(3, 17));
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; - - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; + rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0; + rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1; + rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
return (~rev & 0x7) + 1; }
-inline u32 get_efikasb_rev(void) +static iomux_v3_cfg_t efikasb_revision_pads[] = { + MX51_PAD_EIM_CS3__GPIO2_28, + MX51_PAD_EIM_CS4__GPIO2_29, +}; + +static inline u32 get_sb_rev(void) { u32 rev = 0;
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; + imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, ARRAY_SIZE(efikasb_revision_pads)); + gpio_direction_input(IMX_GPIO_NR(2, 28)); + gpio_direction_input(IMX_GPIO_NR(2, 29));
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; + rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0; + rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
return rev; }
-inline uint32_t get_efika_rev(void) +inline uint32_t get_efikamx_rev(void) { - if (machine_is_efikamx()) - return get_efikamx_rev(); - else - return get_efikasb_rev(); + if (machine_is_efikamx()) { + return get_mx_rev(); + } else if (machine_is_efikasb()) { + return get_sb_rev(); + } }
u32 get_board_rev(void) { - return get_cpu_rev() | (get_efika_rev() << 8); + return get_cpu_rev() | (get_efikamx_rev() << 8); }
/* @@ -137,66 +128,35 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; }
/* * UART configuration */ -static void setup_iomux_uart(void) -{ - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; - - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); -} +static iomux_v3_cfg_t efikamx_uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +};
/* * SPI configuration */ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{ - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* Configure SS0 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); - - /* Configure SS1 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} -#else -static inline void setup_iomux_spi(void) { } -#endif +static iomux_v3_cfg_t efikamx_spi_pads[]= { + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_GPIO1_6__GPIO1_6, +}; + +#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24) +#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25) +#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
/* * PMIC configuration @@ -226,7 +186,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */ @@ -301,29 +261,64 @@ static inline void power_init(void) { } * MMC configuration */ #ifdef CONFIG_FSL_ESDHC + struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, };
-static inline uint32_t efika_mmc_cd(void) +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = { + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_1__SD1_WP, +}; + +#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1,1) + +static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = { + MX51_PAD_GPIO1_0__SD1_CD, + MX51_PAD_EIM_CS2__SD1_CD, +}; + +#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1,0) +#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2,27) + +static iomux_v3_cfg_t efikasb_sdhc2_pads[] = { + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_7__SD2_WP, + MX51_PAD_GPIO1_8__SD2_CD, +}; + +#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1,8) +#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1,7) + +static inline uint32_t efikamx_mmc_getcd(u32 base) { - if (machine_is_efikamx()) - return MX51_PIN_GPIO1_0; - else - return MX51_PIN_EIM_CS2; + if (base == MMC_SDHC1_BASE_ADDR) { + if (machine_is_efikamx()) { + return EFIKAMX_SDHC1_CD; + } else { + return EFIKASB_SDHC1_CD; + } + } else { + return EFIKASB_SDHC2_CD; + } }
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - uint32_t cd = efika_mmc_cd(); - int ret; - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); - else - ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base); + int ret = !gpio_get_value(cd);
return ret; } @@ -331,139 +326,35 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int ret; - uint32_t cd = efika_mmc_cd(); - - /* SDHC1 is used on all revisions, setup control pins first */ - mxc_request_iomux(cd, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(cd, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(cd)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); - - /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ - if (machine_is_efikasb() || (machine_is_efikamx() && - (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 IOMUX */ - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 Control lines IOMUX */ - mxc_request_iomux(MX51_PIN_GPIO1_7, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_8, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_8, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + /* + * All Efika MX boards use eSDHC1 with a common write-protect GPIO + */ + imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, ARRAY_SIZE(efikamx_sdhc1_pads)); + gpio_direction_input(EFIKAMX_SDHC1_WP); + + /* + * Smartbook and Smarttop differ on the location of eSDHC1 carrier-detect GPIO + */ + if (machine_is_efikamx()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]); + gpio_direction_input(EFIKAMX_SDHC1_CD); + } else if (machine_is_efikasb()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]); + gpio_direction_input(EFIKASB_SDHC1_CD); + } + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + /* + * Smartbook (any) and Smarttop (1.0, 1.1) use a second SD controller + */ + if (machine_is_efikasb() || (get_efikamx_rev() < EFIKAMX_BOARD_REV_12)) { + imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, ARRAY_SIZE(efikasb_sdhc2_pads)); + gpio_direction_input(EFIKASB_SDHC2_CD); + gpio_direction_input(EFIKASB_SDHC2_WP); if (!ret) ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); - } else { /* New boards use only SDHC1 */ - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); }
return ret; @@ -471,137 +362,100 @@ int board_mmc_init(bd_t *bis) #endif
/* - * ATA + * PATA */ -#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{ - mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); -} -#else -static inline void setup_iomux_ata(void) { } -#endif +static iomux_v3_cfg_t efikamx_pata_pads[] = { + MX51_PAD_NANDF_WE_B__PATA_DIOW, + MX51_PAD_NANDF_RE_B__PATA_DIOR, + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, + MX51_PAD_NANDF_CLE__PATA_RESET_B, + MX51_PAD_NANDF_WP_B__PATA_DMACK, + MX51_PAD_NANDF_RB0__PATA_DMARQ, + MX51_PAD_NANDF_RB1__PATA_IORDY, + MX51_PAD_GPIO_NAND__PATA_INTRQ, + MX51_PAD_NANDF_CS2__PATA_CS_0, + MX51_PAD_NANDF_CS3__PATA_CS_1, + MX51_PAD_NANDF_CS4__PATA_DA_0, + MX51_PAD_NANDF_CS5__PATA_DA_1, + MX51_PAD_NANDF_CS6__PATA_DA_2, + MX51_PAD_NANDF_D15__PATA_DATA15, + MX51_PAD_NANDF_D14__PATA_DATA14, + MX51_PAD_NANDF_D13__PATA_DATA13, + MX51_PAD_NANDF_D12__PATA_DATA12, + MX51_PAD_NANDF_D11__PATA_DATA11, + MX51_PAD_NANDF_D10__PATA_DATA10, + MX51_PAD_NANDF_D9__PATA_DATA9, + MX51_PAD_NANDF_D8__PATA_DATA8, + MX51_PAD_NANDF_D7__PATA_DATA7, + MX51_PAD_NANDF_D6__PATA_DATA6, + MX51_PAD_NANDF_D5__PATA_DATA5, + MX51_PAD_NANDF_D4__PATA_DATA4, + MX51_PAD_NANDF_D3__PATA_DATA3, + MX51_PAD_NANDF_D2__PATA_DATA2, + MX51_PAD_NANDF_D1__PATA_DATA1, + MX51_PAD_NANDF_D0__PATA_DATA0, +};
/* * EHCI USB */ #ifdef CONFIG_CMD_USB -extern void setup_iomux_usb(void); +extern void efikamx_usb_setup_pads(void); #else -static inline void setup_iomux_usb(void) { } +static inline void efikamx_usb_setup_pads(void) { } #endif
/* * LED configuration + * + * Smarttop LED pad config is done in the DCD + * */ -void setup_iomux_led(void) -{ - if (machine_is_efikamx()) { - /* Blue LED */ - mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); +#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13) +#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14) +#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
- /* Green LED */ - mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); - - /* Red LED */ - mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); - } else { - /* CAPS-LOCK LED */ - mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); - - /* ALARM-LED LED */ - mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); - } -} +static iomux_v3_cfg_t efikasb_led_pads[] = { + MX51_PAD_GPIO1_3__GPIO1_3, + MX51_PAD_EIM_CS0__GPIO2_25, +};
-void efikamx_toggle_led(uint32_t mask) -{ - if (machine_is_efikamx()) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - mask & EFIKAMX_LED_GREEN); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - mask & EFIKAMX_LED_RED); - } else { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), - !(mask & EFIKAMX_LED_GREEN)); - } -} +#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25) +#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
/* * Board initialization */ int board_early_init_f(void) { - setup_iomux_uart(); - setup_iomux_spi(); - setup_iomux_led(); + if (machine_is_efikasb()) { + imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, ARRAY_SIZE(efikasb_led_pads)); + gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0); + gpio_direction_output(EFIKASB_MESSAGE_LED, 1); + } else if (machine_is_efikamx()) { + /* + * Set up GPIO directions for LEDs. + * IOMUX has been done in the DCD already. + * Turn the red LED on for pre-relocation code. + */ + gpio_direction_output(EFIKAMX_LED_BLUE, 0); + gpio_direction_output(EFIKAMX_LED_GREEN, 0); + gpio_direction_output(EFIKAMX_LED_RED, 1); + } + + /* + * Both these pad configurations for UART and SPI are kind of redundant + * since they are the Power-On Defaults for the i.MX51. But, it seems we + * should make absolutely sure that they are set up correctly. + */ + imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, ARRAY_SIZE(efikamx_uart_pads)); + imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, ARRAY_SIZE(efikamx_spi_pads)); + + /* not technically required for U-Boot operation but set it up anyway. */ + gpio_direction_input(EFIKAMX_PMIC_IRQ); + /* Deselect both CS for now.. any other way and NOR doesn't probe properly. */ + gpio_direction_output(EFIKAMX_SPI_SS0, 0); + gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0; } @@ -615,43 +469,36 @@ int board_init(void)
int board_late_init(void) { - setup_iomux_spi(); + if (machine_is_efikamx()) { + /* + * Set up Blue LED for "In U-Boot" status. + * We're all relocated and ready to U-Boot! + */ + gpio_set_value(EFIKAMX_LED_RED, 0); + gpio_set_value(EFIKAMX_LED_GREEN, 0); + gpio_set_value(EFIKAMX_LED_BLUE, 1); + }
power_init();
- setup_iomux_led(); - setup_iomux_ata(); - setup_iomux_usb(); + imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, ARRAY_SIZE(efikamx_pata_pads)); + efikamx_usb_setup_pads();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
- setup_iomux_led(); - - efikamx_toggle_led(EFIKAMX_LED_BLUE); - return 0; }
int checkboard(void) { - u32 rev = get_efika_rev(); + u32 rev = get_efikamx_rev();
+ printf("Board: Genesi Efika MX "); if (machine_is_efikamx()) { - printf("Board: Efika MX, rev1.%i\n", rev & 0xf); - return 0; - } else { - switch (rev) { - case EFIKASB_BOARD_REV_13: - printf("Board: Efika SB rev1.3\n"); - break; - case EFIKASB_BOARD_REV_20: - printf("Board: Efika SB rev2.0\n"); - break; - default: - printf("Board: Efika SB, rev Unknown\n"); - break; - } + printf("Smarttop (1.%i)\n", rev & 0xf); + } else if (machine_is_efikasb()) { + printf("Smartbook\n"); }
return 0;
On 22/08/2012 21:25, Matt Sealey wrote:
This is a rework of a previously submitted patchset and bundles the main board support and USB support into a single commit.
It requires the patch "mx5: add iomux-mx51.h include"
- Use iomux-mx51.h include to simplify board configuration.
- Simplify LED support (remove efikamx_toggle_led, change lit LEDs).
- Simplify MMC support for CD and WP pin differences.
- Fix broken CPU voltage setting - comment said 1.1V but the code set to 1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and all available Linux kernels would drop the voltage to 1.1V anyway and work reliably. This should lower power consumption during the boot process.
- Function renames for readability.
- Some board identification string changes to match actual product names.
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/genesi/mx51_efikamx/efikamx-usb.c | 159 ++++---- board/genesi/mx51_efikamx/efikamx.c | 603 ++++++++++++------------------- 2 files changed, 298 insertions(+), 464 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index e9273d0..abd358a 100644 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -1,7 +1,7 @@ /*
- Copyright (C) 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com
- (C) Copyright 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2009-2012 Genesi USA, Inc.
- See file CREDITS for list of people who contributed to this
- project.
@@ -25,9 +25,7 @@ #include <common.h> #include <usb.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <usb/ehci-fsl.h> #include <usb/ulpi.h> @@ -35,103 +33,93 @@
#include "../../../drivers/usb/host/ehci.h"
-/* USB pin configuration */ -#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)-/*
- Configure the USB H1 and USB H2 IOMUX
- */
-void setup_iomux_usb(void) -{
- setup_iomux_usb_h1();
- if (machine_is_efikasb())
setup_iomux_usb_h2();- /* USB PHY reset */
- mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);- /* USB HUB reset */
- mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);- /* WIFI EN (act low) */
- mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
- /* WIFI RESET */
- mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
- /* BT EN (act low) */
- mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
-}
-/*
- Enable devices connected to USB BUSes
- */
-static void efika_usb_enable_devices(void) +static iomux_v3_cfg_t efikamx_usbh1_pads[] = {
- MX51_PAD_USBH1_CLK__USBH1_CLK,
- MX51_PAD_USBH1_DIR__USBH1_DIR,
- MX51_PAD_USBH1_STP__USBH1_STP,
- MX51_PAD_USBH1_NXT__USBH1_NXT,
- MX51_PAD_USBH1_DATA0__USBH1_DATA0,
- MX51_PAD_USBH1_DATA1__USBH1_DATA1,
- MX51_PAD_USBH1_DATA2__USBH1_DATA2,
- MX51_PAD_USBH1_DATA3__USBH1_DATA3,
- MX51_PAD_USBH1_DATA4__USBH1_DATA4,
- MX51_PAD_USBH1_DATA5__USBH1_DATA5,
- MX51_PAD_USBH1_DATA6__USBH1_DATA6,
- MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+};
+static iomux_v3_cfg_t efikasb_usbh2_pads[] = {
- MX51_PAD_EIM_A24__USBH2_CLK,
- MX51_PAD_EIM_A25__USBH2_DIR,
- MX51_PAD_EIM_A26__USBH2_STP,
- MX51_PAD_EIM_A27__USBH2_NXT,
- MX51_PAD_EIM_D16__USBH2_DATA0,
- MX51_PAD_EIM_D17__USBH2_DATA1,
- MX51_PAD_EIM_D18__USBH2_DATA2,
- MX51_PAD_EIM_D19__USBH2_DATA3,
- MX51_PAD_EIM_D20__USBH2_DATA4,
- MX51_PAD_EIM_D21__USBH2_DATA5,
- MX51_PAD_EIM_D22__USBH2_DATA6,
- MX51_PAD_EIM_D23__USBH2_DATA7,
+};
+static iomux_v3_cfg_t efikamx_usbctrl_pads[] = {
- MX51_PAD_EIM_D27__GPIO2_9,
- MX51_PAD_GPIO1_5__GPIO1_5,
+};
+#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) +#define EFIKAMX_USB_PHY_RESET IMX_GPIO_NR(2, 9)
+void efikamx_usb_setup_pads(void) {
- /* Enable Bluetooth */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
- udelay(10000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
- imx_iomux_v3_setup_multiple_pads(efikamx_usbh1_pads, ARRAY_SIZE(efikamx_usbh1_pads));
- /* Enable WiFi */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
- udelay(10000);
- if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_usbh2_pads, ARRAY_SIZE(efikasb_usbh2_pads));- }
- /* Reset the WiFi chip */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
- udelay(10000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
- imx_iomux_v3_setup_multiple_pads(efikamx_usbctrl_pads, ARRAY_SIZE(efikamx_usbctrl_pads));
}
/*
- Reset USB HUB (or HUBs on EfikaSB)
*/ -static void efika_usb_hub_reset(void) +static void efikamx_usb_hub_reset(void) {
- /* HUB reset */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
- gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
- gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
- gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
}
/*
- Reset USB PHY (or PHYs on EfikaSB)
*/ -static void efika_usb_phy_reset(void) +static void efikamx_usb_phy_reset(void) { /* SMSC 3317 PHY reset */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
- gpio_direction_output(EFIKAMX_USB_PHY_RESET, 0); udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
- gpio_set_value(EFIKAMX_USB_PHY_RESET, 1);
}
-static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
uint32_t alt0, uint32_t alt1)+static void efikamx_usb_init(struct usb_ehci *ehci,
iomux_v3_cfg_t stp_pad,iomux_v3_cfg_t gpio_pad,u32 gpio_nr){ int ret; struct ulpi_regs *ulpi = (struct ulpi_regs *)0; struct ulpi_viewport ulpi_vp;
- mxc_request_iomux(stp_gpio, alt0);
- mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);- gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0);
- imx_iomux_v3_setup_pad(gpio_pad);
- gpio_direction_output(gpio_nr, 0); udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1);
- gpio_set_value(gpio_nr, 1); udelay(1000);
- mxc_request_iomux(stp_gpio, alt1);
- mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG);
imx_iomux_v3_setup_pad(stp_pad); udelay(10000);
ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
@@ -159,18 +147,18 @@ static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, /* * Set VBusChrg *
* NOTE: This violates USB specification, but otherwise, USB on Efika
* NOTE: This violates USB specification, but otherwise, USB on Efika MX*/ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
- doesn't work.
- mdelay(10);
}
int board_ehci_hcd_init(int port) {
- /* Init iMX51 EHCI */
- efika_usb_phy_reset();
- efika_usb_hub_reset();
- efika_usb_enable_devices();
efikamx_usb_phy_reset();
efikamx_usb_hub_reset();
return 0;
} @@ -204,13 +192,12 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) tmp = (tmp & ~0x3) | 0x01; writel(tmp, OTG_BASE_ADDR + 0x80c); } else if (port == 1) {
efika_ehci_init(ehci, MX51_PIN_USBH1_STP,IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0);
efikamx_usb_init(ehci, MX51_PAD_USBH1_STP__USBH1_STP,MX51_PAD_USBH1_STP__GPIO1_27,IMX_GPIO_NR(1, 27));
efika_ehci_init(ehci, MX51_PIN_EIM_A26,IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2);
efikamx_usb_init(ehci, MX51_PAD_EIM_A26__USBH2_STP,MX51_PAD_EIM_A26__GPIO2_20,IMX_GPIO_NR(2, 20));
- if (port)
mdelay(10);} diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 12371c9..b9064fb 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -1,7 +1,7 @@ /*
- Copyright (C) 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com
- (C) Copyright 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2009-2012 Genesi USA, Inc.
- See file CREDITS for list of people who contributed to this
- project.
@@ -24,9 +24,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> @@ -48,16 +46,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif
/*
- Shared variables / local defines
*/
- Board revisions
-/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4
-void efikamx_toggle_led(uint32_t mask);
-/* Board revisions */ #define EFIKAMX_BOARD_REV_11 0x1 #define EFIKAMX_BOARD_REV_12 0x2 #define EFIKAMX_BOARD_REV_13 0x3 @@ -69,66 +59,67 @@ void efikamx_toggle_led(uint32_t mask); /*
- Board identification
*/ -u32 get_efikamx_rev(void) +static u32 get_mx_rev(void) { u32 rev = 0; /* * Retrieve board ID:
* rev1.1: 1,1,1* rev1.2: 1,1,0* rev1.3: 1,0,1* rev1.4: 1,0,0
** gpio: 16 17 11* ==============* r1.1: 1+ 1 1* r1.2: 1 1 0* r1.3: 1 0 1* r1.4: 1 0 0** + note: r1.1 does not strap this pin properly so it needs to* be hacked or ignored.
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
/* set to 1 in order to get correct value on board rev1.1 */
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
- /* set to 1 in order to get correct value on board rev 1.1 */
- gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
- gpio_direction_input(IMX_GPIO_NR(3, 11));
- gpio_direction_input(IMX_GPIO_NR(3, 16));
- gpio_direction_input(IMX_GPIO_NR(3, 17));
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
return (~rev & 0x7) + 1;
}
-inline u32 get_efikasb_rev(void) +static iomux_v3_cfg_t efikasb_revision_pads[] = {
- MX51_PAD_EIM_CS3__GPIO2_28,
- MX51_PAD_EIM_CS4__GPIO2_29,
+};
+static inline u32 get_sb_rev(void) { u32 rev = 0;
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
- imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, ARRAY_SIZE(efikasb_revision_pads));
- gpio_direction_input(IMX_GPIO_NR(2, 28));
- gpio_direction_input(IMX_GPIO_NR(2, 29));
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
return rev;
}
-inline uint32_t get_efika_rev(void) +inline uint32_t get_efikamx_rev(void) {
- if (machine_is_efikamx())
return get_efikamx_rev();- else
return get_efikasb_rev();
- if (machine_is_efikamx()) {
return get_mx_rev();- } else if (machine_is_efikasb()) {
return get_sb_rev();- }
}
u32 get_board_rev(void) {
- return get_cpu_rev() | (get_efika_rev() << 8);
- return get_cpu_rev() | (get_efikamx_rev() << 8);
}
/* @@ -137,66 +128,35 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0;
}
/*
- UART configuration
*/ -static void setup_iomux_uart(void) -{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-} +static iomux_v3_cfg_t efikamx_uart_pads[] = {
- MX51_PAD_UART1_RXD__UART1_RXD,
- MX51_PAD_UART1_TXD__UART1_TXD,
- MX51_PAD_UART1_RTS__UART1_RTS,
- MX51_PAD_UART1_CTS__UART1_CTS,
+};
/*
- SPI configuration
*/ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- /* Configure SS0 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
- /* Configure SS1 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);-} -#else -static inline void setup_iomux_spi(void) { } -#endif +static iomux_v3_cfg_t efikamx_spi_pads[]= {
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
- MX51_PAD_CSPI1_SS0__GPIO4_24,
- MX51_PAD_CSPI1_SS1__GPIO4_25,
- MX51_PAD_GPIO1_6__GPIO1_6,
+};
+#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24) +#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25) +#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
/*
- PMIC configuration
@@ -226,7 +186,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
@@ -301,29 +261,64 @@ static inline void power_init(void) { }
- MMC configuration
*/ #ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, };
-static inline uint32_t efika_mmc_cd(void) +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- MX51_PAD_GPIO1_1__SD1_WP,
+};
+#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1,1)
+static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
- MX51_PAD_GPIO1_0__SD1_CD,
- MX51_PAD_EIM_CS2__SD1_CD,
+};
+#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1,0) +#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2,27)
+static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
- MX51_PAD_SD2_CMD__SD2_CMD,
- MX51_PAD_SD2_CLK__SD2_CLK,
- MX51_PAD_SD2_DATA0__SD2_DATA0,
- MX51_PAD_SD2_DATA1__SD2_DATA1,
- MX51_PAD_SD2_DATA2__SD2_DATA2,
- MX51_PAD_SD2_DATA3__SD2_DATA3,
- MX51_PAD_GPIO1_7__SD2_WP,
- MX51_PAD_GPIO1_8__SD2_CD,
+};
+#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1,8) +#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1,7)
+static inline uint32_t efikamx_mmc_getcd(u32 base) {
- if (machine_is_efikamx())
return MX51_PIN_GPIO1_0;- else
return MX51_PIN_EIM_CS2;
- if (base == MMC_SDHC1_BASE_ADDR) {
if (machine_is_efikamx()) {return EFIKAMX_SDHC1_CD;} else {return EFIKASB_SDHC1_CD;}- } else {
return EFIKASB_SDHC2_CD;- }
}
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- uint32_t cd = efika_mmc_cd();
- int ret;
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IOMUX_TO_GPIO(cd));- else
ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
int ret = !gpio_get_value(cd);
return ret;
} @@ -331,139 +326,35 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int ret;
- uint32_t cd = efika_mmc_cd();
- /* SDHC1 is used on all revisions, setup control pins first */
- mxc_request_iomux(cd,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(cd,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);- mxc_request_iomux(MX51_PIN_GPIO1_1,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_SRE_FAST);- gpio_direction_input(IOMUX_TO_GPIO(cd));
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
- /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
- if (machine_is_efikasb() || (machine_is_efikamx() &&
(get_efika_rev() < EFIKAMX_BOARD_REV_12))) {/* SDHC1 IOMUX */mxc_request_iomux(MX51_PIN_SD1_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CMD,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CLK,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);/* SDHC2 IOMUX */mxc_request_iomux(MX51_PIN_SD2_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD2_CMD,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD2_CLK,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);/* SDHC2 Control lines IOMUX */mxc_request_iomux(MX51_PIN_GPIO1_7,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_GPIO1_7,PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_GPIO1_8,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_GPIO1_8,PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_SRE_FAST);gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
- /*
* All Efika MX boards use eSDHC1 with a common write-protect GPIO*/- imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, ARRAY_SIZE(efikamx_sdhc1_pads));
- gpio_direction_input(EFIKAMX_SDHC1_WP);
- /*
* Smartbook and Smarttop differ on the location of eSDHC1 carrier-detect GPIO*/- if (machine_is_efikamx()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);gpio_direction_input(EFIKAMX_SDHC1_CD);- } else if (machine_is_efikasb()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);gpio_direction_input(EFIKASB_SDHC1_CD);- }
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
- /*
* Smartbook (any) and Smarttop (1.0, 1.1) use a second SD controller*/- if (machine_is_efikasb() || (get_efikamx_rev() < EFIKAMX_BOARD_REV_12)) {
imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, ARRAY_SIZE(efikasb_sdhc2_pads));gpio_direction_input(EFIKASB_SDHC2_CD);gpio_direction_input(EFIKASB_SDHC2_WP);
} else { /* New boards use only SDHC1 */
/* SDHC1 IOMUX */mxc_request_iomux(MX51_PIN_SD1_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CMD,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CLK,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);}
return ret;
@@ -471,137 +362,100 @@ int board_mmc_init(bd_t *bis) #endif
/*
- ATA
*/
- PATA
-#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{
- mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
-} -#else -static inline void setup_iomux_ata(void) { } -#endif +static iomux_v3_cfg_t efikamx_pata_pads[] = {
- MX51_PAD_NANDF_WE_B__PATA_DIOW,
- MX51_PAD_NANDF_RE_B__PATA_DIOR,
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
- MX51_PAD_NANDF_CLE__PATA_RESET_B,
- MX51_PAD_NANDF_WP_B__PATA_DMACK,
- MX51_PAD_NANDF_RB0__PATA_DMARQ,
- MX51_PAD_NANDF_RB1__PATA_IORDY,
- MX51_PAD_GPIO_NAND__PATA_INTRQ,
- MX51_PAD_NANDF_CS2__PATA_CS_0,
- MX51_PAD_NANDF_CS3__PATA_CS_1,
- MX51_PAD_NANDF_CS4__PATA_DA_0,
- MX51_PAD_NANDF_CS5__PATA_DA_1,
- MX51_PAD_NANDF_CS6__PATA_DA_2,
- MX51_PAD_NANDF_D15__PATA_DATA15,
- MX51_PAD_NANDF_D14__PATA_DATA14,
- MX51_PAD_NANDF_D13__PATA_DATA13,
- MX51_PAD_NANDF_D12__PATA_DATA12,
- MX51_PAD_NANDF_D11__PATA_DATA11,
- MX51_PAD_NANDF_D10__PATA_DATA10,
- MX51_PAD_NANDF_D9__PATA_DATA9,
- MX51_PAD_NANDF_D8__PATA_DATA8,
- MX51_PAD_NANDF_D7__PATA_DATA7,
- MX51_PAD_NANDF_D6__PATA_DATA6,
- MX51_PAD_NANDF_D5__PATA_DATA5,
- MX51_PAD_NANDF_D4__PATA_DATA4,
- MX51_PAD_NANDF_D3__PATA_DATA3,
- MX51_PAD_NANDF_D2__PATA_DATA2,
- MX51_PAD_NANDF_D1__PATA_DATA1,
- MX51_PAD_NANDF_D0__PATA_DATA0,
+};
/*
- EHCI USB
*/ #ifdef CONFIG_CMD_USB -extern void setup_iomux_usb(void); +extern void efikamx_usb_setup_pads(void); #else -static inline void setup_iomux_usb(void) { } +static inline void efikamx_usb_setup_pads(void) { } #endif
/*
- LED configuration
- Smarttop LED pad config is done in the DCD
*/
-void setup_iomux_led(void) -{
- if (machine_is_efikamx()) {
/* Blue LED */mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);+#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13) +#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14) +#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
/* Green LED */mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);/* Red LED */mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);- } else {
/* CAPS-LOCK LED */mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);/* ALARM-LED LED */mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);- }
-} +static iomux_v3_cfg_t efikasb_led_pads[] = {
- MX51_PAD_GPIO1_3__GPIO1_3,
- MX51_PAD_EIM_CS0__GPIO2_25,
+};
-void efikamx_toggle_led(uint32_t mask) -{
- if (machine_is_efikamx()) {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),mask & EFIKAMX_LED_BLUE);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),mask & EFIKAMX_LED_GREEN);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),mask & EFIKAMX_LED_RED);- } else {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),mask & EFIKAMX_LED_BLUE);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),!(mask & EFIKAMX_LED_GREEN));- }
-} +#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25) +#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
/*
- Board initialization
*/ int board_early_init_f(void) {
- setup_iomux_uart();
- setup_iomux_spi();
- setup_iomux_led();
if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, ARRAY_SIZE(efikasb_led_pads));gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);gpio_direction_output(EFIKASB_MESSAGE_LED, 1);} else if (machine_is_efikamx()) {
/** Set up GPIO directions for LEDs.* IOMUX has been done in the DCD already.* Turn the red LED on for pre-relocation code.*/gpio_direction_output(EFIKAMX_LED_BLUE, 0);gpio_direction_output(EFIKAMX_LED_GREEN, 0);gpio_direction_output(EFIKAMX_LED_RED, 1);}
/*
* Both these pad configurations for UART and SPI are kind of redundant* since they are the Power-On Defaults for the i.MX51. But, it seems we* should make absolutely sure that they are set up correctly.*/imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, ARRAY_SIZE(efikamx_uart_pads));
imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, ARRAY_SIZE(efikamx_spi_pads));
/* not technically required for U-Boot operation but set it up anyway. */
gpio_direction_input(EFIKAMX_PMIC_IRQ);
/* Deselect both CS for now.. any other way and NOR doesn't probe properly. */
gpio_direction_output(EFIKAMX_SPI_SS0, 0);
gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0;
} @@ -615,43 +469,36 @@ int board_init(void)
int board_late_init(void) {
- setup_iomux_spi();
if (machine_is_efikamx()) {
/** Set up Blue LED for "In U-Boot" status.* We're all relocated and ready to U-Boot!*/gpio_set_value(EFIKAMX_LED_RED, 0);gpio_set_value(EFIKAMX_LED_GREEN, 0);gpio_set_value(EFIKAMX_LED_BLUE, 1);}
power_init();
- setup_iomux_led();
- setup_iomux_ata();
- setup_iomux_usb();
imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, ARRAY_SIZE(efikamx_pata_pads));
efikamx_usb_setup_pads();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
- setup_iomux_led();
- efikamx_toggle_led(EFIKAMX_LED_BLUE);
- return 0;
}
int checkboard(void) {
- u32 rev = get_efika_rev();
u32 rev = get_efikamx_rev();
printf("Board: Genesi Efika MX "); if (machine_is_efikamx()) {
printf("Board: Efika MX, rev1.%i\n", rev & 0xf);return 0;- } else {
switch (rev) {case EFIKASB_BOARD_REV_13:printf("Board: Efika SB rev1.3\n");break;case EFIKASB_BOARD_REV_20:printf("Board: Efika SB rev2.0\n");break;default:printf("Board: Efika SB, rev Unknown\n");break;}
printf("Smarttop (1.%i)\n", rev & 0xf);} else if (machine_is_efikasb()) {
printf("Smartbook\n");}
return 0;
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 22/08/2012 21:25, Matt Sealey wrote:
This is a rework of a previously submitted patchset and bundles the main board support and USB support into a single commit.
It requires the patch "mx5: add iomux-mx51.h include"
- Use iomux-mx51.h include to simplify board configuration.
- Simplify LED support (remove efikamx_toggle_led, change lit LEDs).
- Simplify MMC support for CD and WP pin differences.
- Fix broken CPU voltage setting - comment said 1.1V but the code set to 1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and all available Linux kernels would drop the voltage to 1.1V anyway and work reliably. This should lower power consumption during the boot process.
- Function renames for readability.
- Some board identification string changes to match actual product names.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
checkpatch reports several errors on this patch. Can you fix and resubmit (only this patch, I can apply the frst 3 patches) ?
Regards, Stefano
This is a rework of a previously submitted patchset and bundles the main board support and USB support into a single commit.
It requires the patch "mx5: add iomux-mx51.h include"
* Use iomux-mx51.h include to simplify board configuration. * Simplify LED support (remove efikamx_toggle_led, change lit LEDs). * Simplify MMC support for CD and WP pin differences. * Fix broken CPU voltage setting - comment said 1.1V but the code set to 1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and all available Linux kernels would drop the voltage to 1.1V anyway and work reliably. This should lower power consumption during the boot process. * Function renames for readability. * Some board identification string changes to match actual product names. * Passes checkpatch (v2)
Signed-off-by: Matt Sealey matt@genesi-usa.com Cc: Stefano Babic sbabic@denx.de --- board/genesi/mx51_efikamx/efikamx.c | 604 +++++++++++++---------------------- 1 file changed, 229 insertions(+), 375 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 12371c9..18ab8d9 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -1,7 +1,7 @@ /* + * Copyright (C) 2009 Freescale Semiconductor, Inc. * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2012 Genesi USA, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -24,9 +24,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> @@ -48,16 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif
/* - * Shared variables / local defines + * Board revisions + * + * Note that we get these revisions here for convenience, but we only set + * up for the production model Smarttop (1.3) and Smartbook (2.0). + * */ -/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4 - -void efikamx_toggle_led(uint32_t mask); - -/* Board revisions */ #define EFIKAMX_BOARD_REV_11 0x1 #define EFIKAMX_BOARD_REV_12 0x2 #define EFIKAMX_BOARD_REV_13 0x3 @@ -69,66 +63,67 @@ void efikamx_toggle_led(uint32_t mask); /* * Board identification */ -u32 get_efikamx_rev(void) +static u32 get_mx_rev(void) { u32 rev = 0; /* * Retrieve board ID: - * rev1.1: 1,1,1 - * rev1.2: 1,1,0 - * rev1.3: 1,0,1 - * rev1.4: 1,0,0 + * + * gpio: 16 17 11 + * ============== + * r1.1: 1+ 1 1 + * r1.2: 1 1 0 + * r1.3: 1 0 1 + * r1.4: 1 0 0 + * + * + note: r1.1 does not strap this pin properly so it needs to + * be hacked or ignored. */ - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - /* set to 1 in order to get correct value on board rev1.1 */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; + /* set to 1 in order to get correct value on board rev 1.1 */ + gpio_direction_output(GPIO_NUMBER(3, 16), 1); + gpio_direction_input(GPIO_NUMBER(3, 11)); + gpio_direction_input(GPIO_NUMBER(3, 16)); + gpio_direction_input(GPIO_NUMBER(3, 17));
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; - - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; + rev |= (!!gpio_get_value(GPIO_NUMBER(3, 16))) << 0; + rev |= (!!gpio_get_value(GPIO_NUMBER(3, 17))) << 1; + rev |= (!!gpio_get_value(GPIO_NUMBER(3, 11))) << 2;
return (~rev & 0x7) + 1; }
-inline u32 get_efikasb_rev(void) +static iomux_v3_cfg_t efikasb_revision_pads[] = { + MX51_PAD_EIM_CS3__GPIO2_28, + MX51_PAD_EIM_CS4__GPIO2_29, +}; + +static inline u32 get_sb_rev(void) { u32 rev = 0;
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; + imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, + ARRAY_SIZE(efikasb_revision_pads)); + gpio_direction_input(GPIO_NUMBER(2, 28)); + gpio_direction_input(GPIO_NUMBER(2, 29));
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; + rev |= (!!gpio_get_value(GPIO_NUMBER(2, 28))) << 0; + rev |= (!!gpio_get_value(GPIO_NUMBER(2, 29))) << 1;
return rev; }
-inline uint32_t get_efika_rev(void) +inline uint32_t get_efikamx_rev(void) { if (machine_is_efikamx()) - return get_efikamx_rev(); - else - return get_efikasb_rev(); + return get_mx_rev(); + else if (machine_is_efikasb()) + return get_sb_rev(); }
u32 get_board_rev(void) { - return get_cpu_rev() | (get_efika_rev() << 8); + return get_cpu_rev() | (get_efikamx_rev() << 8); }
/* @@ -138,65 +133,35 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); + PHYS_SDRAM_1_SIZE); return 0; }
/* * UART configuration */ -static void setup_iomux_uart(void) -{ - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; - - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); -} +static iomux_v3_cfg_t efikamx_uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +};
/* * SPI configuration */ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{ - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* Configure SS0 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); - - /* Configure SS1 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} -#else -static inline void setup_iomux_spi(void) { } -#endif +static iomux_v3_cfg_t efikamx_spi_pads[] = { + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_GPIO1_6__GPIO1_6, +}; + +#define EFIKAMX_SPI_SS0 GPIO_NUMBER(4, 24) +#define EFIKAMX_SPI_SS1 GPIO_NUMBER(4, 25) +#define EFIKAMX_PMIC_IRQ GPIO_NUMBER(1, 6)
/* * PMIC configuration @@ -226,7 +191,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */ @@ -301,29 +266,62 @@ static inline void power_init(void) { } * MMC configuration */ #ifdef CONFIG_FSL_ESDHC + struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, };
-static inline uint32_t efika_mmc_cd(void) +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = { + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_1__SD1_WP, +}; + +#define EFIKAMX_SDHC1_WP GPIO_NUMBER(1, 1) + +static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = { + MX51_PAD_GPIO1_0__SD1_CD, + MX51_PAD_EIM_CS2__SD1_CD, +}; + +#define EFIKAMX_SDHC1_CD GPIO_NUMBER(1, 0) +#define EFIKASB_SDHC1_CD GPIO_NUMBER(2, 27) + +static iomux_v3_cfg_t efikasb_sdhc2_pads[] = { + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_7__SD2_WP, + MX51_PAD_GPIO1_8__SD2_CD, +}; + +#define EFIKASB_SDHC2_CD GPIO_NUMBER(1, 8) +#define EFIKASB_SDHC2_WP GPIO_NUMBER(1, 7) + +static inline uint32_t efikamx_mmc_getcd(u32 base) { - if (machine_is_efikamx()) - return MX51_PIN_GPIO1_0; + if (base == MMC_SDHC1_BASE_ADDR) + if (machine_is_efikamx()) + return EFIKAMX_SDHC1_CD; + else + return EFIKASB_SDHC1_CD; else - return MX51_PIN_EIM_CS2; + return EFIKASB_SDHC2_CD; }
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - uint32_t cd = efika_mmc_cd(); - int ret; - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); - else - ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base); + int ret = !gpio_get_value(cd);
return ret; } @@ -331,139 +329,36 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int ret; - uint32_t cd = efika_mmc_cd(); - - /* SDHC1 is used on all revisions, setup control pins first */ - mxc_request_iomux(cd, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(cd, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(cd)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); - - /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ - if (machine_is_efikasb() || (machine_is_efikamx() && - (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 IOMUX */ - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 Control lines IOMUX */ - mxc_request_iomux(MX51_PIN_GPIO1_7, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_8, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_8, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + /* + * All Efika MX boards use eSDHC1 with a common write-protect GPIO + */ + imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, + ARRAY_SIZE(efikamx_sdhc1_pads)); + gpio_direction_input(EFIKAMX_SDHC1_WP); + + /* + * Smartbook and Smarttop differ on the location of eSDHC1 + * carrier-detect GPIO + */ + if (machine_is_efikamx()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]); + gpio_direction_input(EFIKAMX_SDHC1_CD); + } else if (machine_is_efikasb()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]); + gpio_direction_input(EFIKASB_SDHC1_CD); + } + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + if (machine_is_efikasb()) { + + imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, + ARRAY_SIZE(efikasb_sdhc2_pads)); + gpio_direction_input(EFIKASB_SDHC2_CD); + gpio_direction_input(EFIKASB_SDHC2_WP); if (!ret) ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); - } else { /* New boards use only SDHC1 */ - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); }
return ret; @@ -471,74 +366,39 @@ int board_mmc_init(bd_t *bis) #endif
/* - * ATA + * PATA */ -#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{ - mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); -} -#else -static inline void setup_iomux_ata(void) { } -#endif +static iomux_v3_cfg_t efikamx_pata_pads[] = { + MX51_PAD_NANDF_WE_B__PATA_DIOW, + MX51_PAD_NANDF_RE_B__PATA_DIOR, + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, + MX51_PAD_NANDF_CLE__PATA_RESET_B, + MX51_PAD_NANDF_WP_B__PATA_DMACK, + MX51_PAD_NANDF_RB0__PATA_DMARQ, + MX51_PAD_NANDF_RB1__PATA_IORDY, + MX51_PAD_GPIO_NAND__PATA_INTRQ, + MX51_PAD_NANDF_CS2__PATA_CS_0, + MX51_PAD_NANDF_CS3__PATA_CS_1, + MX51_PAD_NANDF_CS4__PATA_DA_0, + MX51_PAD_NANDF_CS5__PATA_DA_1, + MX51_PAD_NANDF_CS6__PATA_DA_2, + MX51_PAD_NANDF_D15__PATA_DATA15, + MX51_PAD_NANDF_D14__PATA_DATA14, + MX51_PAD_NANDF_D13__PATA_DATA13, + MX51_PAD_NANDF_D12__PATA_DATA12, + MX51_PAD_NANDF_D11__PATA_DATA11, + MX51_PAD_NANDF_D10__PATA_DATA10, + MX51_PAD_NANDF_D9__PATA_DATA9, + MX51_PAD_NANDF_D8__PATA_DATA8, + MX51_PAD_NANDF_D7__PATA_DATA7, + MX51_PAD_NANDF_D6__PATA_DATA6, + MX51_PAD_NANDF_D5__PATA_DATA5, + MX51_PAD_NANDF_D4__PATA_DATA4, + MX51_PAD_NANDF_D3__PATA_DATA3, + MX51_PAD_NANDF_D2__PATA_DATA2, + MX51_PAD_NANDF_D1__PATA_DATA1, + MX51_PAD_NANDF_D0__PATA_DATA0, +};
/* * EHCI USB @@ -551,57 +411,58 @@ static inline void setup_iomux_usb(void) { }
/* * LED configuration + * + * Smarttop LED pad config is done in the DCD + * */ -void setup_iomux_led(void) -{ - if (machine_is_efikamx()) { - /* Blue LED */ - mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); - - /* Green LED */ - mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); - - /* Red LED */ - mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); - } else { - /* CAPS-LOCK LED */ - mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); - - /* ALARM-LED LED */ - mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); - } -} +#define EFIKAMX_LED_BLUE GPIO_NUMBER(3, 13) +#define EFIKAMX_LED_GREEN GPIO_NUMBER(3, 14) +#define EFIKAMX_LED_RED GPIO_NUMBER(3, 15)
-void efikamx_toggle_led(uint32_t mask) -{ - if (machine_is_efikamx()) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - mask & EFIKAMX_LED_GREEN); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - mask & EFIKAMX_LED_RED); - } else { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), - !(mask & EFIKAMX_LED_GREEN)); - } -} +static iomux_v3_cfg_t efikasb_led_pads[] = { + MX51_PAD_GPIO1_3__GPIO1_3, + MX51_PAD_EIM_CS0__GPIO2_25, +}; + +#define EFIKASB_CAPSLOCK_LED GPIO_NUMBER(2, 25) +#define EFIKASB_MESSAGE_LED GPIO_NUMBER(1, 3) /* Note: active low */
/* * Board initialization */ int board_early_init_f(void) { - setup_iomux_uart(); - setup_iomux_spi(); - setup_iomux_led(); + if (machine_is_efikasb()) { + imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, + ARRAY_SIZE(efikasb_led_pads)); + gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0); + gpio_direction_output(EFIKASB_MESSAGE_LED, 1); + } else if (machine_is_efikamx()) { + /* + * Set up GPIO directions for LEDs. + * IOMUX has been done in the DCD already. + * Turn the red LED on for pre-relocation code. + */ + gpio_direction_output(EFIKAMX_LED_BLUE, 0); + gpio_direction_output(EFIKAMX_LED_GREEN, 0); + gpio_direction_output(EFIKAMX_LED_RED, 1); + } + + /* + * Both these pad configurations for UART and SPI are kind of redundant + * since they are the Power-On Defaults for the i.MX51. But, it seems we + * should make absolutely sure that they are set up correctly. + */ + imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, + ARRAY_SIZE(efikamx_uart_pads)); + imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, + ARRAY_SIZE(efikamx_spi_pads)); + + /* not technically required for U-Boot operation but do it anyway. */ + gpio_direction_input(EFIKAMX_PMIC_IRQ); + /* Deselect both CS for now, otherwise NOR doesn't probe properly. */ + gpio_direction_output(EFIKAMX_SPI_SS0, 0); + gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0; } @@ -615,44 +476,37 @@ int board_init(void)
int board_late_init(void) { - setup_iomux_spi(); + if (machine_is_efikamx()) { + /* + * Set up Blue LED for "In U-Boot" status. + * We're all relocated and ready to U-Boot! + */ + gpio_set_value(EFIKAMX_LED_RED, 0); + gpio_set_value(EFIKAMX_LED_GREEN, 0); + gpio_set_value(EFIKAMX_LED_BLUE, 1); + }
power_init();
- setup_iomux_led(); - setup_iomux_ata(); + imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, + ARRAY_SIZE(efikamx_pata_pads)); setup_iomux_usb();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
- setup_iomux_led(); - - efikamx_toggle_led(EFIKAMX_LED_BLUE); - return 0; }
int checkboard(void) { - u32 rev = get_efika_rev(); + u32 rev = get_efikamx_rev();
- if (machine_is_efikamx()) { - printf("Board: Efika MX, rev1.%i\n", rev & 0xf); - return 0; - } else { - switch (rev) { - case EFIKASB_BOARD_REV_13: - printf("Board: Efika SB rev1.3\n"); - break; - case EFIKASB_BOARD_REV_20: - printf("Board: Efika SB rev2.0\n"); - break; - default: - printf("Board: Efika SB, rev Unknown\n"); - break; - } - } + printf("Board: Genesi Efika MX "); + if (machine_is_efikamx()) + printf("Smarttop (1.%i)\n", rev & 0xf); + else if (machine_is_efikasb()) + printf("Smartbook\n");
return 0; }
On 27/08/2012 17:58, Matt Sealey wrote:
This is a rework of a previously submitted patchset and bundles the main board support and USB support into a single commit.
It requires the patch "mx5: add iomux-mx51.h include"
- Use iomux-mx51.h include to simplify board configuration.
- Simplify LED support (remove efikamx_toggle_led, change lit LEDs).
- Simplify MMC support for CD and WP pin differences.
- Fix broken CPU voltage setting - comment said 1.1V but the code set to 1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and all available Linux kernels would drop the voltage to 1.1V anyway and work reliably. This should lower power consumption during the boot process.
- Function renames for readability.
- Some board identification string changes to match actual product names.
- Passes checkpatch (v2)
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
On 22/08/2012 21:25, Matt Sealey wrote:
- Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory
- Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/{efikamx => genesi/mx51_efikamx}/Makefile | 0 .../{efikamx => genesi/mx51_efikamx}/efikamx-usb.c | 2 +- board/{efikamx => genesi/mx51_efikamx}/efikamx.c | 0 .../mx51_efikamx}/imximage_mx.cfg | 0 .../mx51_efikamx}/imximage_sb.cfg | 0 boards.cfg | 4 ++-- include/configs/{efikamx.h => mx51_efikamx.h} | 0 7 files changed, 3 insertions(+), 3 deletions(-) rename board/{efikamx => genesi/mx51_efikamx}/Makefile (100%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx-usb.c (99%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx.c (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_mx.cfg (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_sb.cfg (100%) rename include/configs/{efikamx.h => mx51_efikamx.h} (100%)
diff --git a/board/efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile similarity index 100% rename from board/efikamx/Makefile rename to board/genesi/mx51_efikamx/Makefile diff --git a/board/efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c similarity index 99% rename from board/efikamx/efikamx-usb.c rename to board/genesi/mx51_efikamx/efikamx-usb.c index 618b39d..e9273d0 100644 --- a/board/efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -33,7 +33,7 @@ #include <usb/ulpi.h> #include <errno.h>
-#include "../../drivers/usb/host/ehci.h" +#include "../../../drivers/usb/host/ehci.h"
/* USB pin configuration */ #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ diff --git a/board/efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c similarity index 100% rename from board/efikamx/efikamx.c rename to board/genesi/mx51_efikamx/efikamx.c diff --git a/board/efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg similarity index 100% rename from board/efikamx/imximage_mx.cfg rename to board/genesi/mx51_efikamx/imximage_mx.cfg diff --git a/board/efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg similarity index 100% rename from board/efikamx/imximage_sb.cfg rename to board/genesi/mx51_efikamx/imximage_sb.cfg diff --git a/boards.cfg b/boards.cfg index edd750c..a9ec44b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -215,8 +215,8 @@ integratorcp_cm946es arm arm946es integrator armltd ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx highbank arm armv7 highbank - highbank -efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg -efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg +mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg +mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg diff --git a/include/configs/efikamx.h b/include/configs/mx51_efikamx.h similarity index 100% rename from include/configs/efikamx.h rename to include/configs/mx51_efikamx.h
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 22/08/2012 21:25, Matt Sealey wrote:
- Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory
- Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/{efikamx => genesi/mx51_efikamx}/Makefile | 0 .../{efikamx => genesi/mx51_efikamx}/efikamx-usb.c | 2 +- board/{efikamx => genesi/mx51_efikamx}/efikamx.c | 0 .../mx51_efikamx}/imximage_mx.cfg | 0 .../mx51_efikamx}/imximage_sb.cfg | 0 boards.cfg | 4 ++-- include/configs/{efikamx.h => mx51_efikamx.h} | 0 7 files changed, 3 insertions(+), 3 deletions(-) rename board/{efikamx => genesi/mx51_efikamx}/Makefile (100%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx-usb.c (99%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx.c (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_mx.cfg (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_sb.cfg (100%) rename include/configs/{efikamx.h => mx51_efikamx.h} (100%)
diff --git a/board/efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile similarity index 100% rename from board/efikamx/Makefile rename to board/genesi/mx51_efikamx/Makefile diff --git a/board/efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c similarity index 99% rename from board/efikamx/efikamx-usb.c rename to board/genesi/mx51_efikamx/efikamx-usb.c index 618b39d..e9273d0 100644 --- a/board/efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -33,7 +33,7 @@ #include <usb/ulpi.h> #include <errno.h>
-#include "../../drivers/usb/host/ehci.h" +#include "../../../drivers/usb/host/ehci.h"
/* USB pin configuration */ #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ diff --git a/board/efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c similarity index 100% rename from board/efikamx/efikamx.c rename to board/genesi/mx51_efikamx/efikamx.c diff --git a/board/efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg similarity index 100% rename from board/efikamx/imximage_mx.cfg rename to board/genesi/mx51_efikamx/imximage_mx.cfg diff --git a/board/efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg similarity index 100% rename from board/efikamx/imximage_sb.cfg rename to board/genesi/mx51_efikamx/imximage_sb.cfg diff --git a/boards.cfg b/boards.cfg index edd750c..a9ec44b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -215,8 +215,8 @@ integratorcp_cm946es arm arm946es integrator armltd ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx highbank arm armv7 highbank - highbank -efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg -efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg +mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg +mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg diff --git a/include/configs/efikamx.h b/include/configs/mx51_efikamx.h similarity index 100% rename from include/configs/efikamx.h rename to include/configs/mx51_efikamx.h
It is fine with me.
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 22/08/2012 21:25, Matt Sealey wrote:
- Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory
- Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/{efikamx => genesi/mx51_efikamx}/Makefile | 0 .../{efikamx => genesi/mx51_efikamx}/efikamx-usb.c | 2 +- board/{efikamx => genesi/mx51_efikamx}/efikamx.c | 0 .../mx51_efikamx}/imximage_mx.cfg | 0 .../mx51_efikamx}/imximage_sb.cfg | 0 boards.cfg | 4 ++-- include/configs/{efikamx.h => mx51_efikamx.h} | 0 7 files changed, 3 insertions(+), 3 deletions(-) rename board/{efikamx => genesi/mx51_efikamx}/Makefile (100%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx-usb.c (99%) rename board/{efikamx => genesi/mx51_efikamx}/efikamx.c (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_mx.cfg (100%) rename board/{efikamx => genesi/mx51_efikamx}/imximage_sb.cfg (100%) rename include/configs/{efikamx.h => mx51_efikamx.h} (100%)
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
participants (2)
-
Matt Sealey -
Stefano Babic