[U-Boot] [PATCH 1/2] imx: timer: don't clear the GPT control register multiple times
There is no need to clear the control register 100 times in a loop, a single zero write clears the register. I didn't find any justification why clearing this register in a loop is needed (no info in i.MX6 errata or GPT timer linux driver, linux driver uses single write to clear this control register).
Signed-off-by: Anatolij Gustschin agust@denx.de --- arch/arm/mach-imx/timer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index 9b01114..69dbf3c 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -74,8 +74,7 @@ int timer_init(void) __raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */ - for (i = 0; i < 100; i++) - __raw_writel(0, &cur_gpt->control); + __raw_writel(0, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control); i &= ~GPTCR_CLKSOURCE_MASK;
The GPT timer was already initialised in board_init_f() as it is needed in dram init. Do not repeat timer init in board_init_r().
Signed-off-by: Anatolij Gustschin agust@denx.de --- common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c index d245cfc..8b219ba 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -379,7 +379,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (spl_init()) hang(); } -#ifndef CONFIG_PPC +#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6) /* * timer_init() does not exist on PPC systems. The timer is initialized * and enabled (decrementer) in interrupt_init() here.
On 28/08/2017 17:46, Anatolij Gustschin wrote:
The GPT timer was already initialised in board_init_f() as it is needed in dram init. Do not repeat timer init in board_init_r().
Signed-off-by: Anatolij Gustschin agust@denx.de
common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c index d245cfc..8b219ba 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -379,7 +379,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (spl_init()) hang(); } -#ifndef CONFIG_PPC +#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6) /* * timer_init() does not exist on PPC systems. The timer is initialized * and enabled (decrementer) in interrupt_init() here.
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 28/08/2017 17:46, Anatolij Gustschin wrote:
The GPT timer was already initialised in board_init_f() as it is needed in dram init. Do not repeat timer init in board_init_r().
Signed-off-by: Anatolij Gustschin agust@denx.de
common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c index d245cfc..8b219ba 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -379,7 +379,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (spl_init()) hang(); } -#ifndef CONFIG_PPC +#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6) /* * timer_init() does not exist on PPC systems. The timer is initialized * and enabled (decrementer) in interrupt_init() here.
Applied to u-boot-imx, -master, thanks !
Best regards, Stefano Babic
On 28/08/2017 17:46, Anatolij Gustschin wrote:
There is no need to clear the control register 100 times in a loop, a single zero write clears the register. I didn't find any justification why clearing this register in a loop is needed (no info in i.MX6 errata or GPT timer linux driver, linux driver uses single write to clear this control register).
Agree, no idea why.
Signed-off-by: Anatolij Gustschin agust@denx.de
arch/arm/mach-imx/timer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index 9b01114..69dbf3c 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -74,8 +74,7 @@ int timer_init(void) __raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */
- for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
__raw_writel(0, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control); i &= ~GPTCR_CLKSOURCE_MASK;
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 28/08/2017 17:46, Anatolij Gustschin wrote:
There is no need to clear the control register 100 times in a loop, a single zero write clears the register. I didn't find any justification why clearing this register in a loop is needed (no info in i.MX6 errata or GPT timer linux driver, linux driver uses single write to clear this control register).
Signed-off-by: Anatolij Gustschin agust@denx.de
arch/arm/mach-imx/timer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index 9b01114..69dbf3c 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -74,8 +74,7 @@ int timer_init(void) __raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */
- for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
__raw_writel(0, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control); i &= ~GPTCR_CLKSOURCE_MASK;
Applied to u-boot-imx, -master, thanks !
Best regards, Stefano Babic
participants (2)
-
Anatolij Gustschin -
Stefano Babic