[U-Boot] [PATCH] openrisc/cache: disable icache during invalidation

invalidating the memory area that is being executed while icache is on is a bit adventurous, make sure it's turned off during this operation
Signed-off-by: Stefan Kristiansson stefan.kristiansson@saunalahti.fi --- arch/openrisc/cpu/cache.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c index 2a73a4f..fedfd89 100644 --- a/arch/openrisc/cpu/cache.c +++ b/arch/openrisc/cpu/cache.c @@ -44,11 +44,15 @@ void invalidate_dcache_range(unsigned long addr, unsigned long stop) static void invalidate_icache_range(unsigned long addr, unsigned long stop) { ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16; + ulong ie = icache_status();
+ icache_disable(); while (addr < stop) { mtspr(SPR_ICBIR, addr); addr += block_size; } + if (ie) + icache_enable(); }
void flush_cache(unsigned long addr, unsigned long size)

On Tuesday 24 April 2012 01:34:31 Stefan Kristiansson wrote:
invalidating the memory area that is being executed while icache is on is a bit adventurous, make sure it's turned off during this operation
sounds like a bug in the chip. you should be able to icache invalidate the active insn all you like. -mike
participants (2)
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Mike Frysinger
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Stefan Kristiansson