Signed-off-by: Angelo Dureghello angelo@sysam.it --- drivers/mmc/fsl_esdhc.c | 21 ++++++++++++++++----- include/fsl_esdhc.h | 1 + 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345c67..e376926c53 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -26,6 +26,12 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_MCF5441x +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO +#define CONFIG_SYS_FSL_ESDHC_USE_PIO +#endif +#endif + #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ IRQSTATEN_CINT | \ IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ @@ -399,7 +405,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) return 0; #endif - esdhc_write32(&regs->irqstat, -1);

sync(); @@ -987,8 +992,12 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

+#ifdef CONFIG_MCF5441x + esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); +#else /* Put the PROCTL reg back to the default */ esdhc_write32(&regs->proctl, PROCTL_INIT); +#endif

/* Set timout to the maximum value */ esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); @@ -1014,7 +1023,6 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return dm_gpio_get_value(&priv->cd_gpio); #endif #endif - while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000);

@@ -1112,11 +1120,16 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);

writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); + +#ifdef CONFIG_MCF5441x + /* ColdFire, using SDHC_DATA[3] for card detection */ + esdhc_write32(&regs->proctl, esdhc_read32(&regs->proctl) | PROCTL_D3CD); +#endif + cfg = &plat->cfg; #ifndef CONFIG_DM_MMC memset(cfg, '\0', sizeof(*cfg)); #endif - voltage_caps = 0; caps = esdhc_read32(&regs->hostcapblt);

@@ -1129,7 +1142,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 caps = caps | ESDHC_HOSTCAPBLT_VS33; #endif - if (caps & ESDHC_HOSTCAPBLT_VS18) voltage_caps |= MMC_VDD_165_195; if (caps & ESDHC_HOSTCAPBLT_VS30) @@ -1150,7 +1162,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, printf("voltage not supported by controller\n"); return -1; } - if (priv->bus_width == 8) cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; else if (priv->bus_width == 4) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index acd8dd06f8..8dbd5249a7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -106,6 +106,7 @@ #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008

#define CMDARG 0x0002e008