[U-Boot-Users] [PATCH v2 0/5] mpc83xx: MPC8360E-RDK related patches
Hi all,
Here are few patches needed to support MPC8360E-RDK...
Thanks,
New device trees will use "fsl,qe" compatible properties.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- cpu/mpc83xx/fdt.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index f21c54e..909171f 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -52,6 +52,12 @@ void ft_cpu_setup(void *blob, bd_t *bd) "bus-frequency", gd->qe_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "brg-frequency", gd->brg_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe", + "clock-frequency", gd->qe_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe", + "bus-frequency", gd->qe_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe", + "brg-frequency", gd->brg_clk, 1); #endif
#ifdef CFG_NS16550
This is MPC8360E based board with: - 256MB fixed SDRAM; - 8MB Intel Strata NOR flash; - StMICRO 64MiB NAND flash; - two 10/100/1000 ethernet ports connected via Broadcom BCM5481 PHYs; - two 10/100 ethernet ports connected via National DP83848 PHYs; - one PCI and one miniPCI slots; - four serial ports (two NS16550-compatible, two UCCs); - four USB ports working through MPC8360E "FHCI" USB controller; - Fujitsu MB86277 graphics controller; - Analog to Digital Converter/Touchscreen controller, AD7843 connected to SPI.
Features not supported in this patch are: - StMICRO 64MiB NAND flash (patch sent); - MINT framebuffer initialization (patch is pending); - Fetching production information from the EEPROM via I2C; - FHCI USB; - Two slow UCCs used as RS-485 UARTs.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- MAINTAINERS | 4 + MAKEALL | 2 + Makefile | 11 + board/freescale/mpc8360erdk/Makefile | 50 +++ board/freescale/mpc8360erdk/config.mk | 28 ++ board/freescale/mpc8360erdk/mpc8360erdk.c | 340 ++++++++++++++++++ include/configs/MPC8360ERDK.h | 538 +++++++++++++++++++++++++++++ 7 files changed, 973 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mpc8360erdk/Makefile create mode 100644 board/freescale/mpc8360erdk/config.mk create mode 100644 board/freescale/mpc8360erdk/mpc8360erdk.c create mode 100644 include/configs/MPC8360ERDK.h
diff --git a/MAINTAINERS b/MAINTAINERS index 43b3b79..c64eb18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -366,6 +366,10 @@ David Updegraff dave@cray.com
CRAYL1 PPC4xx
+Anton Vorontsov avorontsov@ru.mvista.com + + MPC8360ERDK MPC8360 + Josef Wagner Wagner@Microsys.de
CPC45 MPC8245 diff --git a/MAKEALL b/MAKEALL index 47f3296..914431c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -313,6 +313,8 @@ LIST_83xx=" \ MPC8349ITXGP \ MPC8360EMDS \ MPC8360EMDS_ATM \ + MPC8360ERDK_33 \ + MPC8360ERDK_66 \ MPC837XEMDS \ sbc8349 \ TQM834x \ diff --git a/Makefile b/Makefile index dd995d3..0239293 100644 --- a/Makefile +++ b/Makefile @@ -1922,6 +1922,17 @@ MPC8360EMDS_ATM_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
+MPC8360ERDK_33_config \ +MPC8360ERDK_66_config \ +MPC8360ERDK_config: + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "... CLKIN 33MHz " ; \ + echo "#define CONFIG_CLKIN_33MHZ" >>$(obj)include/config.h ;\ + fi ; + @$(MKCONFIG) -a MPC8360ERDK ppc mpc83xx mpc8360erdk freescale + MPC837XEMDS_config \ MPC837XEMDS_HOST_config: unconfig @mkdir -p $(obj)include diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile new file mode 100644 index 0000000..acc9544 --- /dev/null +++ b/board/freescale/mpc8360erdk/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8360erdk/config.mk b/board/freescale/mpc8360erdk/config.mk new file mode 100644 index 0000000..87dd746 --- /dev/null +++ b/board/freescale/mpc8360erdk/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8360ERDK +# + +TEXT_BASE = 0xFF800000 diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c new file mode 100644 index 0000000..98ec6ab --- /dev/null +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <i2c.h> +#include <spd.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <pci.h> +#include <libfdt.h> + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* MDIO */ + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + /* UCC1 - UEC (Gigabit) */ + {0, 3, 1, 0, 1}, /* TxD0 */ + {0, 4, 1, 0, 1}, /* TxD1 */ + {0, 5, 1, 0, 1}, /* TxD2 */ + {0, 6, 1, 0, 1}, /* TxD3 */ + {0, 9, 2, 0, 1}, /* RxD0 */ + {0, 10, 2, 0, 1}, /* RxD1 */ + {0, 11, 2, 0, 1}, /* RxD2 */ + {0, 12, 2, 0, 1}, /* RxD3 */ + {0, 7, 1, 0, 1}, /* TX_EN */ + {0, 8, 1, 0, 1}, /* TX_ER */ + {0, 15, 2, 0, 1}, /* RX_DV */ + {0, 0, 2, 0, 1}, /* RX_CLK */ + {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + + /* UCC2 - UEC (Gigabit) */ + {0, 17, 1, 0, 1}, /* TxD0 */ + {0, 18, 1, 0, 1}, /* TxD1 */ + {0, 19, 1, 0, 1}, /* TxD2 */ + {0, 20, 1, 0, 1}, /* TxD3 */ + {0, 23, 2, 0, 1}, /* RxD0 */ + {0, 24, 2, 0, 1}, /* RxD1 */ + {0, 25, 2, 0, 1}, /* RxD2 */ + {0, 26, 2, 0, 1}, /* RxD3 */ + {0, 21, 1, 0, 1}, /* TX_EN */ + {0, 22, 1, 0, 1}, /* TX_ER */ + {0, 29, 2, 0, 1}, /* RX_DV */ + {0, 31, 2, 0, 1}, /* RX_CLK */ + {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */ + {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ + + /* UCC7 - UEC */ + {4, 0, 1, 0, 1}, /* TxD0 */ + {4, 1, 1, 0, 1}, /* TxD1 */ + {4, 2, 1, 0, 1}, /* TxD2 */ + {4, 3, 1, 0, 1}, /* TxD3 */ + {4, 6, 2, 0, 1}, /* RxD0 */ + {4, 7, 2, 0, 1}, /* RxD1 */ + {4, 8, 2, 0, 1}, /* RxD2 */ + {4, 9, 2, 0, 1}, /* RxD3 */ + {4, 4, 1, 0, 1}, /* TX_EN */ + {4, 5, 1, 0, 1}, /* TX_ER */ + {4, 12, 2, 0, 1}, /* RX_DV */ + {4, 13, 2, 0, 1}, /* RX_ER */ + {4, 10, 2, 0, 1}, /* COL */ + {4, 11, 2, 0, 1}, /* CRS */ + {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */ + {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */ + + /* UCC4 - UEC */ + {1, 14, 1, 0, 1}, /* TxD0 */ + {1, 15, 1, 0, 1}, /* TxD1 */ + {1, 16, 1, 0, 1}, /* TxD2 */ + {1, 17, 1, 0, 1}, /* TxD3 */ + {1, 20, 2, 0, 1}, /* RxD0 */ + {1, 21, 2, 0, 1}, /* RxD1 */ + {1, 22, 2, 0, 1}, /* RxD2 */ + {1, 23, 2, 0, 1}, /* RxD3 */ + {1, 18, 1, 0, 1}, /* TX_EN */ + {1, 19, 1, 0, 2}, /* TX_ER */ + {1, 26, 2, 0, 1}, /* RX_DV */ + {1, 27, 2, 0, 1}, /* RX_ER */ + {1, 24, 2, 0, 1}, /* COL */ + {1, 25, 2, 0, 1}, /* CRS */ + {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */ + {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */ + + /* PCI1 */ + {5, 4, 2, 0, 3}, /* PCI_M66EN */ + {5, 5, 1, 0, 3}, /* PCI_INTA */ + {5, 6, 1, 0, 3}, /* PCI_RSTO */ + {5, 7, 3, 0, 3}, /* PCI_C_BE0 */ + {5, 8, 3, 0, 3}, /* PCI_C_BE1 */ + {5, 9, 3, 0, 3}, /* PCI_C_BE2 */ + {5, 10, 3, 0, 3}, /* PCI_C_BE3 */ + {5, 11, 3, 0, 3}, /* PCI_PAR */ + {5, 12, 3, 0, 3}, /* PCI_FRAME */ + {5, 13, 3, 0, 3}, /* PCI_TRDY */ + {5, 14, 3, 0, 3}, /* PCI_IRDY */ + {5, 15, 3, 0, 3}, /* PCI_STOP */ + {5, 16, 3, 0, 3}, /* PCI_DEVSEL */ + {5, 17, 0, 0, 0}, /* PCI_IDSEL */ + {5, 18, 3, 0, 3}, /* PCI_SERR */ + {5, 19, 3, 0, 3}, /* PCI_PERR */ + {5, 20, 3, 0, 3}, /* PCI_REQ0 */ + {5, 21, 2, 0, 3}, /* PCI_REQ1 */ + {5, 22, 2, 0, 3}, /* PCI_GNT2 */ + {5, 23, 3, 0, 3}, /* PCI_GNT0 */ + {5, 24, 1, 0, 3}, /* PCI_GNT1 */ + {5, 25, 1, 0, 3}, /* PCI_GNT2 */ + {5, 26, 0, 0, 0}, /* PCI_CLK0 */ + {5, 27, 0, 0, 0}, /* PCI_CLK1 */ + {5, 28, 0, 0, 0}, /* PCI_CLK2 */ + {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */ + {6, 0, 3, 0, 3}, /* PCI_AD0 */ + {6, 1, 3, 0, 3}, /* PCI_AD1 */ + {6, 2, 3, 0, 3}, /* PCI_AD2 */ + {6, 3, 3, 0, 3}, /* PCI_AD3 */ + {6, 4, 3, 0, 3}, /* PCI_AD4 */ + {6, 5, 3, 0, 3}, /* PCI_AD5 */ + {6, 6, 3, 0, 3}, /* PCI_AD6 */ + {6, 7, 3, 0, 3}, /* PCI_AD7 */ + {6, 8, 3, 0, 3}, /* PCI_AD8 */ + {6, 9, 3, 0, 3}, /* PCI_AD9 */ + {6, 10, 3, 0, 3}, /* PCI_AD10 */ + {6, 11, 3, 0, 3}, /* PCI_AD11 */ + {6, 12, 3, 0, 3}, /* PCI_AD12 */ + {6, 13, 3, 0, 3}, /* PCI_AD13 */ + {6, 14, 3, 0, 3}, /* PCI_AD14 */ + {6, 15, 3, 0, 3}, /* PCI_AD15 */ + {6, 16, 3, 0, 3}, /* PCI_AD16 */ + {6, 17, 3, 0, 3}, /* PCI_AD17 */ + {6, 18, 3, 0, 3}, /* PCI_AD18 */ + {6, 19, 3, 0, 3}, /* PCI_AD19 */ + {6, 20, 3, 0, 3}, /* PCI_AD20 */ + {6, 21, 3, 0, 3}, /* PCI_AD21 */ + {6, 22, 3, 0, 3}, /* PCI_AD22 */ + {6, 23, 3, 0, 3}, /* PCI_AD23 */ + {6, 24, 3, 0, 3}, /* PCI_AD24 */ + {6, 25, 3, 0, 3}, /* PCI_AD25 */ + {6, 26, 3, 0, 3}, /* PCI_AD26 */ + {6, 27, 3, 0, 3}, /* PCI_AD27 */ + {6, 28, 3, 0, 3}, /* PCI_AD28 */ + {6, 29, 3, 0, 3}, /* PCI_AD29 */ + {6, 30, 3, 0, 3}, /* PCI_AD30 */ + {6, 31, 3, 0, 3}, /* PCI_AD31 */ + + /* NAND */ + {4, 18, 2, 0, 0}, /* NAND_RYnBY */ + + /* DUART - UART2 */ + {5, 0, 1, 0, 2}, /* UART2_SOUT */ + {5, 2, 1, 0, 1}, /* UART2_RTS */ + {5, 3, 2, 0, 2}, /* UART2_SIN */ + {5, 1, 2, 0, 3}, /* UART2_CTS */ + + /* UCC5 - UART3 */ + {3, 0, 1, 0, 1}, /* UART3_TX */ + {3, 4, 1, 0, 1}, /* UART3_RTS */ + {3, 6, 2, 0, 1}, /* UART3_RX */ + {3, 12, 2, 0, 0}, /* UART3_CTS */ + {3, 13, 2, 0, 0}, /* UCC5_CD */ + + /* UCC6 - UART4 */ + {3, 14, 1, 0, 1}, /* UART4_TX */ + {3, 18, 1, 0, 1}, /* UART4_RTS */ + {3, 20, 2, 0, 1}, /* UART4_RX */ + {3, 26, 2, 0, 0}, /* UART4_CTS */ + {3, 27, 2, 0, 0}, /* UCC6_CD */ + + /* Fujitsu MB86277 (MINT) graphics controller */ + {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */ + {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */ + {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ + {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ + + /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END}, +}; + +int board_early_init_f(void) +{ + return 0; +} + +int board_early_init_r(void) +{ + void *reg = (void *)(CFG_IMMR + 0x14a8); + u32 val; + + /* + * Because of errata in the UCCs, we have to write to the reserved + * registers to slow the clocks down. + */ + val = in_be32(reg); + /* UCC1 */ + val |= 0x00003000; + /* UCC2 */ + val |= 0x0c000000; + out_be32(reg, val); + + return 0; +} + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + udelay(200); + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +long int initdram(int board_type) +{ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + extern void ddr_enable_ecc(unsigned int dram_size); +#endif + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* + * Initialize DDR ECC byte + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +int checkboard(void) +{ + puts("Board: Freescale/Logic MPC8360ERDK\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + .bus_start = CFG_PCI1_MEM_BASE, + .phys_start = CFG_PCI1_MEM_PHYS, + .size = CFG_PCI1_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH, + }, + { + .bus_start = CFG_PCI1_MMIO_BASE, + .phys_start = CFG_PCI1_MMIO_PHYS, + .size = CFG_PCI1_MMIO_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CFG_PCI1_IO_BASE, + .phys_start = CFG_PCI1_IO_PHYS, + .size = CFG_PCI1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions, }; + +#if defined(PCI_33M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | + OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; + printf("PCI clock is 33MHz\n"); +#else + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#endif + + udelay(2000); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg, 0); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + ft_pci_setup(blob, bd); +} +#endif diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h new file mode 100644 index 0000000..e6d0c5e --- /dev/null +++ b/include/configs/MPC8360ERDK.h @@ -0,0 +1,538 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ +#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_CLKIN_33MHZ +#define CONFIG_83XX_CLKIN 33000000 +#define CONFIG_SYS_CLK_FREQ 33000000 +#define PCI_33M 1 +#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 +#else +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define PCI_66M 1 +#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 +#endif /* CONFIG_CLKIN_33MHZ */ + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ + HRCWL_CORE_TO_CSB_2X1 |\ + HRCWL_CE_TO_PLL_1X15) + +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCICKDRV_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_SECONDARY_DDR_DISABLE |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_EARLY) + +/* + * System IO Config + */ +#define CFG_SICRH 0x00000000 +#define CFG_SICRL 0x40000000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +#undef CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) +#define CFG_DDR_TIMING_0 0x00330903 +#define CFG_DDR_TIMING_1 0x3835a322 +#define CFG_DDR_TIMING_2 0x00104909 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47800432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x045b0100 +#define CFG_DDR_SDRAM_CFG 0x03000000 +#define CFG_DDR_SDRAM_CFG2 0x00001000 + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_FLASH_BASE 0xFF800000 /* FLASH base address */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ +#define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * NAND flash on the local bus + */ +#define CFG_NAND_BASE 0x60000000 + +#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE +#define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ + +/* Port size 8 bit, UPMA */ +#define CFG_BR1_PRELIM (CFG_NAND_BASE | 0x00000881) +#define CFG_OR1_PRELIM 0xfc000001 + +/* + * Fujitsu MB86277 (MINT) graphics controller + */ +#define CFG_VIDEO_BASE 0x70000000 + +#define CFG_LBLAWBAR2_PRELIM CFG_VIDEO_BASE +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */ + +/* Port size 32 bit, UPMB */ +#define CFG_BR2_PRELIM (CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */ +#define CFG_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI 1 + +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0xE0300000 +#define CFG_PCI1_IO_PHYS 0xE0300000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ + +#ifdef CONFIG_PCI + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK9 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 2 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK4 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 4 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif + +/* + * Environment + */ + +#ifndef CFG_RAMBOOT +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_SIZE 0x20000 +#else /* CFG_RAMBOOT */ +#define CFG_NO_FLASH 1 /* Flash is not usable now */ +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CFG_ENV_SIZE 0x2000 +#endif /* CFG_RAMBOOT */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_ASKENV + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_LOADS +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* NAND: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +#define CFG_IBAT5L (CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif /* CONFIG_PCI */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_ETHADDR 00:04:9f:ef:01:01 +#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 +#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03 +#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR a00000 +#define CONFIG_HOSTNAME mpc8360erdk +#define CONFIG_BOOTFILE uImage + +#define CONFIG_IPADDR 10.0.0.99 +#define CONFIG_SERVERIP 10.0.0.2 +#define CONFIG_GATEWAYIP 10.0.0.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_ROOTPATH /nfsroot/ + +#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0"\ + "consoledev=ttyS0\0"\ + "loadaddr=a00000\0"\ + "fdtaddr=900000\0"\ + "bootfile=uImage\0"\ + "fdtfile=dtb\0"\ + "fsfile=fs\0"\ + "ubootfile=u-boot.bin\0"\ + "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ + "$mtdparts panic=1\0"\ + "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ + "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ + "$gatewayip:$netmask:$hostname:$netdev:off "\ + "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "tftp_get_uboot=tftp 100000 $ubootfile\0"\ + "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ + "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ + "tftp_get_fs=tftp c00000 $fsfile\0"\ + "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ + "cp.b 100000 ff800000 $filesize\0"\ + "boot_m=bootm $loadaddr - $fdtaddr\0"\ + "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\ + "boot_m\0"\ + "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ + "boot_m\0"\ + "" + +#define CONFIG_BOOTCOMMAND "run dhcpboot" + +#endif /* __CONFIG_H */
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- drivers/mtd/nand/Makefile | 2 + drivers/mtd/nand/fsl_upm.c | 188 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/fsl_upm.h | 34 ++++++++ 3 files changed, 224 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsl_upm.c create mode 100644 include/linux/mtd/fsl_upm.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 42864f9..244fa09 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -32,6 +32,8 @@ COBJS-y += nand_ecc.o COBJS-y += nand_bbt.o COBJS-y += nand_util.o
+COBJS-y += fsl_upm.o + COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c new file mode 100644 index 0000000..81d03e7 --- /dev/null +++ b/drivers/mtd/nand/fsl_upm.c @@ -0,0 +1,188 @@ +/* + * FSL UPM NAND driver + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> + +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM) +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */ +#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */ +#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */ +#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */ + +void run_pattern(struct upm_data *ud, u32 cmd, u32 pat_offset) +{ + out_be32(ud->upm_mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); + out_be32(ud->upm_mar, cmd << 24); + out_8(ud->base, 0x0); + + if (ud->wait_pattern) { + /* + * Some boards/chips needs this. At least on MPC8360E-RDK we + * need it. Probably weird chip, because I don't see any need + * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are + * 0-2 unexpected busy states per block read. + */ + while (!ud->dev_ready()) + debug("unexpected busy state\n"); + } + + /* back to normal operation */ + out_be32(ud->upm_mxmr, FSL_UPM_MxMR_OP_NO); + while (in_be32(ud->upm_mxmr) != FSL_UPM_MxMR_OP_NO) + eieio(); +} + +static void setup_upm(struct upm_data *ud) +{ + int i; + + /* write upm array */ + out_be32(ud->upm_mxmr, FSL_UPM_MxMR_OP_WA); + + for (i = 0; i < 64; i++) { + out_be32(ud->upm_mdr, ud->upm_table[i]); + out_8(ud->base, 0x0); + } + + /* normal operation */ + out_be32(ud->upm_mxmr, FSL_UPM_MxMR_OP_NO); + while (in_be32(ud->upm_mxmr) != FSL_UPM_MxMR_OP_NO) + eieio(); +} + +static void nand_cmdfunc(struct mtd_info *mtd, unsigned command, int column, + int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct upm_data *ud = chip->priv; + + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + run_pattern(ud, readcmd, ud->upm_cmd_offset); + } + + run_pattern(ud, command, ud->upm_cmd_offset); + + if (column != -1) + run_pattern(ud, column, ud->upm_addr_offset); + + if (page_addr != -1) { + run_pattern(ud, page_addr, ud->upm_addr_offset); + run_pattern(ud, (page_addr >> 8) & 0xFF, ud->upm_addr_offset); + if (chip->chipsize > (32 << 20)) + run_pattern(ud, (page_addr >> 16) & 0x0f, + ud->upm_addr_offset); + } + + while (!ud->dev_ready()) + continue; +} + +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *chip = mtd->priv; + + out_8(chip->IO_ADDR_W, byte); +} + +static u8 nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + return in_8(chip->IO_ADDR_R); +} + +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) + chip->write_byte(mtd, buf[i]); +} + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = in_8(chip->IO_ADDR_R); +} + +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) { + if (buf[i] != in_8(chip->IO_ADDR_R)) + return -EFAULT; + } + + return 0; +} + +static void nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ +} + +static int nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct upm_data *ud = chip->priv; + + return ud->dev_ready(); +} + +int fsl_upm_nand_init(struct nand_chip *chip, struct upm_data *ud) +{ + /* yet only 8 bit accessors implemented */ + if (ud->width != 1) + return -ENOSYS; + + setup_upm(ud); + + chip->priv = ud; + chip->chip_delay = ud->chip_delay; + chip->eccmode = NAND_ECC_SOFT; + chip->hwcontrol = nand_hwcontrol; + chip->cmdfunc = nand_cmdfunc; + chip->read_byte = nand_read_byte; + chip->write_byte = nand_write_byte; + chip->read_buf = nand_read_buf; + chip->write_buf = nand_write_buf; + chip->verify_buf = nand_verify_buf; + chip->dev_ready = nand_dev_ready; + + return 0; +} +#endif /* CONFIG_CMD_NAND */ diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h new file mode 100644 index 0000000..1ac7158 --- /dev/null +++ b/include/linux/mtd/fsl_upm.h @@ -0,0 +1,34 @@ +/* + * FSL UPM NAND driver + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __LINUX_MTD_NAND_FSL_UPM +#define __LINUX_MTD_NAND_FSL_UPM + +#include <linux/mtd/nand.h> + +struct upm_data { + int width; + void *base; + void *upm_mxmr; + void *upm_mdr; + void *upm_mar; + u32 *upm_table; + int upm_cmd_offset; + int upm_addr_offset; + int wait_pattern; + int (*dev_ready)(void); + int chip_delay; +}; + +extern int fsl_upm_nand_init(struct nand_chip *chip, struct upm_data *ud); + +#endif
On Wednesday 09 January 2008, Anton Vorontsov wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
This seems to be based on the current NAND infrastructure. You might have noticed that I'm trying right now to merge the patches from William Yuul with the Linux 2.6.22 based NAND subsystem. There will be small changes needed on the driver. Please take a look at the u-boot-nand-flash custodian repository and rebase your patch against this.
Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
On Thu, Jan 10, 2008 at 06:31:06PM +0100, Stefan Roese wrote:
On Wednesday 09 January 2008, Anton Vorontsov wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
This seems to be based on the current NAND infrastructure. You might have noticed that I'm trying right now to merge the patches from William Yuul with the Linux 2.6.22 based NAND subsystem.
This is great news. Though, using u-boot-nand-flash tree I see that write.jffs2 isn't actually working (bad blocks skipping unimplemented), and read.jffs2 is unimplemented in whole...
Without .jffs2 variants nand support is almost useless. :-/ Unfortunately I don't have much time to help you with these updating efforts, implementing .jffs2... so I'd be glad if you'll ack second version of the patch[1] so we'll able to use it today with old nand layer. And I'll provide another patch[2] for your tree, that will update fsl_upm to use new infrastructure (tested to work on good blocks).
Will send [1] and [2] real soon now.
Thanks.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- drivers/mtd/nand/Makefile | 2 + drivers/mtd/nand/fsl_upm.c | 201 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/fsl_upm.h | 39 ++++++++ 3 files changed, 242 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsl_upm.c create mode 100644 include/linux/mtd/fsl_upm.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 42864f9..244fa09 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -32,6 +32,8 @@ COBJS-y += nand_ecc.o COBJS-y += nand_bbt.o COBJS-y += nand_util.o
+COBJS-y += fsl_upm.o + COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c new file mode 100644 index 0000000..5cc410a --- /dev/null +++ b/drivers/mtd/nand/fsl_upm.c @@ -0,0 +1,201 @@ +/* + * FSL UPM NAND driver + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> + +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM) +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */ +#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */ +#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */ +#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */ + +static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) +{ + out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); +} + +static void fsl_upm_end_pattern(struct fsl_upm *upm) +{ + out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); + while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) + eieio(); +} + +static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd) +{ + out_be32(upm->mar, cmd << (32 - width * 8)); + out_8(upm->io_addr, 0x0); +} + +static void fsl_upm_setup(struct fsl_upm *upm) +{ + int i; + + /* write upm array */ + out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA); + + for (i = 0; i < 64; i++) { + out_be32(upm->mdr, upm->array[i]); + out_8(upm->io_addr, 0x0); + } + + /* normal operation */ + out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); + while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) + eieio(); +} + +static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column, + int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_upm_nand *fun = chip->priv; + + fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); + + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + fsl_upm_run_pattern(&fun->upm, fun->width, readcmd); + } + + fsl_upm_run_pattern(&fun->upm, fun->width, command); + + fsl_upm_end_pattern(&fun->upm); + + fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); + + if (column != -1) + fsl_upm_run_pattern(&fun->upm, fun->width, column); + + if (page_addr != -1) { + fsl_upm_run_pattern(&fun->upm, fun->width, page_addr); + fsl_upm_run_pattern(&fun->upm, fun->width, + (page_addr >> 8) & 0xFF); + if (chip->chipsize > (32 << 20)) { + fsl_upm_run_pattern(&fun->upm, fun->width, + (page_addr >> 16) & 0x0f); + } + } + + fsl_upm_end_pattern(&fun->upm); + + if (fun->wait_pattern) { + /* + * Some boards/chips needs this. At least on MPC8360E-RDK we + * need it. Probably weird chip, because I don't see any need + * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are + * 0-2 unexpected busy states per block read. + */ + while (!fun->dev_ready()) + debug("unexpected busy state\n"); + } +} + +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *chip = mtd->priv; + + out_8(chip->IO_ADDR_W, byte); +} + +static u8 nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + return in_8(chip->IO_ADDR_R); +} + +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) + out_8(chip->IO_ADDR_W, buf[i]); +} + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = in_8(chip->IO_ADDR_R); +} + +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) { + if (buf[i] != in_8(chip->IO_ADDR_R)) + return -EFAULT; + } + + return 0; +} + +static void nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ +} + +static int nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_upm_nand *fun = chip->priv; + + return fun->dev_ready(); +} + +int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) +{ + /* yet only 8 bit accessors implemented */ + if (fun->width != 1) + return -ENOSYS; + + fsl_upm_setup(&fun->upm); + + chip->priv = fun; + chip->chip_delay = fun->chip_delay; + chip->eccmode = NAND_ECC_SOFT; + chip->cmdfunc = fun_cmdfunc; + chip->hwcontrol = nand_hwcontrol; + chip->read_byte = nand_read_byte; + chip->read_buf = nand_read_buf; + chip->write_byte = nand_write_byte; + chip->write_buf = nand_write_buf; + chip->verify_buf = nand_verify_buf; + chip->dev_ready = nand_dev_ready; + + return 0; +} +#endif /* CONFIG_CMD_NAND */ diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h new file mode 100644 index 0000000..634ff02 --- /dev/null +++ b/include/linux/mtd/fsl_upm.h @@ -0,0 +1,39 @@ +/* + * FSL UPM NAND driver + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __LINUX_MTD_NAND_FSL_UPM +#define __LINUX_MTD_NAND_FSL_UPM + +#include <linux/mtd/nand.h> + +struct fsl_upm { + const u32 *array; + void __iomem *mdr; + void __iomem *mxmr; + void __iomem *mar; + void __iomem *io_addr; +}; + +struct fsl_upm_nand { + struct fsl_upm upm; + + int width; + int upm_cmd_offset; + int upm_addr_offset; + int wait_pattern; + int (*dev_ready)(void); + int chip_delay; +}; + +extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); + +#endif
On Monday 14 January 2008, Anton Vorontsov wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
Applied, thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8360erdk/Makefile | 2 +- board/freescale/mpc8360erdk/nand.c | 75 ++++++++++++++++++++++++++++++++++ include/configs/MPC8360ERDK.h | 24 +++++++++++ 3 files changed, 100 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mpc8360erdk/nand.c
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile index acc9544..97ae11d 100644 --- a/board/freescale/mpc8360erdk/Makefile +++ b/board/freescale/mpc8360erdk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o +COBJS := $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c new file mode 100644 index 0000000..7c06a3f --- /dev/null +++ b/board/freescale/mpc8360erdk/nand.c @@ -0,0 +1,75 @@ +/* + * MPC8360E-RDK support for the NAND on FSL UPM + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> + +#if defined(CONFIG_CMD_NAND) +#include <common.h> +#include <asm/io.h> +#include <asm/immap_83xx.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +static struct immap *im = (struct immap *)CFG_IMMR; + +static const u32 upm_array[] = { + 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ + 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ + 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ + 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ + 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ + 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ + 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ + 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ + 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ + 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ + 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ +}; + +static int dev_ready(void) +{ + if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { + debug("nand ready\n"); + return 1; + } + + debug("nand busy\n"); + return 0; +} + +static struct fsl_upm_nand fun = { + .upm = { + .array = upm_array, + .io_addr = (void *)CFG_NAND_BASE, + }, + .width = 1, + .upm_cmd_offset = 8, + .upm_addr_offset = 16, + .dev_ready = dev_ready, + .wait_pattern = 1, + .chip_delay = 50, +}; + +int board_nand_init(struct nand_chip *nand) +{ + fun.upm.mxmr = &im->lbus.mamr; + fun.upm.mdr = &im->lbus.mdr; + fun.upm.mar = &im->lbus.mar; + return fsl_upm_nand_init(nand, &fun); +} +#endif /* CONFIG_CMD_NAND */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index e6d0c5e..b258d91 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -186,6 +186,11 @@ * NAND flash on the local bus */ #define CFG_NAND_BASE 0x60000000 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_UPM 1 +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ @@ -514,23 +519,42 @@ "fdtfile=dtb\0"\ "fsfile=fs\0"\ "ubootfile=u-boot.bin\0"\ + "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ "$mtdparts panic=1\0"\ "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ "$gatewayip:$netmask:$hostname:$netdev:off "\ "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ + "rootfstype=jffs2 rw\0"\ "tftp_get_uboot=tftp 100000 $ubootfile\0"\ "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ "tftp_get_fs=tftp c00000 $fsfile\0"\ + "nand_erase_kernel=nand erase 0 400000\0"\ + "nand_erase_dtb=nand erase 400000 20000\0"\ + "nand_erase_fs=nand erase 420000 3be0000\0"\ + "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\ + "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\ + "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\ + "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ + "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ "cp.b 100000 ff800000 $filesize\0"\ + "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ + "nand_write_kernel\0"\ + "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ + "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\ + "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\ + "nand_reflash_fs\0"\ "boot_m=bootm $loadaddr - $fdtaddr\0"\ "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\ "boot_m\0"\ "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ "boot_m\0"\ + "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ + "boot_m\0"\ ""
#define CONFIG_BOOTCOMMAND "run dhcpboot"
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- drivers/mtd/nand/fsl_upm.c | 68 +++++++++++-------------------------------- include/linux/mtd/fsl_upm.h | 3 ++ 2 files changed, 20 insertions(+), 51 deletions(-)
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 5cc410a..4775cdc 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -61,51 +61,28 @@ static void fsl_upm_setup(struct fsl_upm *upm) eieio(); }
-static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column, - int page_addr) +static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; struct fsl_upm_nand *fun = chip->priv;
- fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->oobblock) { - /* OOB area */ - column -= mtd->oobblock; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - fsl_upm_run_pattern(&fun->upm, fun->width, readcmd); - } - - fsl_upm_run_pattern(&fun->upm, fun->width, command); + if (!(ctrl & fun->last_ctrl)) { + fsl_upm_end_pattern(&fun->upm);
- fsl_upm_end_pattern(&fun->upm); + if (cmd == NAND_CMD_NONE) + return;
- fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - - if (column != -1) - fsl_upm_run_pattern(&fun->upm, fun->width, column); + fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); + }
- if (page_addr != -1) { - fsl_upm_run_pattern(&fun->upm, fun->width, page_addr); - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 8) & 0xFF); - if (chip->chipsize > (32 << 20)) { - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 16) & 0x0f); - } + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_ALE) + fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); + else if (ctrl & NAND_CLE) + fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); }
- fsl_upm_end_pattern(&fun->upm); + fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
if (fun->wait_pattern) { /* @@ -119,13 +96,6 @@ static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column, } }
-static void nand_write_byte(struct mtd_info *mtd, u_char byte) -{ - struct nand_chip *chip = mtd->priv; - - out_8(chip->IO_ADDR_W, byte); -} - static u8 nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -164,10 +134,6 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) return 0; }
-static void nand_hwcontrol(struct mtd_info *mtd, int cmd) -{ -} - static int nand_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -184,14 +150,14 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
fsl_upm_setup(&fun->upm);
+ fun->last_ctrl = NAND_CLE; + chip->priv = fun; chip->chip_delay = fun->chip_delay; - chip->eccmode = NAND_ECC_SOFT; - chip->cmdfunc = fun_cmdfunc; - chip->hwcontrol = nand_hwcontrol; + chip->ecc.mode = NAND_ECC_SOFT; + chip->cmd_ctrl = fun_cmd_ctrl; chip->read_byte = nand_read_byte; chip->read_buf = nand_read_buf; - chip->write_byte = nand_write_byte; chip->write_buf = nand_write_buf; chip->verify_buf = nand_verify_buf; chip->dev_ready = nand_dev_ready; diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h index 634ff02..5f0016d 100644 --- a/include/linux/mtd/fsl_upm.h +++ b/include/linux/mtd/fsl_upm.h @@ -32,6 +32,9 @@ struct fsl_upm_nand { int wait_pattern; int (*dev_ready)(void); int chip_delay; + + /* no need to fill */ + int last_ctrl; };
extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
On Monday 14 January 2008, Anton Vorontsov wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
Applied to new "mtd-2.6.22.1" branch. Will push to git server in a short while.
Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
On Monday 14 January 2008, Anton Vorontsov wrote:
On Thu, Jan 10, 2008 at 06:31:06PM +0100, Stefan Roese wrote:
On Wednesday 09 January 2008, Anton Vorontsov wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
This seems to be based on the current NAND infrastructure. You might have noticed that I'm trying right now to merge the patches from William Yuul with the Linux 2.6.22 based NAND subsystem.
This is great news. Though, using u-boot-nand-flash tree I see that write.jffs2 isn't actually working (bad blocks skipping unimplemented), and read.jffs2 is unimplemented in whole...
Without .jffs2 variants nand support is almost useless. :-/
Yes, I was thinking how we should handle this NAND MTD update currently. I'll post a different mail about this in a short while.
Unfortunately I don't have much time to help you with these updating efforts, implementing .jffs2... so I'd be glad if you'll ack second version of the patch[1] so we'll able to use it today with old nand layer. And I'll provide another patch[2] for your tree, that will update fsl_upm to use new infrastructure (tested to work on good blocks).
Will send [1] and [2] real soon now.
OK, if we all agree on how to handle the switch to the new NAND MTD subsystem (see other mail), then I'll accept your NAND driver patch right now. Let's wait how this discussion evolves.
Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8360erdk/Makefile | 2 +- board/freescale/mpc8360erdk/nand.c | 73 ++++++++++++++++++++++++++++++++++ include/configs/MPC8360ERDK.h | 24 +++++++++++ 3 files changed, 98 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mpc8360erdk/nand.c
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile index acc9544..97ae11d 100644 --- a/board/freescale/mpc8360erdk/Makefile +++ b/board/freescale/mpc8360erdk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o +COBJS := $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c new file mode 100644 index 0000000..80dc97c --- /dev/null +++ b/board/freescale/mpc8360erdk/nand.c @@ -0,0 +1,73 @@ +/* + * MPC8360E-RDK support for the NAND on FSL UPM + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> + +#if defined(CONFIG_CMD_NAND) +#include <common.h> +#include <asm/io.h> +#include <asm/immap_83xx.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +static struct immap *im = (struct immap *)CFG_IMMR; + +static u32 upm_table[] = { + 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ + 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ + 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ + 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ + 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ + 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ + 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ + 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ + 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ + 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ + 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ +}; + +static int dev_ready(void) +{ + if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { + debug("nand ready\n"); + return 1; + } + + debug("nand busy\n"); + return 0; +} + +static struct upm_data ud = { + .width = 1, + .base = (void *)CFG_NAND_BASE, + .upm_table = upm_table, + .upm_cmd_offset = 8, + .upm_addr_offset = 16, + .dev_ready = dev_ready, + .wait_pattern = 1, + .chip_delay = 50, +}; + +int board_nand_init(struct nand_chip *nand) +{ + ud.upm_mxmr = &im->lbus.mamr; + ud.upm_mdr = &im->lbus.mdr; + ud.upm_mar = &im->lbus.mar; + return fsl_upm_nand_init(nand, &ud); +} +#endif /* CONFIG_CMD_NAND */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index e6d0c5e..38692d5 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -185,7 +185,12 @@ /* * NAND flash on the local bus */ +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_UPM 1 #define CFG_NAND_BASE 0x60000000 +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ @@ -514,23 +519,42 @@ "fdtfile=dtb\0"\ "fsfile=fs\0"\ "ubootfile=u-boot.bin\0"\ + "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ "$mtdparts panic=1\0"\ "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ "$gatewayip:$netmask:$hostname:$netdev:off "\ "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ + "rootfstype=jffs2 rw\0"\ "tftp_get_uboot=tftp 100000 $ubootfile\0"\ "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ "tftp_get_fs=tftp c00000 $fsfile\0"\ + "nand_erase_kernel=nand erase 0 400000\0"\ + "nand_erase_dtb=nand erase 400000 20000\0"\ + "nand_erase_fs=nand erase 420000 3be0000\0"\ + "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\ + "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\ + "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\ + "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ + "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ "cp.b 100000 ff800000 $filesize\0"\ + "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ + "nand_write_kernel\0"\ + "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ + "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\ + "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\ + "nand_reflash_fs\0"\ "boot_m=bootm $loadaddr - $fdtaddr\0"\ "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\ "boot_m\0"\ "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ "boot_m\0"\ + "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ + "boot_m\0"\ ""
#define CONFIG_BOOTCOMMAND "run dhcpboot"
On Wed, 9 Jan 2008 20:57:58 +0300 Anton Vorontsov avorontsov@ru.mvista.com wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
board/freescale/mpc8360erdk/Makefile | 2 +- board/freescale/mpc8360erdk/nand.c | 73 ++++++++++++++++++++++++++++++++++ include/configs/MPC8360ERDK.h | 24 +++++++++++ 3 files changed, 98 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mpc8360erdk/nand.c
Hello Anton, since WD pulled the upm nand driver, I assumed this would apply, but it fails to build:
nand.c:55: error: variable 'ud' has initializer but incomplete type nand.c:56: error: unknown field 'width' specified in initializer nand.c:56: warning: excess elements in struct initializer nand.c:56: warning: (near initialization for 'ud') nand.c:57: error: unknown field 'base' specified in initializer nand.c:57: warning: excess elements in struct initializer nand.c:57: warning: (near initialization for 'ud') nand.c:58: error: unknown field 'upm_table' specified in initializer nand.c:58: warning: excess elements in struct initializer nand.c:58: warning: (near initialization for 'ud') nand.c:59: error: unknown field 'upm_cmd_offset' specified in initializer nand.c:59: warning: excess elements in struct initializer nand.c:59: warning: (near initialization for 'ud') nand.c:60: error: unknown field 'upm_addr_offset' specified in initializer nand.c:60: warning: excess elements in struct initializer nand.c:60: warning: (near initialization for 'ud') nand.c:61: error: unknown field 'dev_ready' specified in initializer nand.c:61: warning: excess elements in struct initializer nand.c:61: warning: (near initialization for 'ud') nand.c:62: error: unknown field 'wait_pattern' specified in initializer nand.c:62: warning: excess elements in struct initializer nand.c:62: warning: (near initialization for 'ud') nand.c:63: error: unknown field 'chip_delay' specified in initializer nand.c:63: warning: excess elements in struct initializer nand.c:63: warning: (near initialization for 'ud') nand.c: In function 'board_nand_init': nand.c:68: error: invalid use of undefined type 'struct upm_data' nand.c:69: error: invalid use of undefined type 'struct upm_data' nand.c:70: error: invalid use of undefined type 'struct upm_data' nand.c:71: warning: passing argument 2 of 'fsl_upm_nand_init' from incompatible pointer type
can you rebase and resend?
Kim
On Wed, Jan 16, 2008 at 12:31:02PM -0600, Kim Phillips wrote:
On Wed, 9 Jan 2008 20:57:58 +0300 Anton Vorontsov avorontsov@ru.mvista.com wrote:
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
board/freescale/mpc8360erdk/Makefile | 2 +- board/freescale/mpc8360erdk/nand.c | 73 ++++++++++++++++++++++++++++++++++ include/configs/MPC8360ERDK.h | 24 +++++++++++ 3 files changed, 98 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mpc8360erdk/nand.c
Hello Anton, since WD pulled the upm nand driver, I assumed this would apply, but it fails to build:
You're trying to apply v1. I've sent v2 driver & RDK support on Monday 14. Ok, let's duplicate it. ;-)
- - - - Date: Mon, 14 Jan 2008 23:09:45 +0300 Message-ID: 20080114200945.GB24168@localhost.localdomain From: Anton Vorontsov avorontsov@ru.mvista.com To: Kim Phillips kim.phillips@freescale.com Cc: Peter Barada peterb@logicpd.com, Stefan Roese sr@denx.de, u-boot-users@lists.sourceforge.net Subject: [U-Boot-Users] [PATCH v2 2/2] mpc83xx: MPC8360E-RDK: add support for NAND
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8360erdk/Makefile | 2 +- board/freescale/mpc8360erdk/nand.c | 75 ++++++++++++++++++++++++++++++++++ include/configs/MPC8360ERDK.h | 24 +++++++++++ 3 files changed, 100 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mpc8360erdk/nand.c
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile index acc9544..97ae11d 100644 --- a/board/freescale/mpc8360erdk/Makefile +++ b/board/freescale/mpc8360erdk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o +COBJS := $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c new file mode 100644 index 0000000..7c06a3f --- /dev/null +++ b/board/freescale/mpc8360erdk/nand.c @@ -0,0 +1,75 @@ +/* + * MPC8360E-RDK support for the NAND on FSL UPM + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> + +#if defined(CONFIG_CMD_NAND) +#include <common.h> +#include <asm/io.h> +#include <asm/immap_83xx.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +static struct immap *im = (struct immap *)CFG_IMMR; + +static const u32 upm_array[] = { + 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ + 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ + 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ + 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ + 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ + 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ + 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ + 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ + 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ + 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ + 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ +}; + +static int dev_ready(void) +{ + if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { + debug("nand ready\n"); + return 1; + } + + debug("nand busy\n"); + return 0; +} + +static struct fsl_upm_nand fun = { + .upm = { + .array = upm_array, + .io_addr = (void *)CFG_NAND_BASE, + }, + .width = 1, + .upm_cmd_offset = 8, + .upm_addr_offset = 16, + .dev_ready = dev_ready, + .wait_pattern = 1, + .chip_delay = 50, +}; + +int board_nand_init(struct nand_chip *nand) +{ + fun.upm.mxmr = &im->lbus.mamr; + fun.upm.mdr = &im->lbus.mdr; + fun.upm.mar = &im->lbus.mar; + return fsl_upm_nand_init(nand, &fun); +} +#endif /* CONFIG_CMD_NAND */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index e6d0c5e..b258d91 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -186,6 +186,11 @@ * NAND flash on the local bus */ #define CFG_NAND_BASE 0x60000000 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_UPM 1 +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ @@ -514,23 +519,42 @@ "fdtfile=dtb\0"\ "fsfile=fs\0"\ "ubootfile=u-boot.bin\0"\ + "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ "$mtdparts panic=1\0"\ "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ "$gatewayip:$netmask:$hostname:$netdev:off "\ "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ + "rootfstype=jffs2 rw\0"\ "tftp_get_uboot=tftp 100000 $ubootfile\0"\ "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ "tftp_get_fs=tftp c00000 $fsfile\0"\ + "nand_erase_kernel=nand erase 0 400000\0"\ + "nand_erase_dtb=nand erase 400000 20000\0"\ + "nand_erase_fs=nand erase 420000 3be0000\0"\ + "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\ + "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\ + "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\ + "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ + "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ "cp.b 100000 ff800000 $filesize\0"\ + "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ + "nand_write_kernel\0"\ + "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ + "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\ + "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\ + "nand_reflash_fs\0"\ "boot_m=bootm $loadaddr - $fdtaddr\0"\ "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\ "boot_m\0"\ "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ "boot_m\0"\ + "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ + "boot_m\0"\ ""
#define CONFIG_BOOTCOMMAND "run dhcpboot"
This patch adds basic support for Broadcom BCM5481 PHY, with the quirk needed for at least MPC8360E-RDK.
Quirk comes from MPC8360E-RDK BSP source, I think author is Peter Barada peterb@logicpd.com, but I'm not sure.
There are no openly available specifications for that PHY.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- drivers/qe/uec_phy.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec_phy.h | 5 +++ 2 files changed, 82 insertions(+), 0 deletions(-)
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index ca6faa6..6882d03 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -237,6 +237,44 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info) return 0; }
+static int gbit_read_status(struct uec_mii_info *mii_info) +{ + u16 status; + int err; + + err = genmii_update_link(mii_info); + if (err) + return err; + + if (mii_info->autoneg) { + mii_info->pause = 0; + status = phy_read(mii_info, MII_1000BASETSTATUS); + if (status & (LPA_1000FULL | LPA_1000HALF)) { + mii_info->speed = SPEED_1000; + if (status & LPA_1000FULL) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + } else { + status = phy_read(mii_info, PHY_ANLPAR); + + if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + } + } + /* + * On non-aneg, we assume what we put in BMCR is the speed, + * though magic-aneg shouldn't prevent this case from occurring. + */ + return 0; +} + static int marvell_config_aneg (struct uec_mii_info *mii_info) { /* The Marvell PHY has an errata which requires @@ -319,6 +357,35 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return 0; }
+static int bcm_init(struct uec_mii_info *mii_info) +{ + gbit_config_aneg(mii_info); + +#ifdef CONFIG_MPC8360ERDK + { + u16 val; + int cnt = 50; + + /* Wait for aneg to complete. */ + do + val = phy_read(mii_info, PHY_BMSR); + while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); + + /* Set RDX clk delay. */ + phy_write(mii_info, 0x18, 0x7 | (7 << 12)); + + val = phy_read(mii_info, 0x18); + /* Set RDX-RXC skew. */ + val |= (1<<8); + val |= (7 | (7 << 12)); + /* Write bits 14:0. */ + val |= (1<<15); + phy_write(mii_info, 0x18, val); + } +#endif + return 0; +} + static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -491,6 +558,15 @@ static struct phy_info phy_info_marvell = { .config_intr = &marvell_config_intr, };
+static struct phy_info phy_info_bcm5481 = { + .phy_id = 0x0143bca0, + .phy_id_mask = 0xffffff0, + .name = "Broadcom 5481", + .features = MII_GBIT_FEATURES, + .read_status = gbit_read_status, + .init = bcm_init, +}; + static struct phy_info phy_info_genmii = { .phy_id = 0x00000000, .phy_id_mask = 0x00000000, @@ -504,6 +580,7 @@ static struct phy_info *phy_info[] = { &phy_info_dm9161, &phy_info_dm9161a, &phy_info_marvell, + &phy_info_bcm5481, &phy_info_genmii, NULL }; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index e59a940..6f769fb 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -29,6 +29,11 @@ #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
+/* 1000BT status */ +#define MII_1000BASETSTATUS 0x0a +#define LPA_1000FULL 0x0400 +#define LPA_1000HALF 0x0200 + /* Cicada Extended Control Register 1 */ #define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000
Anton Vorontsov wrote:
This patch adds basic support for Broadcom BCM5481 PHY, with the quirk needed for at least MPC8360E-RDK.
Quirk comes from MPC8360E-RDK BSP source, I think author is Peter Barada peterb@logicpd.com, but I'm not sure.
There are no openly available specifications for that PHY.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
drivers/qe/uec_phy.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec_phy.h | 5 +++ 2 files changed, 82 insertions(+), 0 deletions(-)
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index ca6faa6..6882d03 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -237,6 +237,44 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info) return 0; }
+static int gbit_read_status(struct uec_mii_info *mii_info) +{
- u16 status;
- int err;
- err = genmii_update_link(mii_info);
- if (err)
return err;- if (mii_info->autoneg) {
mii_info->pause = 0;status = phy_read(mii_info, MII_1000BASETSTATUS);if (status & (LPA_1000FULL | LPA_1000HALF)) {mii_info->speed = SPEED_1000;if (status & LPA_1000FULL)mii_info->duplex = DUPLEX_FULL;elsemii_info->duplex = DUPLEX_HALF;} else {status = phy_read(mii_info, PHY_ANLPAR);if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))mii_info->duplex = DUPLEX_FULL;elsemii_info->duplex = DUPLEX_HALF;if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))mii_info->speed = SPEED_100;elsemii_info->speed = SPEED_10;}- }
- /*
* On non-aneg, we assume what we put in BMCR is the speed,* though magic-aneg shouldn't prevent this case from occurring.*/return 0;+}
Please roll the 1Gb code into genmii_read_status. 10/100 PHYs should report 0 in the MII_1000BASETSTATUS register so it should work.
static int marvell_config_aneg (struct uec_mii_info *mii_info) { /* The Marvell PHY has an errata which requires @@ -319,6 +357,35 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return 0; }
+static int bcm_init(struct uec_mii_info *mii_info) +{
- gbit_config_aneg(mii_info);
+#ifdef CONFIG_MPC8360ERDK
- {
u16 val;int cnt = 50;/* Wait for aneg to complete. */doval = phy_read(mii_info, PHY_BMSR);while (--cnt && !(val & PHY_BMSR_AUTN_COMP));/* Set RDX clk delay. */phy_write(mii_info, 0x18, 0x7 | (7 << 12));val = phy_read(mii_info, 0x18);/* Set RDX-RXC skew. */val |= (1<<8);val |= (7 | (7 << 12));/* Write bits 14:0. */val |= (1<<15);phy_write(mii_info, 0x18, val);- }
+#endif
What is it that makes this specific to one board? Magic numbers are baaaad, especially for industry-standard memory maps (I'm thinking of offset 0x18 in case it's not obvious)
return 0;+}
static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -491,6 +558,15 @@ static struct phy_info phy_info_marvell = { .config_intr = &marvell_config_intr, };
+static struct phy_info phy_info_bcm5481 = {
- .phy_id = 0x0143bca0,
- .phy_id_mask = 0xffffff0,
- .name = "Broadcom 5481",
- .features = MII_GBIT_FEATURES,
- .read_status = gbit_read_status,
- .init = bcm_init,
+};
static struct phy_info phy_info_genmii = { .phy_id = 0x00000000, .phy_id_mask = 0x00000000, @@ -504,6 +580,7 @@ static struct phy_info *phy_info[] = { &phy_info_dm9161, &phy_info_dm9161a, &phy_info_marvell,
- &phy_info_bcm5481, &phy_info_genmii, NULL
}; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index e59a940..6f769fb 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -29,6 +29,11 @@ #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
+/* 1000BT status */ +#define MII_1000BASETSTATUS 0x0a +#define LPA_1000FULL 0x0400 +#define LPA_1000HALF 0x0200
/* Cicada Extended Control Register 1 */ #define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000
On Thu, 2008-01-10 at 15:41 -0500, Ben Warren wrote:
Anton Vorontsov wrote:
This patch adds basic support for Broadcom BCM5481 PHY, with the quirk needed for at least MPC8360E-RDK.
Quirk comes from MPC8360E-RDK BSP source, I think author is Peter Barada peterb@logicpd.com, but I'm not sure.
There are no openly available specifications for that PHY.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
drivers/qe/uec_phy.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec_phy.h | 5 +++ 2 files changed, 82 insertions(+), 0 deletions(-)
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index ca6faa6..6882d03 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -237,6 +237,44 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info) return 0; }
+static int gbit_read_status(struct uec_mii_info *mii_info) +{
- u16 status;
- int err;
- err = genmii_update_link(mii_info);
- if (err)
return err;- if (mii_info->autoneg) {
mii_info->pause = 0;status = phy_read(mii_info, MII_1000BASETSTATUS);if (status & (LPA_1000FULL | LPA_1000HALF)) {mii_info->speed = SPEED_1000;if (status & LPA_1000FULL)mii_info->duplex = DUPLEX_FULL;elsemii_info->duplex = DUPLEX_HALF;} else {status = phy_read(mii_info, PHY_ANLPAR);if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))mii_info->duplex = DUPLEX_FULL;elsemii_info->duplex = DUPLEX_HALF;if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))mii_info->speed = SPEED_100;elsemii_info->speed = SPEED_10;}- }
- /*
* On non-aneg, we assume what we put in BMCR is the speed,* though magic-aneg shouldn't prevent this case from occurring.*/return 0;+}
Please roll the 1Gb code into genmii_read_status. 10/100 PHYs should report 0 in the MII_1000BASETSTATUS register so it should work.
static int marvell_config_aneg (struct uec_mii_info *mii_info) { /* The Marvell PHY has an errata which requires @@ -319,6 +357,35 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return 0; }
+static int bcm_init(struct uec_mii_info *mii_info) +{
- gbit_config_aneg(mii_info);
+#ifdef CONFIG_MPC8360ERDK
- {
u16 val;int cnt = 50;/* Wait for aneg to complete. */doval = phy_read(mii_info, PHY_BMSR);while (--cnt && !(val & PHY_BMSR_AUTN_COMP));/* Set RDX clk delay. */phy_write(mii_info, 0x18, 0x7 | (7 << 12));val = phy_read(mii_info, 0x18);/* Set RDX-RXC skew. */val |= (1<<8);val |= (7 | (7 << 12));/* Write bits 14:0. */val |= (1<<15);phy_write(mii_info, 0x18, val);- }
+#endif
What is it that makes this specific to one board? Magic numbers are baaaad, especially for industry-standard memory maps (I'm thinking of offset 0x18 in case it's not obvious)
Its specific to the board, in that when hooked up via RGMII the setting in the PHY is required to supply adequate delay between the RXD and RXC signals instead of using trace lengths to achieve timing. I know magic numbers are baaaaad, but the PHY spec is only available under NDA and as such descriptions(including informative constants, etc) can not be disclosed. If it wasn't for this one register setting(after reset), the PHY, as used, wouldn't require any PHY-specific code(outside of ID'ng it as a 5481).
return 0;+}
static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -491,6 +558,15 @@ static struct phy_info phy_info_marvell = { .config_intr = &marvell_config_intr, };
+static struct phy_info phy_info_bcm5481 = {
- .phy_id = 0x0143bca0,
- .phy_id_mask = 0xffffff0,
- .name = "Broadcom 5481",
- .features = MII_GBIT_FEATURES,
- .read_status = gbit_read_status,
- .init = bcm_init,
+};
static struct phy_info phy_info_genmii = { .phy_id = 0x00000000, .phy_id_mask = 0x00000000, @@ -504,6 +580,7 @@ static struct phy_info *phy_info[] = { &phy_info_dm9161, &phy_info_dm9161a, &phy_info_marvell,
- &phy_info_bcm5481, &phy_info_genmii, NULL
}; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index e59a940..6f769fb 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -29,6 +29,11 @@ #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
+/* 1000BT status */ +#define MII_1000BASETSTATUS 0x0a +#define LPA_1000FULL 0x0400 +#define LPA_1000HALF 0x0200
/* Cicada Extended Control Register 1 */ #define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000
Peter Barada wrote:
On Thu, 2008-01-10 at 15:41 -0500, Ben Warren wrote:
Anton Vorontsov wrote:
This patch adds basic support for Broadcom BCM5481 PHY, with the quirk needed for at least MPC8360E-RDK.
Quirk comes from MPC8360E-RDK BSP source, I think author is Peter Barada peterb@logicpd.com, but I'm not sure.
There are no openly available specifications for that PHY.
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com
drivers/qe/uec_phy.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec_phy.h | 5 +++ 2 files changed, 82 insertions(+), 0 deletions(-)
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index ca6faa6..6882d03 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -237,6 +237,44 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info) return 0; }
+static int gbit_read_status(struct uec_mii_info *mii_info) +{
- u16 status;
- int err;
- err = genmii_update_link(mii_info);
- if (err)
return err;- if (mii_info->autoneg) {
mii_info->pause = 0;status = phy_read(mii_info, MII_1000BASETSTATUS);if (status & (LPA_1000FULL | LPA_1000HALF)) {mii_info->speed = SPEED_1000;if (status & LPA_1000FULL)mii_info->duplex = DUPLEX_FULL;elsemii_info->duplex = DUPLEX_HALF;} else {status = phy_read(mii_info, PHY_ANLPAR);if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))mii_info->duplex = DUPLEX_FULL;elsemii_info->duplex = DUPLEX_HALF;if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))mii_info->speed = SPEED_100;elsemii_info->speed = SPEED_10;}- }
- /*
* On non-aneg, we assume what we put in BMCR is the speed,* though magic-aneg shouldn't prevent this case from occurring.*/return 0;+}
Please roll the 1Gb code into genmii_read_status. 10/100 PHYs should report 0 in the MII_1000BASETSTATUS register so it should work.
static int marvell_config_aneg (struct uec_mii_info *mii_info) { /* The Marvell PHY has an errata which requires @@ -319,6 +357,35 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return 0; }
+static int bcm_init(struct uec_mii_info *mii_info) +{
- gbit_config_aneg(mii_info);
+#ifdef CONFIG_MPC8360ERDK
- {
u16 val;int cnt = 50;/* Wait for aneg to complete. */doval = phy_read(mii_info, PHY_BMSR);while (--cnt && !(val & PHY_BMSR_AUTN_COMP));/* Set RDX clk delay. */phy_write(mii_info, 0x18, 0x7 | (7 << 12));val = phy_read(mii_info, 0x18);/* Set RDX-RXC skew. */val |= (1<<8);val |= (7 | (7 << 12));/* Write bits 14:0. */val |= (1<<15);phy_write(mii_info, 0x18, val);- }
+#endif
What is it that makes this specific to one board? Magic numbers are baaaad, especially for industry-standard memory maps (I'm thinking of offset 0x18 in case it's not obvious)
Its specific to the board, in that when hooked up via RGMII the setting in the PHY is required to supply adequate delay between the RXD and RXC signals instead of using trace lengths to achieve timing. I know magic numbers are baaaaad, but the PHY spec is only available under NDA and as such descriptions(including informative constants, etc) can not be disclosed. If it wasn't for this one register setting(after reset), the PHY, as used, wouldn't require any PHY-specific code(outside of ID'ng it as a 5481).
Is this just due to a layout problem on the reference board, or do you always need to do this when connecting this MAC/PHY combo via RGMII? If the former, the additional registers needs to be set in board code. If the latter, please do something like this: Add an 'enet_interface_e if_mode' entry to the 'struct uec_mii_info' definition, and fill it in when you call 'uec_set_mac_if_mode()' and check the value for RGMII when 'bcm_init()' is called.
Sorry, but having a *reference* board #ifdef'd in library code is just wrong.
Regarding the magic numbers, something like this would be better:
#define MII_BCM_BCM_PRIVATE_0 0x16 #define MII_BCM_BCM_PRIVATE_1 0x17 #define MII_BCM_BCM_PRIVATE_2 0x18
regards, Ben
On Wed, 9 Jan 2008 20:50:51 +0300 Anton Vorontsov avorontsov@ru.mvista.com wrote:
Hi all,
Here are few patches needed to support MPC8360E-RDK...
applied 1-2. looks like 4 depends on 3 going through Stefan, and 5 will go through Ben Warren.
Thanks Anton,
Kim
participants (5)
-
Anton Vorontsov -
Ben Warren -
Kim Phillips -
Peter Barada -
Stefan Roese