It is my understanding that the 405EX CPU is not Book-E, however in include/asm-ppc/processor.h line 390, Book-E definitions are used for the 405EX. Is this correct?

I am still trying to debug the cause of the AMCC 405EX Trap (see that thread for more info) and found this. I was trying to see if SRR2 is being displayed in the register dump when I get the machine check on my board.

From what I can tell, the 405EX does not have a CSRR0/1, but the SRR2/3 registers have the same functionality. Elsewhere in the code, that is noted and csrr0/1 are defined. Yet, the exception code that is executed, utilizes the Book-E definitions in processor.h.

Again I ask, is this correct? It would seem like there should be a compiler directive that determines which definitions to use and define SPRN_CSRR0 to SRR2 and SPRN_CSRR1 to SRR3 and so on for the 34 Book-E definitions defined.

Am I correct in my thinking or am I way off? Either way, please let me know. If this is a bug, it should be easily fixed.

Thanks!

Jonathan

-- Jonathan R. Haws Electrical Engineering Space Dynamics Laboratory

Jonathan.Haws@sdl.usu.edu (435)797-4629