[U-Boot] [PATCH 1/4] reset: uniphier: fix compatible for SD reset node for LD11/LD20

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Masahiro Yamada

29 Aug 2017 29 Aug '17

5:20 a.m.

LD20 has SD ctrl instead of MIO ctrl. LD11 has both of them.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

drivers/reset/reset-uniphier.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index ebb2cae5eb33..8a037cf735dd 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -294,7 +294,11 @@ static const struct udevice_id uniphier_reset_match[] = { .data = (ulong)uniphier_mio_reset_data, }, { - .compatible = "socionext,uniphier-ld20-mio-reset", + .compatible = "socionext,uniphier-ld11-sd-reset", + .data = (ulong)uniphier_mio_reset_data, + }, + { + .compatible = "socionext,uniphier-ld20-sd-reset", .data = (ulong)uniphier_mio_reset_data, }, /* Peripheral reset */

-- 2.7.4

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Masahiro Yamada

29 Aug 29 Aug

5:20 a.m.

New subject: [U-Boot] [PATCH 2/4] reset: uniphier: add PXs3 support

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

drivers/reset/reset-uniphier.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 8a037cf735dd..b6bde70d6f6e 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -77,6 +77,17 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESET_END, };

+static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { + UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ + UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ + UNIPHIER_RESETX(12, 0x200c, 5), /* GIO0 */ + UNIPHIER_RESETX(13, 0x200c, 6), /* GIO1 */ + UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY */ + UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY */ + UNIPHIER_RESET_END, +}; + /* Media I/O reset data */ #define UNIPHIER_MIO_RESET_SD(id, ch) \ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) @@ -268,6 +279,10 @@ static const struct udevice_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-reset", .data = (ulong)uniphier_ld20_sys_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-reset", + .data = (ulong)uniphier_pxs3_sys_reset_data, + }, /* Media I/O reset */ { .compatible = "socionext,uniphier-ld4-mio-reset", @@ -301,6 +316,10 @@ static const struct udevice_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-sd-reset", .data = (ulong)uniphier_mio_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-sd-reset", + .data = (ulong)uniphier_mio_reset_data, + }, /* Peripheral reset */ { .compatible = "socionext,uniphier-ld4-peri-reset", @@ -330,6 +349,10 @@ static const struct udevice_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-peri-reset", .data = (ulong)uniphier_pro4_peri_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-peri-reset", + .data = (ulong)uniphier_pro4_peri_reset_data, + }, { /* sentinel */ } };

-- 2.7.4

Masahiro Yamada

5:20 a.m.

New subject: [U-Boot] [PATCH 3/4] ARM: dts: uniphier: sync with Linux

Import updates queued up for Linux 4.14-rc1.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/dts/uniphier-ld11-global.dts | 6 +++++- arch/arm/dts/uniphier-ld11-ref.dts | 6 +++--- arch/arm/dts/uniphier-ld11.dtsi | 13 +++++++++---- arch/arm/dts/uniphier-ld20-global.dts | 6 +++++- arch/arm/dts/uniphier-ld20-ref.dts | 6 +++--- arch/arm/dts/uniphier-ld20.dtsi | 15 ++++++++++----- arch/arm/dts/uniphier-ld4-ref.dts | 6 +++--- arch/arm/dts/uniphier-ld4.dtsi | 11 ++++++----- arch/arm/dts/uniphier-ld6b-ref.dts | 6 +++--- arch/arm/dts/uniphier-ld6b.dtsi | 2 +- arch/arm/dts/uniphier-pinctrl.dtsi | 5 +++++ arch/arm/dts/uniphier-pro4-ace.dts | 2 +- arch/arm/dts/uniphier-pro4-ref.dts | 6 +++--- arch/arm/dts/uniphier-pro4-sanji.dts | 2 +- arch/arm/dts/uniphier-pro4.dtsi | 9 +++++---- arch/arm/dts/uniphier-pro5-4kbox.dts | 4 ++-- arch/arm/dts/uniphier-pro5.dtsi | 13 +++++++------ arch/arm/dts/uniphier-pxs2-gentil.dts | 2 +- arch/arm/dts/uniphier-pxs2-vodka.dts | 2 +- arch/arm/dts/uniphier-pxs2.dtsi | 13 +++++++------ arch/arm/dts/uniphier-sld8-ref.dts | 6 +++--- arch/arm/dts/uniphier-sld8.dtsi | 11 ++++++----- 22 files changed, 90 insertions(+), 62 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts index 7a650a02486a..5ffe7dedf723 100644 --- a/arch/arm/dts/uniphier-ld11-global.dts +++ b/arch/arm/dts/uniphier-ld11-global.dts @@ -9,7 +9,7 @@ */

/dts-v1/; -/include/ "uniphier-ld11.dtsi" +#include "uniphier-ld11.dtsi"

/ { model = "UniPhier LD11 Global Board (REF_LD11_GP)"; @@ -68,3 +68,7 @@ &usb2 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts index cc8ebe34c27c..ffb473ad2e0f 100644 --- a/arch/arm/dts/uniphier-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -8,9 +8,9 @@ */

/dts-v1/; -/include/ "uniphier-ld11.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-ld11.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier LD11 Reference Board"; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 74f8f721a888..0f172c31db69 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -348,9 +348,11 @@ }; };

- aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-ld11-aidet"; reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

gic: interrupt-controller@5fe00000 { @@ -376,6 +378,10 @@ compatible = "socionext,uniphier-ld11-reset"; #reset-cells = <1>; }; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; };

nand: nand@68000000 { @@ -387,9 +393,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; }; }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index 9f620d4101b5..fc2bc9d75d35 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -9,7 +9,7 @@ */

/dts-v1/; -/include/ "uniphier-ld20.dtsi" +#include "uniphier-ld20.dtsi"

/ { model = "UniPhier LD20 Global Board (REF_LD20_GP)"; @@ -50,3 +50,7 @@ &i2c0 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 494166aee24c..1ca0c8620dc5 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -8,9 +8,9 @@ */

/dts-v1/; -/include/ "uniphier-ld20.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-ld20.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier LD20 Reference Board"; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 44257aff35b9..a7fdaa74d155 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -313,7 +313,7 @@ sdctrl@59810000 { compatible = "socionext,uniphier-ld20-sdctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; + reg = <0x59810000 0x400>;

sd_clk: clock { compatible = "socionext,uniphier-ld20-sd-clock"; @@ -383,9 +383,11 @@ }; };

- aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-ld20-aidet"; reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

gic: interrupt-controller@5fe00000 { @@ -411,6 +413,10 @@ compatible = "socionext,uniphier-ld20-reset"; #reset-cells = <1>; }; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; };

usb: usb@65b00000 { @@ -440,9 +446,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; }; }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts index 0520e3cff1a5..0f50acb24c2c 100644 --- a/arch/arm/dts/uniphier-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ld4-ref.dts @@ -8,9 +8,9 @@ */

/dts-v1/; -/include/ "uniphier-ld4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-ld4.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier LD4 Reference Board"; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index 18a105a58f9c..a3bcf227f438 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -424,9 +424,11 @@ interrupt-controller; };

- aidet@61830000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@61830000 { + compatible = "socionext,uniphier-ld4-aidet"; reg = <0x61830000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

sysctrl@61840000 { @@ -452,11 +454,10 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; + pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; }; }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts index b4bb5b546a03..bdb7f50ab3a0 100644 --- a/arch/arm/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -8,9 +8,9 @@ */

/dts-v1/; -/include/ "uniphier-ld6b.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-ld6b.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier LD6b Reference Board"; diff --git a/arch/arm/dts/uniphier-ld6b.dtsi b/arch/arm/dts/uniphier-ld6b.dtsi index 8b9a79731bd3..9a7b25cc8233 100644 --- a/arch/arm/dts/uniphier-ld6b.dtsi +++ b/arch/arm/dts/uniphier-ld6b.dtsi @@ -12,7 +12,7 @@ * The D-chip (digital chip) is the same as the PXs2 die. * Reuse the PXs2 device tree with some properties overridden. */ -/include/ "uniphier-pxs2.dtsi" +#include "uniphier-pxs2.dtsi"

/ { compatible = "socionext,uniphier-ld6b"; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index f5c155261259..d5e8aafccbd6 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -8,6 +8,11 @@ */

&pinctrl { + pinctrl_aout: aout_grp { + groups = "aout"; + function = "aout"; + }; + pinctrl_emmc: emmc_grp { groups = "emmc", "emmc_dat8"; function = "emmc"; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index 9276f8d913b6..8161ba83a047 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -8,7 +8,7 @@ */

/dts-v1/; -/include/ "uniphier-pro4.dtsi" +#include "uniphier-pro4.dtsi"

/ { model = "UniPhier Pro4 Ace Board"; diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts index 13e1b3ec8828..360b31d6927a 100644 --- a/arch/arm/dts/uniphier-pro4-ref.dts +++ b/arch/arm/dts/uniphier-pro4-ref.dts @@ -8,9 +8,9 @@ */

/dts-v1/; -/include/ "uniphier-pro4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-pro4.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier Pro4 Reference Board"; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 568dbd5a4ae3..778e2bb4b78d 100644 --- a/arch/arm/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -8,7 +8,7 @@ */

/dts-v1/; -/include/ "uniphier-pro4.dtsi" +#include "uniphier-pro4.dtsi"

/ { model = "UniPhier Pro4 Sanji Board"; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index cbb848207cc1..b45f23ce7c83 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -531,9 +531,11 @@ }; };

- aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

timer@60000200 { @@ -619,9 +621,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; }; }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-pro5-4kbox.dts b/arch/arm/dts/uniphier-pro5-4kbox.dts index d59309000b5a..05597d385edc 100644 --- a/arch/arm/dts/uniphier-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-pro5-4kbox.dts @@ -8,7 +8,7 @@ */

/dts-v1/; -/include/ "uniphier-pro5.dtsi" +#include "uniphier-pro5.dtsi"

/ { model = "UniPhier Pro5 4KBOX Board"; @@ -26,7 +26,7 @@ i2c6 = &i2c6; };

- memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 498354c45f90..94eb65651296 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -500,7 +500,7 @@ sdctrl@59810000 { compatible = "socionext,uniphier-pro5-sdctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; + reg = <0x59810000 0x400>; u-boot,dm-pre-reloc;

sd_clk: clock { @@ -542,9 +542,11 @@ }; };

- aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

timer@60000200 { @@ -628,9 +630,8 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; + pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; };

emmc: sdhc@68400000 { @@ -670,4 +671,4 @@ }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts index 6f691a8b42c8..7f0f972bde4f 100644 --- a/arch/arm/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/dts/uniphier-pxs2-gentil.dts @@ -8,7 +8,7 @@ */

/dts-v1/; -/include/ "uniphier-pxs2.dtsi" +#include "uniphier-pxs2.dtsi"

/ { model = "UniPhier PXs2 Gentil Board"; diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts index d13e5f2b6c10..ec9ffb7df8b1 100644 --- a/arch/arm/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/dts/uniphier-pxs2-vodka.dts @@ -8,7 +8,7 @@ */

/dts-v1/; -/include/ "uniphier-pxs2.dtsi" +#include "uniphier-pxs2.dtsi"

/ { model = "UniPhier PXs2 Vodka Board"; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 32844f781f5a..c304d90874f1 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -477,7 +477,7 @@ sdctrl@59810000 { compatible = "socionext,uniphier-pxs2-sdctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; + reg = <0x59810000 0x400>; u-boot,dm-pre-reloc;

sd_clk: clock { @@ -554,9 +554,11 @@ }; };

- aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

timer@60000200 { @@ -640,11 +642,10 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; + pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; }; }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts index 6ddf2a1b1df7..3557bb7fed57 100644 --- a/arch/arm/dts/uniphier-sld8-ref.dts +++ b/arch/arm/dts/uniphier-sld8-ref.dts @@ -8,9 +8,9 @@ */

/dts-v1/; -/include/ "uniphier-sld8.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-sld8.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier sLD8 Reference Board"; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 7d6370f6afe2..a3de26b40cc9 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -424,9 +424,11 @@ interrupt-controller; };

- aidet@61830000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@61830000 { + compatible = "socionext,uniphier-sld8-aidet"; reg = <0x61830000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi"

-- 2.7.4

Masahiro Yamada

5:20 a.m.

New subject: [U-Boot] [PATCH 4/4] ARM: dts: uniphier: update PXs3 SoC/board DT

Support PXs3 SoC and its reference development board.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/dts/uniphier-pxs3-ref.dts | 21 ++++-- arch/arm/dts/uniphier-pxs3.dtsi | 127 ++++++++++++++++++++++++------------- 2 files changed, 98 insertions(+), 50 deletions(-)

diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts index cb1eef43c464..d65f746a3f9d 100644 --- a/arch/arm/dts/uniphier-pxs3-ref.dts +++ b/arch/arm/dts/uniphier-pxs3-ref.dts @@ -4,13 +4,12 @@ * Copyright (C) 2017 Socionext Inc. * Author: Masahiro Yamada yamada.masahiro@socionext.com * - * SPDX-License-Identifier: GPL-2.0+ X11 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */

/dts-v1/; -/include/ "uniphier-pxs3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-pxs3.dtsi" +#include "uniphier-support-card.dtsi"

/ { model = "UniPhier PXs3 Reference Board"; @@ -39,7 +38,7 @@ };

&ethsc { - interrupts = <0 48 4>; + interrupts = <0 52 4>; };

&serial0 { @@ -49,3 +48,15 @@ &i2c0 { status = "okay"; }; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index cdf7f9005f73..8615ba0bc771 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -4,46 +4,10 @@ * Copyright (C) 2017 Socionext Inc. * Author: Masahiro Yamada yamada.masahiro@socionext.com * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */

-/memreserve/ 0x80000000 0x00080000; +/memreserve/ 0x80000000 0x02000000;

/ { compatible = "socionext,uniphier-pxs3"; @@ -76,28 +40,74 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; };

cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; };

cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x002>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; };

cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x003>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + clock-latency-ns = <300>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + clock-latency-ns = <300>; + }; + opp-666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp-866667000 { + opp-hz = /bits/ 64 <866667000>; + clock-latency-ns = <300>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <300>; }; };

@@ -172,6 +182,22 @@ clock-frequency = <58820000>; };

+ gpio: gpio@55000000 { + compatible = "socionext,uniphier-pxs3-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>, + <&pinctrl 160 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; @@ -205,6 +231,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -251,7 +279,7 @@ sdctrl@59810000 { compatible = "socionext,uniphier-pxs3-sdctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; + reg = <0x59810000 0x400>;

sd_clk: clock { compatible = "socionext,uniphier-pxs3-sd-clock"; @@ -282,7 +310,6 @@

emmc: sdhc@5a000000 { compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - status = "disabled"; reg = <0x5a000000 0x400>; interrupts = <0 78 4>; pinctrl-names = "default"; @@ -291,6 +318,11 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; + cdns,phy-dll-delay-sdclk = <21>; + cdns,phy-dll-delay-sdclk-hsmmc = <21>; };

sd: sdhc@5a400000 { @@ -317,9 +349,11 @@ }; };

- aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-pxs3-aidet"; reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; };

gic: interrupt-controller@5fe00000 { @@ -345,10 +379,14 @@ compatible = "socionext,uniphier-pxs3-reset"; #reset-cells = <1>; }; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; };

nand: nand@68000000 { - compatible = "socionext,denali-nand-v5b"; + compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; @@ -356,9 +394,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; }; }; };

-/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi"

-- 2.7.4

Masahiro Yamada

30 Aug 30 Aug

2:11 a.m.

New subject: [U-Boot] [PATCH 1/4] reset: uniphier: fix compatible for SD reset node for LD11/LD20

2017-08-29 12:20 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:

...

LD20 has SD ctrl instead of MIO ctrl. LD11 has both of them.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com

Series, applied to u-boot-uniphier.

-- Best Regards Masahiro Yamada

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Masahiro Yamada