From: Marcel Ziswiler marcel.ziswiler@toradex.com

As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com Reviewed-by: Simon Glass sjg@chromium.org

---

Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - Add Simon's reviewed-by.

arch/arm/dts/tegra124-apalis.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts index 2fc0384d14..fe08d3ea73 100644 --- a/arch/arm/dts/tegra124-apalis.dts +++ b/arch/arm/dts/tegra124-apalis.dts @@ -1683,9 +1683,9 @@ bias-pull-up; };

- gpio1_3_4_5_6 { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6"; + gpio0_1_3_4_5_6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; bias-high-impedance; }; };

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Introduce a weak tegra_pcie_board_port_reset() function by default calling the existing tegra_pcie_port_reset() function. Additionally add a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe port index if required. This allows overriding the PCIe port reset functionality from board specific code as e.g. required for Apalis T30 and Apalis TK1.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com Acked-by: Stephen Warren swarren@nvidia.com

---

Changes in v6: - Updated to latest SPDX style.

Changes in v5: - Add Stephen's acked-by.

Changes in v4: - Revert previously missed (struct tegra_pcie_port *) casts as reported by Stephen.

Changes in v3: - Stick to struct tegra_pcie_port as suggested by Stephen.

Changes in v2: - Incorporate Stephen's review feedback by introducing a tegra_pcie_port_index_of_port() function as well as a board-specific reset override function.

drivers/pci/pci_tegra.c | 17 ++++++++++++++--- include/pci_tegra.h | 10 ++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 include/pci_tegra.h

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index b325914b15..56c08585e6 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -17,6 +17,7 @@ #include <errno.h> #include <malloc.h> #include <pci.h> +#include <pci_tegra.h> #include <power-domain.h> #include <reset.h>

@@ -888,7 +889,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) return ret; }

-static void tegra_pcie_port_reset(struct tegra_pcie_port *port) +void tegra_pcie_port_reset(struct tegra_pcie_port *port) { unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); unsigned long value; @@ -905,6 +906,16 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) afi_writel(port->pcie, value, ctrl); }

+int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port) +{ + return port->index; +} + +void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port) +{ + tegra_pcie_port_reset(port); +} + static void tegra_pcie_port_enable(struct tegra_pcie_port *port) { struct tegra_pcie *pcie = port->pcie; @@ -923,7 +934,7 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)

afi_writel(pcie, value, ctrl);

- tegra_pcie_port_reset(port); + tegra_pcie_board_port_reset(port);

if (soc->force_pca_enable) { value = rp_readl(port, RP_VEND_CTL2); @@ -974,7 +985,7 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) } while (--timeout);

retry: - tegra_pcie_port_reset(port); + tegra_pcie_board_port_reset(port); } while (--retries);

return false; diff --git a/include/pci_tegra.h b/include/pci_tegra.h new file mode 100644 index 0000000000..11e92fc26d --- /dev/null +++ b/include/pci_tegra.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Toradex, Inc. + */ + +struct tegra_pcie_port; + +int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port); + +void tegra_pcie_port_reset(struct tegra_pcie_port *port);

From: Marcel Ziswiler marcel.ziswiler@toradex.com

It turns out that the current PCIe reset implementation in the PCIe board init function is not quite working reliably due to PCIe reset timing violations. Fix this by overriding the tegra_pcie_board_port_reset() function.

Also allow optionally bringing up the PCIe switch as found on the Apalis Evaluation board. Note however that the Apalis PCIe port is also left disabled in the device tree by default.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com

---

Changes in v6: None Changes in v5: - Updated copyright period to 2016-2018. - Changed error() to pr_err(). - Added a blank line after declarations as warned by patman. - Rebased and resend as series so far never got applied!

Changes in v4: None Changes in v3: - Stick to struct tegra_pcie_port as suggested by Stephen. - Introduce proper CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT Kconfig option as suggested by Stephen.

Changes in v2: None

board/toradex/apalis-tk1/Kconfig | 8 ++ board/toradex/apalis-tk1/apalis-tk1.c | 252 +++++++++++++++++++++------------- 2 files changed, 165 insertions(+), 95 deletions(-)

diff --git a/board/toradex/apalis-tk1/Kconfig b/board/toradex/apalis-tk1/Kconfig index 05407ad2d5..159b8fb19a 100644 --- a/board/toradex/apalis-tk1/Kconfig +++ b/board/toradex/apalis-tk1/Kconfig @@ -25,6 +25,14 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512"

+config APALIS_TK1_PCIE_EVALBOARD_INIT + bool "Apalis Evaluation Board PCIe Initialisation" + help + Bring up the Apalis PCIe port with the PCIe switch as found on the + Apalis Evaluation board. Note that by default the PCIe port is also + left disabled in the device tree which needs changing as well for this + to actually work. + source "board/toradex/common/Kconfig"

endif diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 6bb2acca16..d6a736d8aa 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -1,20 +1,29 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2016 Toradex, Inc. + * Copyright (c) 2016-2018 Toradex, Inc. */

#include <common.h> +#include <dm.h> #include <asm/arch-tegra/ap.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <pci_tegra.h> #include <power/as3722.h> +#include <power/pmic.h>

#include "../common/tdx-common.h" #include "pinmux-config-apalis-tk1.h"

-#define LAN_RESET_N TEGRA_GPIO(S, 2) +#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6) +#define LAN_RESET_N TEGRA_GPIO(S, 2) +#define LAN_WAKE_N TEGRA_GPIO(O, 5) +#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT +#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */ +#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4) +#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */

int arch_misc_init(void) { @@ -58,123 +67,176 @@ void pinmux_init(void) }

#ifdef CONFIG_PCI_TEGRA -int tegra_pcie_board_init(void) +/* TODO: Convert to driver model */ +static int as3722_sd_enable(struct udevice *pmic, unsigned int sd) { - /* TODO: Convert to driver model - struct udevice *pmic; int err;

- err = as3722_init(&pmic); + if (sd > 6) + return -EINVAL; + + err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); if (err) { - error("failed to initialize AS3722 PMIC: %d\n", err); + pr_err("failed to update SD control register: %d", err); return err; }

- err = as3722_sd_enable(pmic, 4); - if (err < 0) { - error("failed to enable SD4: %d\n", err); - return err; - } + return 0; +}

- err = as3722_sd_set_voltage(pmic, 4, 0x24); - if (err < 0) { - error("failed to set SD4 voltage: %d\n", err); - return err; - } +/* TODO: Convert to driver model */ +static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo) +{ + int err; + u8 ctrl_reg = AS3722_LDO_CONTROL0;

- err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH | - AS3722_GPIO_INVERT); - if (err < 0) { - error("failed to configure GPIO#1 as output: %d\n", err); - return err; - } + if (ldo > 11) + return -EINVAL;

- err = as3722_gpio_direction_output(pmic, 2, 1); - if (err < 0) { - error("failed to set GPIO#2 high: %d\n", err); - return err; + if (ldo > 7) { + ctrl_reg = AS3722_LDO_CONTROL1; + ldo -= 8; } - */

- /* Reset I210 Gigabit Ethernet Controller */ - gpio_request(LAN_RESET_N, "LAN_RESET_N"); - gpio_direction_output(LAN_RESET_N, 0); - - /* - * Make sure we don't get any back feeding from LAN_WAKE_N resp. - * DEV_OFF_N - */ - gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N"); - gpio_direction_output(TEGRA_GPIO(O, 5), 0); - - gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N"); - gpio_direction_output(TEGRA_GPIO(O, 6), 0); - - /* Make sure LDO9 and LDO10 are initially enabled @ 0V */ - /* TODO: Convert to driver model - err = as3722_ldo_enable(pmic, 9); - if (err < 0) { - error("failed to enable LDO9: %d\n", err); - return err; - } - err = as3722_ldo_enable(pmic, 10); - if (err < 0) { - error("failed to enable LDO10: %d\n", err); - return err; - } - err = as3722_ldo_set_voltage(pmic, 9, 0x80); - if (err < 0) { - error("failed to set LDO9 voltage: %d\n", err); - return err; - } - err = as3722_ldo_set_voltage(pmic, 10, 0x80); - if (err < 0) { - error("failed to set LDO10 voltage: %d\n", err); + err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo); + if (err) { + pr_err("failed to update LDO control register: %d", err); return err; } - */

- mdelay(100); - - /* Make sure controller gets enabled by disabling DEV_OFF_N */ - gpio_set_value(TEGRA_GPIO(O, 6), 1); + return 0; +}

- /* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */ - /* TODO: Convert to driver model - err = as3722_ldo_set_voltage(pmic, 9, 0xff); - if (err < 0) { - error("failed to set LDO9 voltage: %d\n", err); - return err; +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(pmic_as3722), &dev); + if (ret) { + pr_err("failed to find AS3722 PMIC: %d\n", ret); + return ret; } - err = as3722_ldo_set_voltage(pmic, 10, 0xff); - if (err < 0) { - error("failed to set LDO10 voltage: %d\n", err); - return err; + + ret = as3722_sd_enable(dev, 4); + if (ret < 0) { + pr_err("failed to enable SD4: %d\n", ret); + return ret; } - */

- mdelay(100); - gpio_set_value(LAN_RESET_N, 1); + ret = as3722_sd_set_voltage(dev, 4, 0x24); + if (ret < 0) { + pr_err("failed to set SD4 voltage: %d\n", ret); + return ret; + }

-#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT -#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */ -#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4) + gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N"); + gpio_request(LAN_RESET_N, "LAN_RESET_N"); + gpio_request(LAN_WAKE_N, "LAN_WAKE_N");

- /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation - Board */ +#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT gpio_request(PEX_PERST_N, "PEX_PERST_N"); gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL"); - gpio_direction_output(PEX_PERST_N, 0); - gpio_direction_output(RESET_MOCI_CTRL, 0); - /* Must be asserted for 100 ms after power and clocks are stable */ - mdelay(100); - gpio_set_value(PEX_PERST_N, 1); - /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until - 900 us After PEX_PERST# De-assertion */ - mdelay(1); - gpio_set_value(RESET_MOCI_CTRL, 1); -#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */ +#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */

return 0; } + +void tegra_pcie_board_port_reset(struct tegra_pcie_port *port) +{ + int index = tegra_pcie_port_index_of_port(port); + + if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(pmic_as3722), + &dev); + if (ret) { + debug("%s: Failed to find PMIC\n", __func__); + return; + } + + /* Reset I210 Gigabit Ethernet Controller */ + gpio_direction_output(LAN_RESET_N, 0); + + /* + * Make sure we don't get any back feeding from DEV_OFF_N resp. + * LAN_WAKE_N + */ + gpio_direction_output(LAN_DEV_OFF_N, 0); + gpio_direction_output(LAN_WAKE_N, 0); + + /* Make sure LDO9 and LDO10 are initially enabled @ 0V */ + ret = as3722_ldo_enable(dev, 9); + if (ret < 0) { + pr_err("failed to enable LDO9: %d\n", ret); + return; + } + ret = as3722_ldo_enable(dev, 10); + if (ret < 0) { + pr_err("failed to enable LDO10: %d\n", ret); + return; + } + ret = as3722_ldo_set_voltage(dev, 9, 0x80); + if (ret < 0) { + pr_err("failed to set LDO9 voltage: %d\n", ret); + return; + } + ret = as3722_ldo_set_voltage(dev, 10, 0x80); + if (ret < 0) { + pr_err("failed to set LDO10 voltage: %d\n", ret); + return; + } + + /* Make sure controller gets enabled by disabling DEV_OFF_N */ + gpio_set_value(LAN_DEV_OFF_N, 1); + + /* + * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype + * V1.0A and sample V1.0B and newer modules + */ + ret = as3722_ldo_set_voltage(dev, 9, 0xff); + if (ret < 0) { + pr_err("failed to set LDO9 voltage: %d\n", ret); + return; + } + ret = as3722_ldo_set_voltage(dev, 10, 0xff); + if (ret < 0) { + pr_err("failed to set LDO10 voltage: %d\n", ret); + return; + } + + /* + * Must be asserted for 100 ms after power and clocks are stable + */ + mdelay(100); + + gpio_set_value(LAN_RESET_N, 1); + } else if (index == 0) { /* Apalis PCIe */ +#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT + /* + * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis + * Evaluation Board + */ + gpio_direction_output(PEX_PERST_N, 0); + gpio_direction_output(RESET_MOCI_CTRL, 0); + + /* + * Must be asserted for 100 ms after power and clocks are stable + */ + mdelay(100); + + gpio_set_value(PEX_PERST_N, 1); + /* + * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed + * Until 900 us After PEX_PERST# De-assertion + */ + mdelay(1); + gpio_set_value(RESET_MOCI_CTRL, 1); +#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */ + } +} #endif /* CONFIG_PCI_TEGRA */