[U-Boot] [PATCH 1/2] sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- arch/arm/include/asm/arch-sunxi/prcm.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index ae3880b13b..ba4427c925 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -196,6 +196,10 @@ #define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) #define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0) +#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1) +#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2) + #ifndef __ASSEMBLY__ #include <linux/compiler.h>
@@ -233,6 +237,8 @@ struct __packed sunxi_prcm_reg { u32 dram_pwr; /* 0x180 */ u8 res12[0xc]; /* 0x184 */ u32 dram_tst; /* 0x190 */ + u8 res13[0x3c]; /* 0x194 */ + u32 prcm_sec_switch; /* 0x1d0 */ };
void prcm_apb0_enable(u32 flags);
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM.
Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure.
Add code to switch the PRCM to non-secure.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- arch/arm/mach-sunxi/clock_sun6i.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index ec5b026ef5..870ff5b1e0 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -66,11 +66,17 @@ void clock_init_sec(void) #ifdef CONFIG_MACH_SUNXI_H3_H5 struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
setbits_le32(&ccm->ccu_sec_switch, CCM_SEC_SWITCH_MBUS_NONSEC | CCM_SEC_SWITCH_BUS_NONSEC | CCM_SEC_SWITCH_PLL_NONSEC); + setbits_le32(&prcm->prcm_sec_switch, + PRCM_SEC_SWITCH_APB0_CLK_NONSEC | + PRCM_SEC_SWITCH_PLL_CFG_NONSEC | + PRCM_SEC_SWITCH_PWR_GATE_NONSEC); #endif }
在 2017-07-20 14:00，Icenowy Zheng 写道：
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM.
Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure.
Add code to switch the PRCM to non-secure.
Ping.
Maxime and Jagan, can you merge this patchset?
This is necessary for R_CCU to work properly on H3.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/mach-sunxi/clock_sun6i.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index ec5b026ef5..870ff5b1e0 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -66,11 +66,17 @@ void clock_init_sec(void) #ifdef CONFIG_MACH_SUNXI_H3_H5 struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;setbits_le32(&ccm->ccu_sec_switch, CCM_SEC_SWITCH_MBUS_NONSEC | CCM_SEC_SWITCH_BUS_NONSEC | CCM_SEC_SWITCH_PLL_NONSEC);
setbits_le32(&prcm->prcm_sec_switch,
PRCM_SEC_SWITCH_APB0_CLK_NONSEC |PRCM_SEC_SWITCH_PLL_CFG_NONSEC |PRCM_SEC_SWITCH_PWR_GATE_NONSEC);#endif }
On Wed, Jul 26, 2017 at 07:55:24PM +0800, icenowy@aosc.io wrote:
在 2017-07-20 14:00，Icenowy Zheng 写道：
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM.
Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure.
Add code to switch the PRCM to non-secure.
Ping.
Maxime and Jagan, can you merge this patchset?
This is necessary for R_CCU to work properly on H3.
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Maxime
On Thu, Jul 27, 2017 at 3:31 AM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Wed, Jul 26, 2017 at 07:55:24PM +0800, icenowy@aosc.io wrote:
在 2017-07-20 14:00，Icenowy Zheng 写道：
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM.
Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure.
Add code to switch the PRCM to non-secure.
Ping.
Maxime and Jagan, can you merge this patchset?
This is necessary for R_CCU to work properly on H3.
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Tested-by: Chen-Yu Tsai wens@csie.org
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng icenowy@aosc.io wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Could you provide a reference as to where or how you found out about this?
Thanks ChenYu
在 2017-08-08 12:13，Chen-Yu Tsai 写道：
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng icenowy@aosc.io wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Could you provide a reference as to where or how you found out about this?
https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/p...
Thanks ChenYu
On Tue, Aug 8, 2017 at 2:46 PM, icenowy@aosc.io wrote:
在 2017-08-08 12:13，Chen-Yu Tsai 写道：
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng icenowy@aosc.io wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Could you provide a reference as to where or how you found out about this?
https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/p...
I assume you've mapped out what each bit means by testing it?
Tested-by: Chen-Yu Tsai wens@csie.org
在 2017-08-09 11:46，Chen-Yu Tsai 写道：
On Tue, Aug 8, 2017 at 2:46 PM, icenowy@aosc.io wrote:
在 2017-08-08 12:13，Chen-Yu Tsai 写道：
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng icenowy@aosc.io wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Could you provide a reference as to where or how you found out about this?
https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/p...
I assume you've mapped out what each bit means by testing it?
Yes.
Toggling bit 0 will make at least 0x0 (CPUS_CFG_REG) inaccessible. Toggling bit 1 will make at least 0x40 and 0x44 (PLL_CTRL_REG{0,1}) inaccessible. Toggling bit 2 will make at least 0x120 (VDD_SYS_PWR_RST) inaccessible.
(The register names are from http://linux-sunxi.org/PRCM )
Tested-by: Chen-Yu Tsai wens@csie.org
On Thu, Jul 20, 2017 at 11:30 AM, Icenowy Zheng icenowy@aosc.io wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Applied both in u-boot-sunxi/master
thanks!
participants (5)
-
Chen-Yu Tsai -
Icenowy Zheng -
icenowy＠aosc.io
-
Jagan Teki -
Maxime Ripard