[U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward...
Patch work: http://patchwork.ozlabs.org/patch/343084/
Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region
arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++-- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-)
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency.
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency.
Can you give an example?
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init)
- we do this here instead.
- But first check if we have the generic timer.
*/ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ
Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ?
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
- ldreq r1, =CONFIG_SYS_CLK_FREQ
- ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif
Diana
Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency.
Can you give an example?
In LS1021A-QDS/TWR, the CONFIG_SYS_CLK_FREQ is 100Mhz and the ARCH timer's Frequency will be 12.5Mhz...
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S
b/arch/arm/cpu/armv7/nonsec_virt.S
index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init)
- we do this here instead.
- But first check if we have the generic timer.
*/ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ
Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ?
I hadn't found any board is using this in the upstreamed tree, or may I miss something ?
If there exist some, and I will redefined it for them here.
In ARMv7, what could I find is that only vexpress_ca15_tc2 board has enabled the CONFIG_ARMV7_VIRT without defining it.
Thanks,
BRs Xiubo
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
- ldreq r1, =CONFIG_SYS_CLK_FREQ
- ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif
Diana
On 07/04/2014 04:43 AM, Xiubo Li-B47053 wrote:
Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency.
Can you give an example?
In LS1021A-QDS/TWR, the CONFIG_SYS_CLK_FREQ is 100Mhz and the ARCH timer's Frequency will be 12.5Mhz...
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S
b/arch/arm/cpu/armv7/nonsec_virt.S
index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ
Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ?
I hadn't found any board is using this in the upstreamed tree, or may I miss something ?
If there exist some, and I will redefined it for them here.
In ARMv7, what could I find is that only vexpress_ca15_tc2 board has enabled the CONFIG_ARMV7_VIRT without defining it.
Yes, this board defines CONFIG_ARMV7_VIRT. In order for this board to work after your changes you need to define CONFIG_TIMER_CLK_FREQ.
Diana
For some SoCs, the pen address may has different endianness with the CPUs, so this need the byte revertion for it,
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index e9766c0..c334a15 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -181,6 +181,9 @@ ENTRY(smp_waitloop) wfi ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address ldr r1, [r1] +#ifdef CONFIG_SOC_BIG_ENDIAN + rev r1, r1 +#endif cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop @ again (due to a spurious wakeup) mov pc, r1
To enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com --- arch/arm/cpu/armv7/ls102xa/cpu.c | 12 ++++++++++++ include/configs/ls1021aqds.h | 9 +++++++++ include/configs/ls1021atwr.h | 9 +++++++++ 3 files changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index f9046c6..2268f15 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -101,3 +101,15 @@ int cpu_eth_init(bd_t *bis)
return 0; } + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Setting the address at which secondary cores start from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + /* After setting the secondary cores start address, just release + * them to boot. + */ + out_be32(CONFIG_DCFG_CCSR_SCRATCHRW1, addr); + out_be32(CONFIG_DCFG_CCSR_BRR, 0x2); +} +#endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 +#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000 +#define CONFIG_TIMER_CLK_FREQ 125000000 + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a8dc56e..235a862 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 +#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000 +#define CONFIG_TIMER_CLK_FREQ 125000000 + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128
On 07/03/2014 12:51 PM, Xiubo Li wrote:
To enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com
arch/arm/cpu/armv7/ls102xa/cpu.c | 12 ++++++++++++ include/configs/ls1021aqds.h | 9 +++++++++ include/configs/ls1021atwr.h | 9 +++++++++ 3 files changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index f9046c6..2268f15 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -101,3 +101,15 @@ int cpu_eth_init(bd_t *bis)
return 0; }
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Setting the address at which secondary cores start from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{
- /* After setting the secondary cores start address, just release
* them to boot.*/- out_be32(CONFIG_DCFG_CCSR_SCRATCHRW1, addr);
- out_be32(CONFIG_DCFG_CCSR_BRR, 0x2);
+} +#endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
Why are you hardcoding the register addresses in this file? I saw that all registers are defined in: arch/arm/include/asm/arch-ls102xa/config.h. Why are these special?
+#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000
Why do you need the GIC base address? Can't this be read from CBAR?
+#define CONFIG_TIMER_CLK_FREQ 125000000
- #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a8dc56e..235a862 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 +#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000 +#define CONFIG_TIMER_CLK_FREQ 125000000
- #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
Why are you hardcoding the register addresses in this file? I saw that all registers are defined in: arch/arm/include/asm/arch-ls102xa/config.h. Why are these special?
No special, and I'll follow your advice.
+#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000
Why do you need the GIC base address? Can't this be read from CBAR?
I'm not very sure, I have tried, but failed, I will do some research later.
Thanks,
BRs Xiubo
+#define CONFIG_TIMER_CLK_FREQ 125000000
- #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a8dc56e..235a862 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 +#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000 +#define CONFIG_TIMER_CLK_FREQ 125000000
- #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128
On 07/04/2014 04:48 AM, Xiubo Li-B47053 wrote:
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
Why are you hardcoding the register addresses in this file? I saw that all registers are defined in: arch/arm/include/asm/arch-ls102xa/config.h. Why are these special?
No special, and I'll follow your advice.
+#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000
Why do you need the GIC base address? Can't this be read from CBAR?
I'm not very sure, I have tried, but failed, I will do some research later.
What is not working? Is the address returned by CBAR wrong?
Diana
+#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
Why are you hardcoding the register addresses in this file? I saw that all registers are defined in: arch/arm/include/asm/arch-ls102xa/config.h. Why are these special?
No special, and I'll follow your advice.
+#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000
Why do you need the GIC base address? Can't this be read from CBAR?
I'm not very sure, I have tried, but failed, I will do some research later.
What is not working? Is the address returned by CBAR wrong?
It works now using the CBAR...
Thanks,
BRs Xiubo
Diana
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++-- 3 files changed, 298 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 192d389..b959bf5 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -34,14 +34,98 @@ #define FSL_LS102xA_DEVDISR3_PCIE1 0x80000000 #define FSL_LS102xA_DEVDISR3_PCIE2 0x40000000
-/* CSU CSL2 register offset */ -#define CSU_CSL2_IFC_REG_OFFSET 0x4 -/* Mask of Non secure read/write access in CSU_CL registers */ -#define CSU_CSL2x_NS_SUP_WRITE_ACCESS 0x00000080 -#define CSU_CSL2x_NS_USER_WRITE_ACCESS 0x00000040 -#define CSU_CSL2x_NS_SUP_READ_ACCESS 0x00000008 -#define CSU_CSL2x_NS_USER_READ_ACCESS 0x00000004 +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, +};
+enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB3, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI2 = 40, + CSU_CSLX_DSPI1, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_2D_ACE, + CSU_CSLX_IFC, + CSU_CSLX_I2C1, + CSU_CSLX_USB2, + CSU_CSLX_I2C3, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_RESERVED0, + CSU_CSLX_ETSEC1, + CSU_CSLX_SEC5_5, + CSU_CSLX_ETSEC3, + CSU_CSLX_ETSEC2, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_ASRC, + CSU_CSLX_SPDIF, + CSU_CSLX_FLEXCAN2, + CSU_CSLX_FLEXCAN1, + CSU_CSLX_FLEXCAN4 = 80, + CSU_CSLX_FLEXCAN3, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_COP_DCSR, + CSU_CSLX_EPU, + CSU_CSLX_GDI, + CSU_CSLX_DDI, + CSU_CSLX_RESERVED1, + CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_RESERVED2, +}; /* * Define default values for some CCSR macros to make header files cleaner* * diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index fe00421..7444e06 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -377,15 +377,111 @@ int board_init(void) return 0; }
+struct csu_ns_dev { + unsigned long ind; + uint32_t val; +};
-void enable_ifc_ns_read_access(void) +struct csu_ns_dev ns_dev[] = { - uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET; - uint32_t reg; + CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW, + CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW, + CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW, + CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R, + CSU_CSLX_OCRAM, CSU_NS_SUP_RW, + CSU_CSLX_GIC, CSU_NS_SUP_RW, + CSU_CSLX_PCIE1, CSU_NS_SUP_RW, + CSU_CSLX_OCRAM2, CSU_NS_SUP_RW, + CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW, + CSU_CSLX_PCIE2, CSU_NS_SUP_RW, + CSU_CSLX_SATA, CSU_NS_SUP_RW, + CSU_CSLX_USB3, CSU_NS_SUP_RW, + CSU_CSLX_SERDES, CSU_NS_SUP_RW, + CSU_CSLX_QDMA, CSU_NS_SUP_RW, + CSU_CSLX_LPUART2, CSU_NS_SUP_RW, + CSU_CSLX_LPUART1, CSU_NS_SUP_RW, + CSU_CSLX_LPUART4, CSU_NS_SUP_RW, + CSU_CSLX_LPUART3, CSU_NS_SUP_RW, + CSU_CSLX_LPUART6, CSU_NS_SUP_RW, + CSU_CSLX_LPUART5, CSU_NS_SUP_RW, + CSU_CSLX_DSPI2, CSU_NS_SUP_RW, + CSU_CSLX_DSPI1, CSU_NS_SUP_RW, + CSU_CSLX_QSPI, CSU_NS_SUP_RW, + CSU_CSLX_ESDHC, CSU_NS_SUP_RW, + CSU_CSLX_2D_ACE, CSU_NS_SUP_RW, + CSU_CSLX_IFC, CSU_NS_SUP_RW, + CSU_CSLX_I2C1, CSU_NS_SUP_RW, + CSU_CSLX_USB2, CSU_NS_SUP_RW, + CSU_CSLX_I2C3, CSU_NS_SUP_RW, + CSU_CSLX_I2C2, CSU_NS_SUP_RW, + CSU_CSLX_DUART2, CSU_NS_SUP_RW, + CSU_CSLX_DUART1, CSU_NS_SUP_RW, + CSU_CSLX_WDT2, CSU_NS_SUP_RW, + CSU_CSLX_WDT1, CSU_NS_SUP_RW, + CSU_CSLX_EDMA, CSU_NS_SUP_RW, + CSU_CSLX_SYS_CNT, CSU_NS_SUP_RW, + CSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW, + CSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW, + CSU_CSLX_DDR, CSU_NS_SUP_RW, + CSU_CSLX_QUICC, CSU_NS_SUP_RW, + CSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW, + CSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW, + CSU_CSLX_SFP, CSU_NS_SUP_RW, + CSU_CSLX_TMU, CSU_NS_SUP_RW, + CSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW, + CSU_CSLX_RESERVED0, CSU_NS_SUP_RW, + CSU_CSLX_ETSEC1, CSU_NS_SUP_RW, + CSU_CSLX_SEC5_5, CSU_NS_SUP_RW, + CSU_CSLX_ETSEC3, CSU_NS_SUP_RW, + CSU_CSLX_ETSEC2, CSU_NS_SUP_RW, + CSU_CSLX_GPIO2, CSU_NS_SUP_RW, + CSU_CSLX_GPIO1, CSU_NS_SUP_RW, + CSU_CSLX_GPIO4, CSU_NS_SUP_RW, + CSU_CSLX_GPIO3, CSU_NS_SUP_RW, + CSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW, + CSU_CSLX_CSU, CSU_NS_SUP_RW, + CSU_CSLX_ASRC, CSU_NS_SUP_RW, + CSU_CSLX_SPDIF, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW, + CSU_CSLX_SAI2, CSU_NS_SUP_RW, + CSU_CSLX_SAI1, CSU_NS_SUP_RW, + CSU_CSLX_SAI4, CSU_NS_SUP_RW, + CSU_CSLX_SAI3, CSU_NS_SUP_RW, + CSU_CSLX_FTM2, CSU_NS_SUP_RW, + CSU_CSLX_FTM1, CSU_NS_SUP_RW, + CSU_CSLX_FTM4, CSU_NS_SUP_RW, + CSU_CSLX_FTM3, CSU_NS_SUP_RW, + CSU_CSLX_FTM6, CSU_NS_SUP_RW, + CSU_CSLX_FTM5, CSU_NS_SUP_RW, + CSU_CSLX_FTM8, CSU_NS_SUP_RW, + CSU_CSLX_FTM7, CSU_NS_SUP_RW, + CSU_CSLX_COP_DCSR, CSU_NS_SUP_RW, + CSU_CSLX_EPU, CSU_NS_SUP_RW, + CSU_CSLX_GDI, CSU_NS_SUP_RW, + CSU_CSLX_DDI, CSU_NS_SUP_RW, + CSU_CSLX_RESERVED1, CSU_NS_SUP_RW, + CSU_CSLX_USB3_PHY, CSU_NS_SUP_RW, + CSU_CSLX_RESERVED2, CSU_NS_SUP_RW, +};
- reg = in_be32(csu_csl2); - out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS | - CSU_CSL2x_NS_USER_READ_ACCESS); +void enable_devices_ns_access(void) +{ + uint32_t *csu_csl; + uint32_t reg; + int i; + + for (i = 0; i < ARRAY_SIZE(ns_dev); i++) { + csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4; + reg = in_be32(csu_csl); + if (ns_dev[i].ind % 2 == 0) + reg |= ns_dev[i].val << 16; + else + reg |= ns_dev[i].val; + out_be32(csu_csl, reg); + } }
int board_late_init(void) @@ -403,7 +499,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR); scsi_scan(1); - enable_ifc_ns_read_access(); + enable_devices_ns_access(); return 0; }
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d57fa77..f75b779 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -458,14 +458,111 @@ int board_init(void) return 0; }
-void enable_ifc_ns_read_access(void) +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +struct csu_ns_dev ns_dev[] = { - uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET; - uint32_t reg; + CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW, + CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW, + CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW, + CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R, + CSU_CSLX_OCRAM, CSU_NS_SUP_RW, + CSU_CSLX_GIC, CSU_NS_SUP_RW, + CSU_CSLX_PCIE1, CSU_NS_SUP_RW, + CSU_CSLX_OCRAM2, CSU_NS_SUP_RW, + CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW, + CSU_CSLX_PCIE2, CSU_NS_SUP_RW, + CSU_CSLX_SATA, CSU_NS_SUP_RW, + CSU_CSLX_USB3, CSU_NS_SUP_RW, + CSU_CSLX_SERDES, CSU_NS_SUP_RW, + CSU_CSLX_QDMA, CSU_NS_SUP_RW, + CSU_CSLX_LPUART2, CSU_NS_SUP_RW, + CSU_CSLX_LPUART1, CSU_NS_SUP_RW, + CSU_CSLX_LPUART4, CSU_NS_SUP_RW, + CSU_CSLX_LPUART3, CSU_NS_SUP_RW, + CSU_CSLX_LPUART6, CSU_NS_SUP_RW, + CSU_CSLX_LPUART5, CSU_NS_SUP_RW, + CSU_CSLX_DSPI2, CSU_NS_SUP_RW, + CSU_CSLX_DSPI1, CSU_NS_SUP_RW, + CSU_CSLX_QSPI, CSU_NS_SUP_RW, + CSU_CSLX_ESDHC, CSU_NS_SUP_RW, + CSU_CSLX_2D_ACE, CSU_NS_SUP_RW, + CSU_CSLX_IFC, CSU_NS_SUP_RW, + CSU_CSLX_I2C1, CSU_NS_SUP_RW, + CSU_CSLX_USB2, CSU_NS_SUP_RW, + CSU_CSLX_I2C3, CSU_NS_SUP_RW, + CSU_CSLX_I2C2, CSU_NS_SUP_RW, + CSU_CSLX_DUART2, CSU_NS_SUP_RW, + CSU_CSLX_DUART1, CSU_NS_SUP_RW, + CSU_CSLX_WDT2, CSU_NS_SUP_RW, + CSU_CSLX_WDT1, CSU_NS_SUP_RW, + CSU_CSLX_EDMA, CSU_NS_SUP_RW, + CSU_CSLX_SYS_CNT, CSU_NS_SUP_RW, + CSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW, + CSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW, + CSU_CSLX_DDR, CSU_NS_SUP_RW, + CSU_CSLX_QUICC, CSU_NS_SUP_RW, + CSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW, + CSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW, + CSU_CSLX_SFP, CSU_NS_SUP_RW, + CSU_CSLX_TMU, CSU_NS_SUP_RW, + CSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW, + CSU_CSLX_RESERVED0, CSU_NS_SUP_RW, + CSU_CSLX_ETSEC1, CSU_NS_SUP_RW, + CSU_CSLX_SEC5_5, CSU_NS_SUP_RW, + CSU_CSLX_ETSEC3, CSU_NS_SUP_RW, + CSU_CSLX_ETSEC2, CSU_NS_SUP_RW, + CSU_CSLX_GPIO2, CSU_NS_SUP_RW, + CSU_CSLX_GPIO1, CSU_NS_SUP_RW, + CSU_CSLX_GPIO4, CSU_NS_SUP_RW, + CSU_CSLX_GPIO3, CSU_NS_SUP_RW, + CSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW, + CSU_CSLX_CSU, CSU_NS_SUP_RW, + CSU_CSLX_ASRC, CSU_NS_SUP_RW, + CSU_CSLX_SPDIF, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW, + CSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW, + CSU_CSLX_SAI2, CSU_NS_SUP_RW, + CSU_CSLX_SAI1, CSU_NS_SUP_RW, + CSU_CSLX_SAI4, CSU_NS_SUP_RW, + CSU_CSLX_SAI3, CSU_NS_SUP_RW, + CSU_CSLX_FTM2, CSU_NS_SUP_RW, + CSU_CSLX_FTM1, CSU_NS_SUP_RW, + CSU_CSLX_FTM4, CSU_NS_SUP_RW, + CSU_CSLX_FTM3, CSU_NS_SUP_RW, + CSU_CSLX_FTM6, CSU_NS_SUP_RW, + CSU_CSLX_FTM5, CSU_NS_SUP_RW, + CSU_CSLX_FTM8, CSU_NS_SUP_RW, + CSU_CSLX_FTM7, CSU_NS_SUP_RW, + CSU_CSLX_COP_DCSR, CSU_NS_SUP_RW, + CSU_CSLX_EPU, CSU_NS_SUP_RW, + CSU_CSLX_GDI, CSU_NS_SUP_RW, + CSU_CSLX_DDI, CSU_NS_SUP_RW, + CSU_CSLX_RESERVED1, CSU_NS_SUP_RW, + CSU_CSLX_USB3_PHY, CSU_NS_SUP_RW, + CSU_CSLX_RESERVED2, CSU_NS_SUP_RW, +};
- reg = in_be32(csu_csl2); - out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS | - CSU_CSL2x_NS_USER_READ_ACCESS); +void enable_devices_ns_access(void) +{ + uint32_t *csu_csl; + uint32_t reg; + int i; + + for (i = 0; i < ARRAY_SIZE(ns_dev); i++) { + csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4; + reg = in_be32(csu_csl); + if (ns_dev[i].ind % 2 == 0) + reg |= ns_dev[i].val << 16; + else + reg |= ns_dev[i].val; + out_be32(csu_csl, reg); + } }
int board_late_init(void) @@ -483,7 +580,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR); scsi_scan(1); - enable_ifc_ns_read_access(); + enable_devices_ns_access(); return 0; }
On 07/03/2014 12:51 PM, Xiubo Li wrote:
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++-- 3 files changed, 298 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 192d389..b959bf5 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -34,14 +34,98 @@ #define FSL_LS102xA_DEVDISR3_PCIE1 0x80000000 #define FSL_LS102xA_DEVDISR3_PCIE2 0x40000000
-/* CSU CSL2 register offset */ -#define CSU_CSL2_IFC_REG_OFFSET 0x4 -/* Mask of Non secure read/write access in CSU_CL registers */ -#define CSU_CSL2x_NS_SUP_WRITE_ACCESS 0x00000080 -#define CSU_CSL2x_NS_USER_WRITE_ACCESS 0x00000040 -#define CSU_CSL2x_NS_SUP_READ_ACCESS 0x00000008 -#define CSU_CSL2x_NS_USER_READ_ACCESS 0x00000004 +enum csu_cslx_access {
- CSU_NS_SUP_R = 0x08,
- CSU_NS_SUP_W = 0x80,
- CSU_NS_SUP_RW = 0x88,
- CSU_NS_USER_R = 0x04,
- CSU_NS_USER_W = 0x40,
- CSU_NS_USER_RW = 0x44,
+};
+enum csu_cslx_ind {
- CSU_CSLX_PCIE2_IO = 0,
- CSU_CSLX_PCIE1_IO,
- CSU_CSLX_MG2TPR_IP,
- CSU_CSLX_IFC_MEM,
- CSU_CSLX_OCRAM,
- CSU_CSLX_GIC,
- CSU_CSLX_PCIE1,
- CSU_CSLX_OCRAM2,
- CSU_CSLX_QSPI_MEM,
- CSU_CSLX_PCIE2,
- CSU_CSLX_SATA,
- CSU_CSLX_USB3,
- CSU_CSLX_SERDES = 32,
- CSU_CSLX_QDMA,
- CSU_CSLX_LPUART2,
- CSU_CSLX_LPUART1,
- CSU_CSLX_LPUART4,
- CSU_CSLX_LPUART3,
- CSU_CSLX_LPUART6,
- CSU_CSLX_LPUART5,
- CSU_CSLX_DSPI2 = 40,
- CSU_CSLX_DSPI1,
- CSU_CSLX_QSPI,
- CSU_CSLX_ESDHC,
- CSU_CSLX_2D_ACE,
- CSU_CSLX_IFC,
- CSU_CSLX_I2C1,
- CSU_CSLX_USB2,
- CSU_CSLX_I2C3,
- CSU_CSLX_I2C2,
- CSU_CSLX_DUART2 = 50,
- CSU_CSLX_DUART1,
- CSU_CSLX_WDT2,
- CSU_CSLX_WDT1,
- CSU_CSLX_EDMA,
- CSU_CSLX_SYS_CNT,
- CSU_CSLX_DMA_MUX2,
- CSU_CSLX_DMA_MUX1,
- CSU_CSLX_DDR,
- CSU_CSLX_QUICC,
- CSU_CSLX_DCFG_CCU_RCPM = 60,
- CSU_CSLX_SECURE_BOOTROM,
- CSU_CSLX_SFP,
- CSU_CSLX_TMU,
- CSU_CSLX_SECURE_MONITOR,
- CSU_CSLX_RESERVED0,
- CSU_CSLX_ETSEC1,
- CSU_CSLX_SEC5_5,
- CSU_CSLX_ETSEC3,
- CSU_CSLX_ETSEC2,
- CSU_CSLX_GPIO2 = 70,
- CSU_CSLX_GPIO1,
- CSU_CSLX_GPIO4,
- CSU_CSLX_GPIO3,
- CSU_CSLX_PLATFORM_CONT,
- CSU_CSLX_CSU,
- CSU_CSLX_ASRC,
- CSU_CSLX_SPDIF,
- CSU_CSLX_FLEXCAN2,
- CSU_CSLX_FLEXCAN1,
- CSU_CSLX_FLEXCAN4 = 80,
- CSU_CSLX_FLEXCAN3,
- CSU_CSLX_SAI2,
- CSU_CSLX_SAI1,
- CSU_CSLX_SAI4,
- CSU_CSLX_SAI3,
- CSU_CSLX_FTM2,
- CSU_CSLX_FTM1,
- CSU_CSLX_FTM4,
- CSU_CSLX_FTM3,
- CSU_CSLX_FTM6 = 90,
- CSU_CSLX_FTM5,
- CSU_CSLX_FTM8,
- CSU_CSLX_FTM7,
- CSU_CSLX_COP_DCSR,
- CSU_CSLX_EPU,
- CSU_CSLX_GDI,
- CSU_CSLX_DDI,
- CSU_CSLX_RESERVED1,
- CSU_CSLX_USB3_PHY = 117,
- CSU_CSLX_RESERVED2,
+}; /*
- Define default values for some CCSR macros to make header files cleaner*
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index fe00421..7444e06 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -377,15 +377,111 @@ int board_init(void) return 0; }
+struct csu_ns_dev {
- unsigned long ind;
- uint32_t val;
+};
-void enable_ifc_ns_read_access(void) +struct csu_ns_dev ns_dev[] = {
- uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET;
- uint32_t reg;
- CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW,
- CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW,
- CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW,
- CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R,
- CSU_CSLX_OCRAM, CSU_NS_SUP_RW,
- CSU_CSLX_GIC, CSU_NS_SUP_RW,
- CSU_CSLX_PCIE1, CSU_NS_SUP_RW,
- CSU_CSLX_OCRAM2, CSU_NS_SUP_RW,
- CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW,
- CSU_CSLX_PCIE2, CSU_NS_SUP_RW,
- CSU_CSLX_SATA, CSU_NS_SUP_RW,
- CSU_CSLX_USB3, CSU_NS_SUP_RW,
- CSU_CSLX_SERDES, CSU_NS_SUP_RW,
- CSU_CSLX_QDMA, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART2, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART1, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART4, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART3, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART6, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART5, CSU_NS_SUP_RW,
- CSU_CSLX_DSPI2, CSU_NS_SUP_RW,
- CSU_CSLX_DSPI1, CSU_NS_SUP_RW,
- CSU_CSLX_QSPI, CSU_NS_SUP_RW,
- CSU_CSLX_ESDHC, CSU_NS_SUP_RW,
- CSU_CSLX_2D_ACE, CSU_NS_SUP_RW,
- CSU_CSLX_IFC, CSU_NS_SUP_RW,
- CSU_CSLX_I2C1, CSU_NS_SUP_RW,
- CSU_CSLX_USB2, CSU_NS_SUP_RW,
- CSU_CSLX_I2C3, CSU_NS_SUP_RW,
- CSU_CSLX_I2C2, CSU_NS_SUP_RW,
- CSU_CSLX_DUART2, CSU_NS_SUP_RW,
- CSU_CSLX_DUART1, CSU_NS_SUP_RW,
- CSU_CSLX_WDT2, CSU_NS_SUP_RW,
- CSU_CSLX_WDT1, CSU_NS_SUP_RW,
- CSU_CSLX_EDMA, CSU_NS_SUP_RW,
- CSU_CSLX_SYS_CNT, CSU_NS_SUP_RW,
- CSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW,
- CSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW,
- CSU_CSLX_DDR, CSU_NS_SUP_RW,
- CSU_CSLX_QUICC, CSU_NS_SUP_RW,
- CSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW,
- CSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW,
- CSU_CSLX_SFP, CSU_NS_SUP_RW,
- CSU_CSLX_TMU, CSU_NS_SUP_RW,
- CSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW,
- CSU_CSLX_RESERVED0, CSU_NS_SUP_RW,
- CSU_CSLX_ETSEC1, CSU_NS_SUP_RW,
- CSU_CSLX_SEC5_5, CSU_NS_SUP_RW,
- CSU_CSLX_ETSEC3, CSU_NS_SUP_RW,
- CSU_CSLX_ETSEC2, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO2, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO1, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO4, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO3, CSU_NS_SUP_RW,
- CSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW,
- CSU_CSLX_CSU, CSU_NS_SUP_RW,
- CSU_CSLX_ASRC, CSU_NS_SUP_RW,
- CSU_CSLX_SPDIF, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW,
- CSU_CSLX_SAI2, CSU_NS_SUP_RW,
- CSU_CSLX_SAI1, CSU_NS_SUP_RW,
- CSU_CSLX_SAI4, CSU_NS_SUP_RW,
- CSU_CSLX_SAI3, CSU_NS_SUP_RW,
- CSU_CSLX_FTM2, CSU_NS_SUP_RW,
- CSU_CSLX_FTM1, CSU_NS_SUP_RW,
- CSU_CSLX_FTM4, CSU_NS_SUP_RW,
- CSU_CSLX_FTM3, CSU_NS_SUP_RW,
- CSU_CSLX_FTM6, CSU_NS_SUP_RW,
- CSU_CSLX_FTM5, CSU_NS_SUP_RW,
- CSU_CSLX_FTM8, CSU_NS_SUP_RW,
- CSU_CSLX_FTM7, CSU_NS_SUP_RW,
- CSU_CSLX_COP_DCSR, CSU_NS_SUP_RW,
- CSU_CSLX_EPU, CSU_NS_SUP_RW,
- CSU_CSLX_GDI, CSU_NS_SUP_RW,
- CSU_CSLX_DDI, CSU_NS_SUP_RW,
- CSU_CSLX_RESERVED1, CSU_NS_SUP_RW,
- CSU_CSLX_USB3_PHY, CSU_NS_SUP_RW,
- CSU_CSLX_RESERVED2, CSU_NS_SUP_RW,
+};
- reg = in_be32(csu_csl2);
- out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |
CSU_CSL2x_NS_USER_READ_ACCESS);+void enable_devices_ns_access(void) +{
uint32_t *csu_csl;
uint32_t reg;
int i;
for (i = 0; i < ARRAY_SIZE(ns_dev); i++) {
csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4;reg = in_be32(csu_csl);if (ns_dev[i].ind % 2 == 0)reg |= ns_dev[i].val << 16;elsereg |= ns_dev[i].val;out_be32(csu_csl, reg);} }
int board_late_init(void)
@@ -403,7 +499,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR); scsi_scan(1);
- enable_ifc_ns_read_access();
- enable_devices_ns_access(); return 0; }
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d57fa77..f75b779 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -458,14 +458,111 @@ int board_init(void) return 0; }
-void enable_ifc_ns_read_access(void) +struct csu_ns_dev {
- unsigned long ind;
- uint32_t val;
+};
+struct csu_ns_dev ns_dev[] = {
- uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET;
- uint32_t reg;
- CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW,
- CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW,
- CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW,
- CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R,
- CSU_CSLX_OCRAM, CSU_NS_SUP_RW,
- CSU_CSLX_GIC, CSU_NS_SUP_RW,
- CSU_CSLX_PCIE1, CSU_NS_SUP_RW,
- CSU_CSLX_OCRAM2, CSU_NS_SUP_RW,
- CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW,
- CSU_CSLX_PCIE2, CSU_NS_SUP_RW,
- CSU_CSLX_SATA, CSU_NS_SUP_RW,
- CSU_CSLX_USB3, CSU_NS_SUP_RW,
- CSU_CSLX_SERDES, CSU_NS_SUP_RW,
- CSU_CSLX_QDMA, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART2, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART1, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART4, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART3, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART6, CSU_NS_SUP_RW,
- CSU_CSLX_LPUART5, CSU_NS_SUP_RW,
- CSU_CSLX_DSPI2, CSU_NS_SUP_RW,
- CSU_CSLX_DSPI1, CSU_NS_SUP_RW,
- CSU_CSLX_QSPI, CSU_NS_SUP_RW,
- CSU_CSLX_ESDHC, CSU_NS_SUP_RW,
- CSU_CSLX_2D_ACE, CSU_NS_SUP_RW,
- CSU_CSLX_IFC, CSU_NS_SUP_RW,
- CSU_CSLX_I2C1, CSU_NS_SUP_RW,
- CSU_CSLX_USB2, CSU_NS_SUP_RW,
- CSU_CSLX_I2C3, CSU_NS_SUP_RW,
- CSU_CSLX_I2C2, CSU_NS_SUP_RW,
- CSU_CSLX_DUART2, CSU_NS_SUP_RW,
- CSU_CSLX_DUART1, CSU_NS_SUP_RW,
- CSU_CSLX_WDT2, CSU_NS_SUP_RW,
- CSU_CSLX_WDT1, CSU_NS_SUP_RW,
- CSU_CSLX_EDMA, CSU_NS_SUP_RW,
- CSU_CSLX_SYS_CNT, CSU_NS_SUP_RW,
- CSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW,
- CSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW,
- CSU_CSLX_DDR, CSU_NS_SUP_RW,
- CSU_CSLX_QUICC, CSU_NS_SUP_RW,
- CSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW,
- CSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW,
- CSU_CSLX_SFP, CSU_NS_SUP_RW,
- CSU_CSLX_TMU, CSU_NS_SUP_RW,
- CSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW,
- CSU_CSLX_RESERVED0, CSU_NS_SUP_RW,
- CSU_CSLX_ETSEC1, CSU_NS_SUP_RW,
- CSU_CSLX_SEC5_5, CSU_NS_SUP_RW,
- CSU_CSLX_ETSEC3, CSU_NS_SUP_RW,
- CSU_CSLX_ETSEC2, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO2, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO1, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO4, CSU_NS_SUP_RW,
- CSU_CSLX_GPIO3, CSU_NS_SUP_RW,
- CSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW,
- CSU_CSLX_CSU, CSU_NS_SUP_RW,
- CSU_CSLX_ASRC, CSU_NS_SUP_RW,
- CSU_CSLX_SPDIF, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW,
- CSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW,
- CSU_CSLX_SAI2, CSU_NS_SUP_RW,
- CSU_CSLX_SAI1, CSU_NS_SUP_RW,
- CSU_CSLX_SAI4, CSU_NS_SUP_RW,
- CSU_CSLX_SAI3, CSU_NS_SUP_RW,
- CSU_CSLX_FTM2, CSU_NS_SUP_RW,
- CSU_CSLX_FTM1, CSU_NS_SUP_RW,
- CSU_CSLX_FTM4, CSU_NS_SUP_RW,
- CSU_CSLX_FTM3, CSU_NS_SUP_RW,
- CSU_CSLX_FTM6, CSU_NS_SUP_RW,
- CSU_CSLX_FTM5, CSU_NS_SUP_RW,
- CSU_CSLX_FTM8, CSU_NS_SUP_RW,
- CSU_CSLX_FTM7, CSU_NS_SUP_RW,
- CSU_CSLX_COP_DCSR, CSU_NS_SUP_RW,
- CSU_CSLX_EPU, CSU_NS_SUP_RW,
- CSU_CSLX_GDI, CSU_NS_SUP_RW,
- CSU_CSLX_DDI, CSU_NS_SUP_RW,
- CSU_CSLX_RESERVED1, CSU_NS_SUP_RW,
- CSU_CSLX_USB3_PHY, CSU_NS_SUP_RW,
- CSU_CSLX_RESERVED2, CSU_NS_SUP_RW,
+};
- reg = in_be32(csu_csl2);
- out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |
CSU_CSL2x_NS_USER_READ_ACCESS);+void enable_devices_ns_access(void)
This function is identical for twr and qds? Can't be just one in a common file?
+{
uint32_t *csu_csl;
uint32_t reg;
int i;
for (i = 0; i < ARRAY_SIZE(ns_dev); i++) {
csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4;reg = in_be32(csu_csl);if (ns_dev[i].ind % 2 == 0)reg |= ns_dev[i].val << 16;elsereg |= ns_dev[i].val;out_be32(csu_csl, reg);} }
int board_late_init(void)
@@ -483,7 +580,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR); scsi_scan(1);
- enable_ifc_ns_read_access();
- enable_devices_ns_access(); return 0; }
Diana Craciun
- reg = in_be32(csu_csl2);
- out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |
CSU_CSL2x_NS_USER_READ_ACCESS);+void enable_devices_ns_access(void)
This function is identical for twr and qds? Can't be just one in a common file?
Sure, I will follow your advice.
Thanks,
BRs Xiubo
+{
uint32_t *csu_csl;
uint32_t reg;
int i;
for (i = 0; i < ARRAY_SIZE(ns_dev); i++) {
csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4;reg = in_be32(csu_csl);if (ns_dev[i].ind % 2 == 0)reg |= ns_dev[i].val << 16;elsereg |= ns_dev[i].val;out_be32(csu_csl, reg);} }
int board_late_init(void)
@@ -483,7 +580,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR); scsi_scan(1);
- enable_ifc_ns_read_access();
- enable_devices_ns_access(); return 0; }
Diana Craciun
On 07/03/2014 12:51 PM, Xiubo Li wrote:
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe
But we have HYP enabled. In this case why are the series dependent on this patch?
timers that are not synchronized, effectively seeing time going backward...
Patch work: http://patchwork.ozlabs.org/patch/343084/
Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region
arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++-- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-)
Diana
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe
But we have HYP enabled. In this case why are the series dependent on this patch?
Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too.
When and where to clear them is better ? In uboot or in kernel when needed?
Thanks,
BRs Xiubo
timers that are not synchronized, effectively seeing time going backward...
Patch work: http://patchwork.ozlabs.org/patch/343084/
Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region
arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-
board/freescale/ls1021aqds/ls1021aqds.c | 110
+++++++++++++++++++--
board/freescale/ls1021atwr/ls1021atwr.c | 111
++++++++++++++++++++--
include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-)
Diana
On 07/04/2014 04:31 AM, Xiubo Li-B47053 wrote:
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe
But we have HYP enabled. In this case why are the series dependent on this patch?
Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too.
When and where to clear them is better ? In uboot or in kernel when needed?
If HYP mode is available CNTVOFF is cleared in Linux. What I am trying to say is that it will work also without the patch you mentioned.
Diana
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe
But we have HYP enabled. In this case why are the series dependent on this patch?
Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too.
When and where to clear them is better ? In uboot or in kernel when needed?
If HYP mode is available CNTVOFF is cleared in Linux. What I am trying to say is that it will work also without the patch you mentioned.
Diana
Yes, it will work, but the time won't be correct sometimes till the CNTVOFFs are cleared in Linux, which we can see from the Linux boot logs with the following is enabled: CONFIG_PRINTK_TIME=y
This is because, if the HYP mode is available for Host OS, the Physical timers Will be used, but the ARCH ARM Timer will still use the Virtual timer's counter To count the xtime.
Thanks,
BRs Xiubo
participants (3)
-
Diana Craciun -
Li.Xiubo＠freescale.com -
Xiubo Li