[U-Boot] [PATCH] arm: imx: common rework cache settings for imx6
Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC
Signed-off-by: Adrian Alonso aalonso@freescale.com --- arch/arm/cpu/armv7/mx6/soc.c | 95 --------------------------------------- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/cache.c | 103 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+), 95 deletions(-) create mode 100644 arch/arm/imx-common/cache.c
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5110112..2f7d5c8 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,9 +8,6 @@ */
#include <common.h> -#include <asm/armv7.h> -#include <asm/bootm.h> -#include <asm/pl310.h> #include <asm/errno.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> @@ -440,31 +437,6 @@ int board_postclk_init(void) return 0; }
-#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - enum dcache_option option = DCACHE_WRITETHROUGH; -#else - enum dcache_option option = DCACHE_WRITEBACK; -#endif - - /* Avoid random hang when download by usb */ - invalidate_dcache_all(); - - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); - - /* Enable caching on OCRAM and ROM */ - mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, - ROMCP_ARB_END_ADDR, - option); - mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, - IRAM_SIZE, - option); -} -#endif - #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { @@ -605,70 +577,3 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif - -#ifndef CONFIG_SYS_L2CACHE_OFF -#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 -void v7_outer_cache_enable(void) -{ - struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; - unsigned int val; - - - /* - * Set bit 22 in the auxiliary control register. If this bit - * is cleared, PL310 treats Normal Shared Non-cacheable - * accesses as Cacheable no-allocate. - */ - setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); - -#if defined CONFIG_MX6SL - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - val = readl(&iomux->gpr[11]); - if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { - /* L2 cache configured as OCRAM, reset it */ - val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; - writel(val, &iomux->gpr[11]); - } -#endif - - /* Must disable the L2 before changing the latency parameters */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x132, &pl310->pl310_tag_latency_ctrl); - writel(0x132, &pl310->pl310_data_latency_ctrl); - - val = readl(&pl310->pl310_prefetch_ctrl); - - /* Turn on the L2 I/D prefetch */ - val |= 0x30000000; - - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - -#ifndef CONFIG_MX6Q - val |= 0x40800000; -#endif - writel(val, &pl310->pl310_prefetch_ctrl); - - val = readl(&pl310->pl310_power_ctrl); - val |= L2X0_DYNAMIC_CLK_GATING_EN; - val |= L2X0_STNDBY_MODE_EN; - writel(val, &pl310->pl310_power_ctrl); - - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - -void v7_outer_cache_disable(void) -{ - struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; - - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} -#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index b9f1ca4..3b034e1 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,6 +19,7 @@ obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) +obj-y += cache.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c new file mode 100644 index 0000000..54b021c --- /dev/null +++ b/arch/arm/imx-common/cache.c @@ -0,0 +1,103 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv7.h> +#include <asm/pl310.h> +#include <asm/io.h> + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH; +#else + enum dcache_option option = DCACHE_WRITEBACK; +#endif + /* Avoid random hang when download by usb */ + invalidate_dcache_all(); + + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); + + /* Enable caching on OCRAM and ROM */ + mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, + ROMCP_ARB_END_ADDR, + option); + mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, + IRAM_SIZE, + option); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +#ifdef CONFIG_SYS_L2_PL310 +#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + unsigned int val; + + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); + +#if defined CONFIG_MX6SL + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } +#endif + + /* Must disable the L2 before changing the latency parameters */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x132, &pl310->pl310_tag_latency_ctrl); + writel(0x132, &pl310->pl310_data_latency_ctrl); + + val = readl(&pl310->pl310_prefetch_ctrl); + + /* Turn on the L2 I/D prefetch */ + val |= 0x30000000; + + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + +#ifndef CONFIG_MX6Q + val |= 0x40800000; +#endif + writel(val, &pl310->pl310_prefetch_ctrl); + + val = readl(&pl310->pl310_power_ctrl); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, &pl310->pl310_power_ctrl); + + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} +#endif /* !CONFIG_SYS_L2_PL310 */ +#endif /* !CONFIG_SYS_L2CACHE_OFF */
Move common imx6 arch init setup, init.c can be extended and reused to support imx7 SoC keeping init arch common code.
Signed-off-by: Adrian Alonso aalonso@freescale.com --- Apply patch on top of: arm: imx: common rework cache settings for imx6
arch/arm/cpu/armv7/mx6/soc.c | 274 ----------------------------- arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/init.c | 289 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 4 + 4 files changed, 294 insertions(+), 275 deletions(-) create mode 100644 arch/arm/imx-common/init.c
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2f7d5c8..d2e5776 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,25 +8,17 @@ */
#include <common.h> -#include <asm/errno.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/imx-common/boot_mode.h> -#include <asm/imx-common/dma.h> #include <stdbool.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <dm.h> #include <imx_thermal.h>
-enum ldo_reg { - LDO_ARM, - LDO_SOC, - LDO_PU, -}; - struct scu_regs { u32 ctrl; u32 config; @@ -183,260 +175,6 @@ u32 __weak get_board_rev(void) } #endif
-void init_aips(void) -{ - struct aipstz_regs *aips1, *aips2; -#ifdef CONFIG_MX6SX - struct aipstz_regs *aips3; -#endif - - aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; - aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; -#ifdef CONFIG_MX6SX - aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR; -#endif - - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, &aips1->mprot0); - writel(0x77777777, &aips1->mprot1); - writel(0x77777777, &aips2->mprot0); - writel(0x77777777, &aips2->mprot1); - - /* - * Set all OPACRx to be non-bufferable, not require - * supervisor privilege level for access,allow for - * write access and untrusted master access. - */ - writel(0x00000000, &aips1->opacr0); - writel(0x00000000, &aips1->opacr1); - writel(0x00000000, &aips1->opacr2); - writel(0x00000000, &aips1->opacr3); - writel(0x00000000, &aips1->opacr4); - writel(0x00000000, &aips2->opacr0); - writel(0x00000000, &aips2->opacr1); - writel(0x00000000, &aips2->opacr2); - writel(0x00000000, &aips2->opacr3); - writel(0x00000000, &aips2->opacr4); - -#ifdef CONFIG_MX6SX - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, &aips3->mprot0); - writel(0x77777777, &aips3->mprot1); - - /* - * Set all OPACRx to be non-bufferable, not require - * supervisor privilege level for access,allow for - * write access and untrusted master access. - */ - writel(0x00000000, &aips3->opacr0); - writel(0x00000000, &aips3->opacr1); - writel(0x00000000, &aips3->opacr2); - writel(0x00000000, &aips3->opacr3); - writel(0x00000000, &aips3->opacr4); -#endif -} - -static void clear_ldo_ramp(void) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg; - - /* ROM may modify LDO ramp up time according to fuse setting, so in - * order to be in the safe side we neeed to reset these settings to - * match the reset value: 0'b00 - */ - reg = readl(&anatop->ana_misc2); - reg &= ~(0x3f << 24); - writel(reg, &anatop->ana_misc2); -} - -/* - * Set the PMU_REG_CORE register - * - * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. - * Possible values are from 0.725V to 1.450V in steps of - * 0.025V (25mV). - */ -static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - u32 val, step, old, reg = readl(&anatop->reg_core); - u8 shift; - - if (mv < 725) - val = 0x00; /* Power gated off */ - else if (mv > 1450) - val = 0x1F; /* Power FET switched full on. No regulation */ - else - val = (mv - 700) / 25; - - clear_ldo_ramp(); - - switch (ldo) { - case LDO_SOC: - shift = 18; - break; - case LDO_PU: - shift = 9; - break; - case LDO_ARM: - shift = 0; - break; - default: - return -EINVAL; - } - - old = (reg & (0x1F << shift)) >> shift; - step = abs(val - old); - if (step == 0) - return 0; - - reg = (reg & ~(0x1F << shift)) | (val << shift); - writel(reg, &anatop->reg_core); - - /* - * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per - * step - */ - udelay(3 * step); - - return 0; -} - -static void imx_set_wdog_powerdown(bool enable) -{ - struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; - struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; - struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; - - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) - writew(enable, &wdog3->wmcr); - - /* Write to the PDE (Power Down Enable) bit */ - writew(enable, &wdog1->wmcr); - writew(enable, &wdog2->wmcr); -} - -static void set_ahb_rate(u32 val) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg, div; - - div = get_periph_clk() / val - 1; - reg = readl(&mxc_ccm->cbcdr); - - writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | - (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); -} - -static void clear_mmdc_ch_mask(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg; - reg = readl(&mxc_ccm->ccdr); - - /* Clear MMDC channel mask */ - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); - writel(reg, &mxc_ccm->ccdr); -} - -static void init_bandgap(void) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - /* - * Ensure the bandgap has stabilized. - */ - while (!(readl(&anatop->ana_misc0) & 0x80)) - ; - /* - * For best noise performance of the analog blocks using the - * outputs of the bandgap, the reftop_selfbiasoff bit should - * be set. - */ - writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); -} - - -#ifdef CONFIG_MX6SL -static void set_preclk_from_osc(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg; - - reg = readl(&mxc_ccm->cscmr1); - reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; - writel(reg, &mxc_ccm->cscmr1); -} -#endif - -#define SRC_SCR_WARM_RESET_ENABLE 0 - -static void init_src(void) -{ - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - - /* - * force warm reset sources to generate cold reset - * for a more reliable restart - */ - val = readl(&src_regs->scr); - val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE); - writel(val, &src_regs->scr); -} - -int arch_cpu_init(void) -{ - init_aips(); - - /* Need to clear MMDC_CHx_MASK to make warm reset work. */ - clear_mmdc_ch_mask(); - - /* - * Disable self-bias circuit in the analog bandap. - * The self-bias circuit is used by the bandgap during startup. - * This bit should be set after the bandgap has initialized. - */ - init_bandgap(); - - /* - * When low freq boot is enabled, ROM will not set AHB - * freq, so we need to ensure AHB freq is 132MHz in such - * scenario. - */ - if (mxc_get_clock(MXC_ARM_CLK) == 396000000) - set_ahb_rate(132000000); - - /* Set perclk to source from OSC 24MHz */ -#if defined(CONFIG_MX6SL) - set_preclk_from_osc(); -#endif - - imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ - -#ifdef CONFIG_APBH_DMA - /* Start APBH DMA */ - mxs_dma_init(); -#endif - - init_src(); - - return 0; -} - -int board_postclk_init(void) -{ - set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ - - return 0; -} - #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { @@ -458,18 +196,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif
-void boot_mode_apply(unsigned cfg_val) -{ - unsigned reg; - struct src *psrc = (struct src *)SRC_BASE_ADDR; - writel(cfg_val, &psrc->gpr9); - reg = readl(&psrc->gpr10); - if (cfg_val) - reg |= 1 << 28; - else - reg &= ~(1 << 28); - writel(reg, &psrc->gpr10); -} /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 3b034e1..d77a236 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,7 +19,7 @@ obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) -obj-y += cache.o +obj-y += cache.o init.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c new file mode 100644 index 0000000..aae8b5d --- /dev/null +++ b/arch/arm/imx-common/init.c @@ -0,0 +1,289 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/dma.h> +#include <asm/arch/crm_regs.h> + +enum ldo_reg { + LDO_ARM, + LDO_SOC, + LDO_PU, +}; + +void init_aips(void) +{ + struct aipstz_regs *aips1, *aips2; +#ifdef CONFIG_MX6SX + struct aipstz_regs *aips3; +#endif + + aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; + aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; +#ifdef CONFIG_MX6SX + aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; +#endif + + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips1->mprot0); + writel(0x77777777, &aips1->mprot1); + writel(0x77777777, &aips2->mprot0); + writel(0x77777777, &aips2->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips1->opacr0); + writel(0x00000000, &aips1->opacr1); + writel(0x00000000, &aips1->opacr2); + writel(0x00000000, &aips1->opacr3); + writel(0x00000000, &aips1->opacr4); + writel(0x00000000, &aips2->opacr0); + writel(0x00000000, &aips2->opacr1); + writel(0x00000000, &aips2->opacr2); + writel(0x00000000, &aips2->opacr3); + writel(0x00000000, &aips2->opacr4); + +#ifdef CONFIG_MX6SX + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); +#endif +} + +static void clear_ldo_ramp(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg; + + /* ROM may modify LDO ramp up time according to fuse setting, so in + * order to be in the safe side we neeed to reset these settings to + * match the reset value: 0'b00 + */ + reg = readl(&anatop->ana_misc2); + reg &= ~(0x3f << 24); + writel(reg, &anatop->ana_misc2); +} + +/* + * Set the PMU_REG_CORE register + * + * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. + * Possible values are from 0.725V to 1.450V in steps of + * 0.025V (25mV). + */ +static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val, step, old, reg = readl(&anatop->reg_core); + u8 shift; + + if (mv < 725) + val = 0x00; /* Power gated off */ + else if (mv > 1450) + val = 0x1F; /* Power FET switched full on. No regulation */ + else + val = (mv - 700) / 25; + + clear_ldo_ramp(); + + switch (ldo) { + case LDO_SOC: + shift = 18; + break; + case LDO_PU: + shift = 9; + break; + case LDO_ARM: + shift = 0; + break; + default: + return -EINVAL; + } + + old = (reg & (0x1F << shift)) >> shift; + step = abs(val - old); + if (step == 0) + return 0; + + reg = (reg & ~(0x1F << shift)) | (val << shift); + writel(reg, &anatop->reg_core); + + /* + * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per + * step + */ + udelay(3 * step); + + return 0; +} + +static void imx_set_wdog_powerdown(bool enable) +{ + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) + writew(enable, &wdog3->wmcr); + + /* Write to the PDE (Power Down Enable) bit */ + writew(enable, &wdog1->wmcr); + writew(enable, &wdog2->wmcr); +} + +static void set_ahb_rate(u32 val) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg, div; + + div = get_periph_clk() / val - 1; + reg = readl(&mxc_ccm->cbcdr); + + writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | + (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); +} + +static void clear_mmdc_ch_mask(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + reg = readl(&mxc_ccm->ccdr); + + /* Clear MMDC channel mask */ + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + writel(reg, &mxc_ccm->ccdr); +} + +static void init_bandgap(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + /* + * Ensure the bandgap has stabilized. + */ + while (!(readl(&anatop->ana_misc0) & 0x80)) + ; + /* + * For best noise performance of the analog blocks using the + * outputs of the bandgap, the reftop_selfbiasoff bit should + * be set. + */ + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); +} + + +#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + +#define SRC_SCR_WARM_RESET_ENABLE 0 + +static void init_src(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + + /* + * force warm reset sources to generate cold reset + * for a more reliable restart + */ + val = readl(&src_regs->scr); + val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE); + writel(val, &src_regs->scr); +} + +int arch_cpu_init(void) +{ + init_aips(); + + /* Need to clear MMDC_CHx_MASK to make warm reset work. */ + clear_mmdc_ch_mask(); + + /* + * Disable self-bias circuit in the analog bandap. + * The self-bias circuit is used by the bandgap during startup. + * This bit should be set after the bandgap has initialized. + */ + init_bandgap(); + + /* + * When low freq boot is enabled, ROM will not set AHB + * freq, so we need to ensure AHB freq is 132MHz in such + * scenario. + */ + if (mxc_get_clock(MXC_ARM_CLK) == 396000000) + set_ahb_rate(132000000); + + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + +#ifdef CONFIG_APBH_DMA + /* Start APBH DMA */ + mxs_dma_init(); +#endif + + init_src(); + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ + + return 0; +} +#endif + +void boot_mode_apply(unsigned cfg_val) +{ + unsigned reg; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + writel(cfg_val, &psrc->gpr9); + reg = readl(&psrc->gpr10); + if (cfg_val) + reg |= 1 << 28; + else + reg &= ~(1 << 28); + writel(reg, &psrc->gpr10); +} diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4d84a9b..9a079e5 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -137,8 +137,10 @@ /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR +#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR +#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) @@ -219,6 +221,8 @@
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) +#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) +#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
Hi Adrian,
Since this is only for mx6, why move the code to imx-common? "
ifeq ($(SOC),$(filter $(SOC),mx6)) -obj-y += cache.o +obj-y += cache.o init.o
"
Also many pieces of code are only for imx6, imx7 do not need them for now, such as the ldo ramp part.
I think basic imx7 support do not need such a big change, if we do need to consolidate code for common usage, we can do this when we need to add more stuff.
[.....]
Regards, Peng. --
On Thu, Aug 27, 2015 at 2:39 AM, Peng Fan b51431@freescale.com wrote:
Hi Adrian,
Since this is only for mx6, why move the code to imx-common? "
ifeq ($(SOC),$(filter $(SOC),mx6)) -obj-y += cache.o +obj-y += cache.o init.o
"
Also many pieces of code are only for imx6, imx7 do not need them for now, such as the ldo ramp part.
I think basic imx7 support do not need such a big change, if we do need to consolidate code for common usage, we can do this when we need to add more stuff.
Personally I think it's better off being done from the outset else it never gets done and we end up in the situation we were for imx6.
Peter
On Thu, Aug 27, 2015 at 10:00:57AM +0100, Peter Robinson wrote:
On Thu, Aug 27, 2015 at 2:39 AM, Peng Fan b51431@freescale.com wrote:
Hi Adrian,
Since this is only for mx6, why move the code to imx-common? "
ifeq ($(SOC),$(filter $(SOC),mx6)) -obj-y += cache.o +obj-y += cache.o init.o
"
Also many pieces of code are only for imx6, imx7 do not need them for now, such as the ldo ramp part.
I think basic imx7 support do not need such a big change, if we do need to consolidate code for common usage, we can do this when we need to add more stuff.
Personally I think it's better off being done from the outset else it never gets done and we end up in the situation we were for imx6.
I agree that we'd better remove duplicated code and consolidate code for common usage to make it cleaner and easy to maintian.
But from the current patch, clear_ldo_ramp set_ldo_voltage set_ahb_rate clear_mmdc_ch_mask init_bandgap set_preclk_from_osc are all imx6 specific, imx7 do not have the implementation for these functions for now.
The goal of arch_cpu_init is for different SoC usage from my understanding, I think it should be there for different SoCs. The following functions can be consolidated for common usage. boot_mode_apply init_src init_aips
The Makefile part shows only for imx6 "ifeq ($(SOC),$(filter $(SOC),mx6))", from this patch. Then why move most code mainly imx6 specific to imx-common?
If we do need such a patch for now, init_aips and boot_mode_apply and init_src may can be consolidated for common usage for imx6/7. But anyway I prefer a small cleanup patch to do this after basic imx7 upstreamed.
Regards, Peng.
Peter
--
Hi Peng, Peter,
See comments below
Regards
-----Original Message----- From: Peng Fan [mailto:b51431@freescale.com] Sent: Thursday, August 27, 2015 3:16 AM To: Peter Robinson pbrobinson@gmail.com Cc: Alonso Lazcano Adrian-B38018 aalonso@freescale.com; Estevam Fabio- R49496 Fabio.Estevam@freescale.com; u-boot@lists.denx.de; otavio@ossystems.com.br Subject: Re: [U-Boot] [PATCH] arm: imx: imx-common: init: move arch init common setup
On Thu, Aug 27, 2015 at 10:00:57AM +0100, Peter Robinson wrote:
On Thu, Aug 27, 2015 at 2:39 AM, Peng Fan b51431@freescale.com wrote:
Hi Adrian,
Since this is only for mx6, why move the code to imx-common? "
ifeq ($(SOC),$(filter $(SOC),mx6)) -obj-y += cache.o +obj-y += cache.o init.o
"
Also many pieces of code are only for imx6, imx7 do not need them for now, such as the ldo ramp part.
I think basic imx7 support do not need such a big change, if we do need to consolidate code for common usage, we can do this when we need to add more stuff.
Personally I think it's better off being done from the outset else it never gets done and we end up in the situation we were for imx6.
I agree that we'd better remove duplicated code and consolidate code for common usage to make it cleaner and easy to maintian.
But from the current patch, clear_ldo_ramp set_ldo_voltage set_ahb_rate clear_mmdc_ch_mask init_bandgap set_preclk_from_osc are all imx6 specific, imx7 do not have the implementation for these functions for now.
The goal of arch_cpu_init is for different SoC usage from my understanding, I think it should be there for different SoCs.
[Adrian] Ok I agree with that all imx6 specific function can be kept on mx6/soc.c And that each soc will implement their corresponding arch_cpu_init function to Address their particular initialization.
The following functions can be consolidated for common usage. boot_mode_apply init_src init_aips
[Adrian] Ok I can rework the patch set for it :)
The Makefile part shows only for imx6 "ifeq ($(SOC),$(filter $(SOC),mx6))", from this patch. Then why move most code mainly imx6 specific to imx- common?
[Adrian] For future patch to just add mx7 in soc filter.
If we do need such a patch for now, init_aips and boot_mode_apply and init_src may can be consolidated for common usage for imx6/7. But anyway I prefer a small cleanup patch to do this after basic imx7 upstreamed.
[Adrian] iMX7 upstream is been kept on hold due to feedback to try to reuse as much of Common code as possible, some drivers (thermal, usb) had already reworked to Support both imx6 and imx7; I think we need to push for: "arm: imx: common rework cache settings for imx6" and this patch (version 2 will be sent ASAP) So basic imx7 support ca be accepted.
Regards, Peng.
Peter
--
On Thu, Aug 27, 2015 at 1:31 PM, Alonso Adrian aalonso@freescale.com wrote:
If we do need such a patch for now, init_aips and boot_mode_apply and init_src may can be consolidated for common usage for imx6/7. But anyway I prefer a small cleanup patch to do this after basic imx7 upstreamed.
[Adrian] iMX7 upstream is been kept on hold due to feedback to try to reuse as much of Common code as possible, some drivers (thermal, usb) had already reworked to Support both imx6 and imx7; I think we need to push for: "arm: imx: common rework cache settings for imx6" and this patch (version 2 will be sent ASAP) So basic imx7 support ca be accepted.
Fully agree. Before adding new code we need to rework the code to be common and add the new one. Add code duplication for later rework does open the door for it never to be reworked and this is not acceptable.
Hi Adrian,
On Wed, Aug 26, 2015 at 06:27:42PM -0500, Adrian Alonso wrote:
Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC
Better not do this now. See below comments.
Signed-off-by: Adrian Alonso aalonso@freescale.com
arch/arm/cpu/armv7/mx6/soc.c | 95 --------------------------------------- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/cache.c | 103 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+), 95 deletions(-) create mode 100644 arch/arm/imx-common/cache.c
[...]
-#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void)
Different imx SoCs have different implementation for this.
-{ -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
- enum dcache_option option = DCACHE_WRITEBACK;
-#endif
- /* Avoid random hang when download by usb */
- invalidate_dcache_all();
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
- /* Enable caching on OCRAM and ROM */
- mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
ROMCP_ARB_END_ADDR,option);- mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
IRAM_SIZE,option);-} -#endif
From my understanding, only i.MX6 have this pl310 support.
There is no need to move the code to imx-common.
-#ifndef CONFIG_SYS_L2CACHE_OFF -#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 -void v7_outer_cache_enable(void) -{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- unsigned int val;
- /*
* Set bit 22 in the auxiliary control register. If this bit* is cleared, PL310 treats Normal Shared Non-cacheable* accesses as Cacheable no-allocate.*/- setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
/* L2 cache configured as OCRAM, reset it */val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;writel(val, &iomux->gpr[11]);- }
-#endif
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
- writel(0x132, &pl310->pl310_tag_latency_ctrl);
- writel(0x132, &pl310->pl310_data_latency_ctrl);
- val = readl(&pl310->pl310_prefetch_ctrl);
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
- /*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2* But according to ARM PL310 errata: 752271* ID: 752271: Double linefill feature can cause data corruption* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2* Workaround: The only workaround to this erratum is to disable the* double linefill feature. This is the default behavior.*/-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
- writel(val, &pl310->pl310_prefetch_ctrl);
- val = readl(&pl310->pl310_power_ctrl);
- val |= L2X0_DYNAMIC_CLK_GATING_EN;
- val |= L2X0_STNDBY_MODE_EN;
- writel(val, &pl310->pl310_power_ctrl);
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-void v7_outer_cache_disable(void) -{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-} -#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index b9f1ca4..3b034e1 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,6 +19,7 @@ obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) +obj-y += cache.o
Only mx6. Then there is no need to move the code imx-common.
From the long run, we may move most code to saying arch/arm/mach-imx in
future. But now I think we let the code be there.
[...]
Regards, Peng. --
Hi Peng,
See my comments below.
-----Original Message----- From: Peng Fan [mailto:b51431@freescale.com] Sent: Wednesday, August 26, 2015 8:34 PM To: Alonso Lazcano Adrian-B38018 aalonso@freescale.com Cc: u-boot@lists.denx.de; sbabic@denx.de; Estevam Fabio-R49496 Fabio.Estevam@freescale.com; otavio@ossystems.com.br Subject: Re: [U-Boot] [PATCH] arm: imx: common rework cache settings for imx6
Hi Adrian,
On Wed, Aug 26, 2015 at 06:27:42PM -0500, Adrian Alonso wrote:
Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC
Better not do this now. See below comments.
Signed-off-by: Adrian Alonso aalonso@freescale.com
arch/arm/cpu/armv7/mx6/soc.c | 95 --------------------------------------- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/cache.c | 103 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+), 95 deletions(-) create mode 100644 arch/arm/imx-common/cache.c
[...]
-#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void)
Different imx SoCs have different implementation for this.
[Adrian] True, but cache settings are the same for imx6 and imx7 and would like to reuse for both SoC family platforms.
-{ -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
- enum dcache_option option = DCACHE_WRITEBACK;
-#endif
- /* Avoid random hang when download by usb */
- invalidate_dcache_all();
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
- /* Enable caching on OCRAM and ROM */
- mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
ROMCP_ARB_END_ADDR,option);- mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
IRAM_SIZE,option);-} -#endif
From my understanding, only i.MX6 have this pl310 support. There is no need to move the code to imx-common.
[Adrian] Yes that's the case, that's why I added the macro check for CONFIG_SYS_L2_PL310 To just enable v7_outer_chache_xx functions for iMX6 who defines PL310 macro.
-#ifndef CONFIG_SYS_L2CACHE_OFF -#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 -void v7_outer_cache_enable(void) -{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- unsigned int val;
- /*
* Set bit 22 in the auxiliary control register. If this bit* is cleared, PL310 treats Normal Shared Non-cacheable* accesses as Cacheable no-allocate.*/- setbits_le32(&pl310->pl310_aux_ctrl,
L310_SHARED_ATT_OVERRIDE_ENABLE);
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
/* L2 cache configured as OCRAM, reset it */val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;writel(val, &iomux->gpr[11]);- }
-#endif
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
- writel(0x132, &pl310->pl310_tag_latency_ctrl);
- writel(0x132, &pl310->pl310_data_latency_ctrl);
- val = readl(&pl310->pl310_prefetch_ctrl);
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
- /*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL isr3p2
* But according to ARM PL310 errata: 752271* ID: 752271: Double linefill feature can cause data corruption* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2* Workaround: The only workaround to this erratum is to disable the* double linefill feature. This is the default behavior.*/-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
- writel(val, &pl310->pl310_prefetch_ctrl);
- val = readl(&pl310->pl310_power_ctrl);
- val |= L2X0_DYNAMIC_CLK_GATING_EN;
- val |= L2X0_STNDBY_MODE_EN;
- writel(val, &pl310->pl310_power_ctrl);
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-void v7_outer_cache_disable(void) -{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-} -#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index b9f1ca4..3b034e1 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,6 +19,7 @@ obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) +obj-y += cache.o
Only mx6. Then there is no need to move the code imx-common. From the long run, we may move most code to saying arch/arm/mach-imx in future. But now I think we let the code be there.
[Adrian] I was thinking on just adding in a new patch the filter for iMX7 soc to also use the cache common function. ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o endif
[...]
Regards, Peng. --
participants (5)
-
Adrian Alonso -
Alonso Adrian
-
Otavio Salvador -
Peng Fan -
Peter Robinson