[PATCH v2 0/7] rockchip: Add Engicam PX30.Core support
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards.
Possible baseboards are, - EDIMM2.2 Starter Kit - C.TOUCH 2.0 10.1" Open Frame
Right now boot support is working via Rockchip miniloader, will update to U-Boot TPL once the ddr supported.
Note: dts patches are in Linux mailing-list.
Earlier patch series is at: https://patchwork.ozlabs.org/project/uboot/cover/20200724105119.13123-1-jaga...
Jagan Teki (6): arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit rockchip: px30: Add EVB_PX30 Kconfig help rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 rockchip: Add Engicam PX30.Core C.TOUCH 2.0 doc: rockchip: Document Rockchip miniloader flashing
Michael Trimarchi (1): arm64: dts: rockchip: Add Engicam PX30.Core SOM
arch/arm/dts/Makefile | 2 + arch/arm/dts/px30-engicam-common.dtsi | 39 ++++ arch/arm/dts/px30-engicam-ctouch2.dtsi | 8 + arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 + arch/arm/dts/px30-px30-core-ctouch2.dts | 22 ++ arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 ++ arch/arm/dts/px30-px30-core.dtsi | 232 ++++++++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 18 ++ board/rockchip/evb_px30/MAINTAINERS | 12 ++ configs/px30-core-ctouch2-px30_defconfig | 108 ++++++++++ configs/px30-core-edimm2.2-px30_defconfig | 108 ++++++++++ doc/board/rockchip/rockchip.rst | 40 +++- 12 files changed, 616 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/px30-engicam-common.dtsi create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 arch/arm/dts/px30-px30-core.dtsi create mode 100644 configs/px30-core-ctouch2-px30_defconfig create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
From: Jagan Teki jagan@amarulasolutions.com
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board.
Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out
SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Michael Trimarchi michael@amarulasolutions.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v2: - Minor device tree adjustments as per Linux mainline changes - Add Michael Trimarchi as one of the contributors - collect Kever Yang r-b tag - Add additional copyright
arch/arm/dts/px30-engicam-common.dtsi | 39 +++++++++++++++++++++++++ arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 +++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-common.dtsi create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi
diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi new file mode 100644 index 0000000000..bd5bde989e --- /dev/null +++ b/arch/arm/dts/px30-engicam-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; /* +5V */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_3v3>; /* +3V3_SOM */ + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <800>; + vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi new file mode 100644 index 0000000000..cb00988953 --- /dev/null +++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi"
From: Michael Trimarchi michael@amarulasolutions.com
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features
PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards.
Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0
Add support for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Michael Trimarchi michael@amarulasolutions.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v2: - Minor device tree adjustments as per Linux mainline changes - Add Michael Trimarchi as one of the contributors - Collect Kever Yang r-b tag - Add additional copyright
arch/arm/dts/px30-px30-core.dtsi | 232 +++++++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm/dts/px30-px30-core.dtsi
diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-px30-core.dtsi new file mode 100644 index 0000000000..16e6cf28a4 --- /dev/null +++ b/arch/arm/dts/px30-px30-core.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "engicam,px30-px30-core", "rockchip,px30"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +};
From: Jagan Teki jagan@amarulasolutions.com
TARGET_EVB_PX30 can be possible to use other px30 boards.
Add the help text for existing EVB, so-that the new boards which are resuing this config option can mention their board help text.
This would help to track which boards are using EVB_PX30 config.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v2: - Collect Kever Yang r-b tag
arch/arm/mach-rockchip/px30/Kconfig | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index f5373c6f9f..6cd65dfa97 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -2,6 +2,11 @@ if ROCKCHIP_PX30
config TARGET_EVB_PX30 bool "EVB_PX30" + help + This target config option used for below listed px30 boards. + + EVB_PX30: + * EVB_PX30 is an evaluation board for Rockchip PX30.
config TARGET_ODROID_GO2 bool "ODROID_GO2"
From: Jagan Teki jagan@amarulasolutions.com
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v2: - Collect Kever Yang r-b tag
arch/arm/dts/Makefile | 1 + arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 +++++ arch/arm/mach-rockchip/px30/Kconfig | 6 ++ board/rockchip/evb_px30/MAINTAINERS | 6 ++ configs/px30-core-edimm2.2-px30_defconfig | 108 ++++++++++++++++++++++ 5 files changed, 142 insertions(+) create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..f1b0286fa1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ + px30-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \ diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-px30-core-edimm2.2.dts new file mode 100644 index 0000000000..c36280ce7f --- /dev/null +++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-edimm2.2.dtsi" +#include "px30-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 6cd65dfa97..98959fbf53 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -8,6 +8,12 @@ config TARGET_EVB_PX30 EVB_PX30: * EVB_PX30 is an evaluation board for Rockchip PX30.
+ PX30.Core EDIMM2.2: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam. + * PX30.Core needs to mount on top of EDIMM2.2 for creating complete + PX30.Core EDIMM2.2 Starter Kit. + config TARGET_ODROID_GO2 bool "ODROID_GO2"
diff --git a/board/rockchip/evb_px30/MAINTAINERS b/board/rockchip/evb_px30/MAINTAINERS index 4dc060c501..48fba4e046 100644 --- a/board/rockchip/evb_px30/MAINTAINERS +++ b/board/rockchip/evb_px30/MAINTAINERS @@ -5,3 +5,9 @@ F: board/rockchip/evb_px30 F: include/configs/evb_px30.h F: configs/evb-px30_defconfig F: configs/firefly-px30_defconfig + +PX30-Core-EDIMM2.2 +M: Jagan Teki jagan@amarulasolutions.com +M: Suniel Mahesh sunil@amarulasolutions.com +S: Maintained +F: configs/px30-core-edimm2.2-px30_defconfig diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig new file mode 100644 index 0000000000..07205f0243 --- /dev/null +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_EVB_PX30=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set
From: Jagan Teki jagan@amarulasolutions.com
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface.
Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector
SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Michael Trimarchi michael@amarulasolutions.com --- Changes for v2: - Add more content in patch description to describe the board capabilities - Add Michael Trimarchi as one of the contributors - Add additional copyright
arch/arm/dts/px30-engicam-ctouch2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi
diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi new file mode 100644 index 0000000000..58425b1e55 --- /dev/null +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi"
From: Jagan Teki jagan@amarulasolutions.com
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support.
PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v2: - Minor device tree adjustments as per Linux mainline changes - rename device tree from ctouch2-of10.dts to ctouch2.dts - rename defconfig from ctouch2-of10 to ctouch2 - collect Kever Yang r-b tag - Add additional copyright
arch/arm/dts/Makefile | 1 + arch/arm/dts/px30-px30-core-ctouch2.dts | 22 +++++ arch/arm/mach-rockchip/px30/Kconfig | 7 ++ board/rockchip/evb_px30/MAINTAINERS | 6 ++ configs/px30-core-ctouch2-px30_defconfig | 108 +++++++++++++++++++++++ 5 files changed, 144 insertions(+) create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts create mode 100644 configs/px30-core-ctouch2-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f1b0286fa1..1ffa07cc6e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ + px30-px30-core-ctouch2.dtb \ px30-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb
diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-px30-core-ctouch2.dts new file mode 100644 index 0000000000..2da0128188 --- /dev/null +++ b/arch/arm/dts/px30-px30-core-ctouch2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0"; + compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 98959fbf53..507a54af58 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -14,6 +14,13 @@ config TARGET_EVB_PX30 * PX30.Core needs to mount on top of EDIMM2.2 for creating complete PX30.Core EDIMM2.2 Starter Kit.
+ PX30.Core CTOUCH2: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * CTOUCH2.0 is a general purpose Carrier board with capacitive + touch interface support. + * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete + PX30.Core C.TOUCH Carrier board. + config TARGET_ODROID_GO2 bool "ODROID_GO2"
diff --git a/board/rockchip/evb_px30/MAINTAINERS b/board/rockchip/evb_px30/MAINTAINERS index 48fba4e046..2634a0aa8d 100644 --- a/board/rockchip/evb_px30/MAINTAINERS +++ b/board/rockchip/evb_px30/MAINTAINERS @@ -11,3 +11,9 @@ M: Jagan Teki jagan@amarulasolutions.com M: Suniel Mahesh sunil@amarulasolutions.com S: Maintained F: configs/px30-core-edimm2.2-px30_defconfig + +PX30-Core-CTOUCH2.0 +M: Jagan Teki jagan@amarulasolutions.com +M: Suniel Mahesh sunil@amarulasolutions.com +S: Maintained +F: configs/px30-core-ctouch2-px30_defconfig diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig new file mode 100644 index 0000000000..ea3c9c85c1 --- /dev/null +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_EVB_PX30=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set
From: Jagan Teki jagan@amarulasolutions.com
This would be useful and recommended boot flow for new boards which has doesn't have the DDR support yet in mainline.
Sometimes it is very useful for debugging mainline DDR support.
Documen it for px30 boot flow.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Changes for v2: - no changes
doc/board/rockchip/rockchip.rst | 40 ++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 8c92de0c92..ea061ad171 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -123,6 +123,9 @@ To build rk3399 boards:: Flashing --------
+1. Package the image with U-Boot TPL/SPL +----------------------------------------- + SD Card ^^^^^^^
@@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD:: sf erase 0x60000 +$filesize sf write $kernel_addr_r 0x60000 ${filesize}
+2. Package the image with Rockchip miniloader +--------------------------------------------- + +Image package with Rockchip miniloader requires robin [1]. + +Create idbloader.img + +.. code-block:: none + + cd u-boot + ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img + cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img + sudo dd if=idbloader.img of=/dev/sda seek=64 + +Create trust.img + +.. code-block:: none + + cd rkbin + ./tools/trust_merger RKTRUST/PX30TRUST.ini + sudo dd if=trust.img of=/dev/sda seek=24576 + +Create uboot.img + +.. code-block:: none + + rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000 + sudo dd if=uboot.img of=/dev/sda seek=16384 + +Note: +1. 0x200000 is load address and it's an optional in some platforms. +2. rkbin binaries are kept on updating, so would recommend to use the latest versions. + TODO ----
@@ -195,5 +231,7 @@ TODO - Document SPI flash boot - Add missing SoC's with it boards list
+[1] https://github.com/rockchip-linux/rkbin + .. Jagan Teki jagan@amarulasolutions.com -.. Tuesday 02 June 2020 12:18:57 AM IST +.. Thursday 23 July 2020 04:50:22 PM IST
Hi Suniel,
Seems like the comments in V1 does not addressed.
And for the DRAM support, all the DRAM type driver for PX30 has been support, what's the reason you can't add
DRAM support in TPL for this board?
Thanks,
- Kever
On 2020/9/14 下午11:36, Suniel Mahesh wrote:
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards.
Possible baseboards are,
- EDIMM2.2 Starter Kit
- C.TOUCH 2.0 10.1" Open Frame
Right now boot support is working via Rockchip miniloader, will update to U-Boot TPL once the ddr supported.
Note: dts patches are in Linux mailing-list.
Earlier patch series is at: https://patchwork.ozlabs.org/project/uboot/cover/20200724105119.13123-1-jaga...
Jagan Teki (6): arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit rockchip: px30: Add EVB_PX30 Kconfig help rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 rockchip: Add Engicam PX30.Core C.TOUCH 2.0 doc: rockchip: Document Rockchip miniloader flashing
Michael Trimarchi (1): arm64: dts: rockchip: Add Engicam PX30.Core SOM
arch/arm/dts/Makefile | 2 + arch/arm/dts/px30-engicam-common.dtsi | 39 ++++ arch/arm/dts/px30-engicam-ctouch2.dtsi | 8 + arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 + arch/arm/dts/px30-px30-core-ctouch2.dts | 22 ++ arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 ++ arch/arm/dts/px30-px30-core.dtsi | 232 ++++++++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 18 ++ board/rockchip/evb_px30/MAINTAINERS | 12 ++ configs/px30-core-ctouch2-px30_defconfig | 108 ++++++++++ configs/px30-core-edimm2.2-px30_defconfig | 108 ++++++++++ doc/board/rockchip/rockchip.rst | 40 +++- 12 files changed, 616 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/px30-engicam-common.dtsi create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 arch/arm/dts/px30-px30-core.dtsi create mode 100644 configs/px30-core-ctouch2-px30_defconfig create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
participants (2)
-
Kever Yang -
Suniel Mahesh