[PATCH] arm64: zynqmp: Disable Tri-state for MIO38 Pin

gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-stateĀ is enabled for MIO38, causing inappropriate PHY register reads.
Disabled Tri-state for MIO38 to make HW reset work.
Tri-state disable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7a3 00000540
Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 00000540
Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 25 +++++++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 22e7d68d02..c4f1da9218 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -190,6 +190,25 @@ &pinctrl0 { status = "okay";
+ pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -345,6 +364,12 @@ }; };
+&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index eadc256306..6c5e0e5660 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -178,6 +178,25 @@ &pinctrl0 { status = "okay";
+ pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -333,6 +352,12 @@ }; };
+&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default";

On 10/20/23 07:06, Tejas Bhumkar wrote:
gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-state is enabled for MIO38, causing inappropriate PHY register reads.
Disabled Tri-state for MIO38 to make HW reset work.
Tri-state disable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7a3 00000540
Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 00000540
Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 25 +++++++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 22e7d68d02..c4f1da9218 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -190,6 +190,25 @@ &pinctrl0 { status = "okay";
- pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
- pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp";
@@ -345,6 +364,12 @@ }; };
+&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
+};
- &uart1 { status = "okay"; pinctrl-names = "default";
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index eadc256306..6c5e0e5660 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -178,6 +178,25 @@ &pinctrl0 { status = "okay";
- pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
- };
- pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp";
@@ -333,6 +352,12 @@ }; };
+&gpio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio0_default>;
+};
- &uart1 { status = "okay"; pinctrl-names = "default";
Applied. M
participants (2)
-
Michal Simek
-
Tejas Bhumkar