[U-Boot] [PATCH 1/2] ppc/85xx: Introduce low level write_tlb function
Factor out the code we use to actually write a tlb entry.
set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Added update to copyright * introduced FSL_BOOKE_MAS7 macro
cpu/mpc85xx/start.S | 21 ++++++++++++++++++++- cpu/mpc85xx/tlb.c | 16 +++------------- include/asm-ppc/mmu.h | 4 ++++ 3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 7a23b4f..49256b3 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -1127,6 +1127,25 @@ flush_dcache:
blr
+ .globl write_tlb +write_tlb: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr MAS7,r7 +#endif + li r3,0 +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r3 +#endif + isync + tlbwe + msync + isync + blr + .globl setup_ivors setup_ivors:
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 03c2449..d39712a 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -42,19 +42,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = FSL_BOOKE_MAS2(epn, wimge); _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); - _mas7 = rpn >> 32; + _mas7 = FSL_BOOKE_MAS7(rpn);
- mtspr(MAS0, _mas0); - mtspr(MAS1, _mas1); - mtspr(MAS2, _mas2); - mtspr(MAS3, _mas3); -#ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); -#endif -#ifdef CONFIG_SYS_BOOK3E_HV - mtspr(MAS8, 0); -#endif - asm volatile("isync;msync;tlbwe;isync"); + write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
#ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index eda2959..8f382fd 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -450,6 +450,8 @@ extern void print_bats(void); (((epn) & MAS3_RPN) | (wimge)) #define FSL_BOOKE_MAS3(rpn, user, perms) \ (((rpn) & MAS3_RPN) | (user) | (perms)) +#define FSL_BOOKE_MAS7(rpn) \ + (((u64)(rpn)) >> 32)
#define BOOKE_PAGESZ_1K 0 #define BOOKE_PAGESZ_4K 1 @@ -480,6 +482,8 @@ extern int find_tlb_idx(void *addr, u8 tlbsel);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
+extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); + #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Use new FSL_BOOKE_MAS7 macro
cpu/mpc85xx/tlb.c | 9 +++++---- include/asm-ppc/mmu.h | 21 ++++++++++----------- 2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index d39712a..b8ea5c5 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -90,10 +90,11 @@ void init_tlbs(void) int i;
for (i = 0; i < num_tlb_entries; i++) { - set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, - tlb_table[i].perms, tlb_table[i].wimge, - tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, - tlb_table[i].iprot); + write_tlb(tlb_table[i].mas0, + tlb_table[i].mas1, + tlb_table[i].mas2, + tlb_table[i].mas3, + tlb_table[i].mas7); }
return ; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8f382fd..a019d0b 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -485,19 +485,18 @@ extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ - { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ - .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } + { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ + .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ + .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ + .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ + .mas7 = FSL_BOOKE_MAS7(_rpn), }
struct fsl_e_tlb_entry { - u8 tlb; - u32 epn; - u64 rpn; - u8 perms; - u8 wimge; - u8 ts; - u8 esel; - u8 tsize; - u8 iprot; + u32 mas0; + u32 mas1; + u32 mas2; + u32 mas3; + u32 mas7; };
extern struct fsl_e_tlb_entry tlb_table[];
participants (1)
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Kumar Gala