From: Roy Zang tie-fei.zang@freescale.com

The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function.

Signed-off-by: Roy Zang tie-fei.zang@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ arch/powerpc/include/asm/immap_85xx.h | 13 +++++++++++++ 3 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 174b031..856d69e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -444,6 +444,23 @@ int cpu_init_r(void) isync(); #endif

+#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy1 = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + out_be32(&usb_phy1->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif +#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy2 = + (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + out_be32(&usb_phy2->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 92d825a..78fd677 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -269,6 +269,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE

#elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -281,6 +283,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE

#elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -325,6 +329,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE

#elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -337,6 +343,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE

#else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index caa3c59..75ee506 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2304,6 +2304,13 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t;

+typedef struct ccsr_usb_phy { + u8 res0[0x18]; + u32 usb_enable_override; + u8 res[0xe4]; +} ccsr_usb_phy_t; +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 + #ifdef CONFIG_SECURE_BOOT typedef struct ccsr_sfp_regs { u8 reserved0[0x40]; @@ -2350,6 +2357,8 @@ typedef struct ccsr_snvs_regs { #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 @@ -2475,6 +2484,10 @@ typedef struct ccsr_snvs_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \