Hi Tom,

please pull these changes to your tree.

CI doesn't show any issue. https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/11584

There is new pwm driver and also gem update to DM_ETH_PHY. I want to also update other two xilinx ethernet driver but it requires a little bit of time to test it properly.

Thanks, Michal

The following changes since commit d2e5250be49fce4653689c41a5dc7e2d7e7ecf33:

Merge tag 'next-20220328' of https://source.denx.de/u-boot/custodians/u-boot-video into next (2022-03-28 17:04:45 -0400)

are available in the Git repository at:

git@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2022.07-rc1-v2

for you to fetch changes up to a7379ba6505d70d887951be9ebb3f47e3792c708:

net: zynq_gem: Add SGMII dynamic config support (2022-04-05 15:13:13 +0200)

---------------------------------------------------------------- Xilinx changes for v2022.07-rc1 v2

xilinx: - Allow booting bigger kernels till 100MB

zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device

serial_zynq: - Change fifo behavior in DEBUG mode

zynq_sdhci: - Fix BASECLK setting calculation

clk_zynqmp: - Add support for showing video clock

gpio: - Update slg driver to handle DT flags

net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver

pwm: - Add driver for cadence PWM

versal: - Add support for reserved memory

firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations

include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers

---------------------------------------------------------------- Ashok Reddy Soma (1): mmc: zynq_sdhci: Fix SDx_BASECLK configuration

Michal Simek (13): firmware: zynqmp: Do not bind PD driver in SPL if disabled arm64: versal: Do not place u-boot to reserved memory location dt-bindings: phy: Sync phy.h with Linux kernel arm64: zynqmp: Remove low level UART setting cont serial: zynq: Change fifo behavior in debug mode timer: cadence: Add bind function to driver pwm: Add driver for cadence TTC arm: zynqmp: Enable PWM command and cadence ttc pwm driver xilinx: Increase max size of image from 60 to 100MB clk: zynqmp: Add support for for DP audio/video clocks arm64: zynqmp: Record ID code for XCZU1EG device dt-bindings: xilinx: Add missing ids for PD net: zynq_gem: Use shared MDIO bus support for zynqmp

Sai Krishna Potthuri (1): arm64: zynqmp: Add resets property to sdhci nodes

T Karthik Reddy (6): net: phy: Fix rgmii-id phy reset timeout issue net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabled net: zynq_gem: Move ethernet info print statement gpio: slg7xl45106: Update gpio desc flags from DT firmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config api net: zynq_gem: Add SGMII dynamic config support

MAINTAINERS | 1 + arch/arm/dts/zynqmp.dtsi | 2 + board/xilinx/versal/board.c | 20 ++ board/xilinx/zynqmp/zynqmp-dlc21-revA/psu_init_gpl.c | 4 - board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c | 4 - board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c | 8 - board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c | 8 - board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c | 8 - board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c | 4 - board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c | 4 - board/xilinx/zynqmp/zynqmp.c | 5 + configs/xilinx_zynqmp_virt_defconfig | 3 + drivers/clk/clk_zynqmp.c | 7 + drivers/firmware/firmware-zynqmp.c | 19 +- drivers/gpio/gpio_slg7xl45106.c | 2 + drivers/mmc/zynq_sdhci.c | 9 + drivers/net/phy/ethernet_id.c | 49 ++-- drivers/net/phy/phy.c | 2 +- drivers/net/zynq_gem.c | 86 ++++++- drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cadence-ttc.c | 261 ++++++++++++++++++++ drivers/serial/serial_zynq.c | 10 +- drivers/timer/cadence-ttc.c | 12 + include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_zynqmp.h | 2 +- include/dt-bindings/phy/phy.h | 4 +- include/dt-bindings/power/xlnx-versal-power.h | 11 + include/dt-bindings/power/xlnx-zynqmp-power.h | 11 + include/phy.h | 2 +- include/zynqmp_firmware.h | 7 + 31 files changed, 493 insertions(+), 82 deletions(-) create mode 100644 drivers/pwm/pwm-cadence-ttc.c