[U-Boot] [PATCH 1/7] powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +++ arch/powerpc/cpu/mpc85xx/fdt.c | 7 +++ arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 21 ++++++++ arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + board/freescale/corenet_ds/corenet_ds.c | 44 ---------------- include/configs/corenet_ds.h | 17 +++--- 8 files changed, 133 insertions(+), 52 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4a6cc65..b2be1fc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -40,6 +40,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_HAS_SRIO +extern void srio_init(void); +#endif + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -384,6 +388,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init();
+#ifdef CONFIG_SYS_HAS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 53e0596..5cfe497 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -38,6 +38,9 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob); +#ifdef CONFIG_SYS_HAS_SRIO +extern void ft_srio_setup(void *blob); +#endif
#ifdef CONFIG_MP #include "mp.h" @@ -478,4 +481,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_qportals(blob); #endif + +#ifdef CONFIG_SYS_HAS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 95c73be..99332e6 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -16,6 +16,7 @@ endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o +COBJS-$(CONFIG_SYS_HAS_SRIO) += srio.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 54e60bb..e9dbdc2 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/mp.h> #include <asm/fsl_enet.h> +#include <asm/fsl_serdes.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) return fdt_setprop_string(blob, offset, "phy-connection-type", fsl_phy_enet_if_str[phyc]); } + +#ifdef CONFIG_SYS_HAS_SRIO +void ft_srio_setup(void *blob) +{ +#ifdef CONFIG_SRIO1 + if (!is_serdes_configured(SRIO1)) { + fdt_del_node_and_alias(blob, "rio0"); + } +#else + fdt_del_node_and_alias(blob, "rio0"); +#endif +#ifdef CONFIG_SRIO2 + if (!is_serdes_configured(SRIO2)) { + fdt_del_node_and_alias(blob, "rio1"); + } +#else + fdt_del_node_and_alias(blob, "rio1"); +#endif +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c new file mode 100644 index 0000000..e46d328 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -0,0 +1,86 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 + #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 + #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_SRIO" +#endif + +void srio_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + int srio1_used = 0, srio2_used = 0; + + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + LAW_TRGT_IF_RIO_1); + srio1_used = 1; + printf("SRIO1: enabled\n"); + } else { + printf("SRIO1: disabled\n"); + } + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + LAW_TRGT_IF_RIO_2); + srio2_used = 1; + printf("SRIO2: enabled\n"); + } else { + printf("SRIO2: disabled\n"); + } +#endif + +#ifdef CONFIG_FSL_CORENET + /* On FSL_CORENET devices we can disable individual ports */ + if (!srio1_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); + if (!srio2_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); +#endif + + /* neither port is used - disable everything */ + if (!srio1_used && !srio2_used) { + setbits_be32(&gur->devdisr, _DEVDISR_SRIO1); + setbits_be32(&gur->devdisr, _DEVDISR_SRIO2); + setbits_be32(&gur->devdisr, _DEVDISR_RMU); + } +} diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 0e255ff..6a4279c 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -90,6 +90,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 +#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index f183cf6..232dc72 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -157,34 +157,10 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. @@ -217,24 +193,6 @@ void board_lmb_reserve(struct lmb *lmb) } #endif
-void ft_srio_setup(void *blob) -{ -#ifdef CONFIG_SRIO1 - if (!is_serdes_configured(SRIO1)) { - fdt_del_node_and_alias(blob, "rio0"); - } -#else - fdt_del_node_and_alias(blob, "rio0"); -#endif -#ifdef CONFIG_SRIO2 - if (!is_serdes_configured(SRIO2)) { - fdt_del_node_and_alias(blob, "rio1"); - } -#else - fdt_del_node_and_alias(blob, "rio1"); -#endif -} - void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -242,8 +200,6 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
- ft_srio_setup(blob); - base = getenv_bootm_low(); size = getenv_bootm_size();
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e1cd1b0..477ca09 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -51,6 +51,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */
@@ -265,21 +266,21 @@ /* * RapidIO */ -#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* * General PCI
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8548cds/law.c | 5 +---- board/freescale/mpc8548cds/tlb.c | 9 ++++----- include/configs/MPC8548CDS.h | 15 ++++++++------- 3 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index e59fee8..5b6943d 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -57,9 +57,6 @@ struct law_entry law_table[] = { #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_RIO_MEM_PHYS - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -#endif };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 2267ad7..b2c1b31 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
/* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#endif + /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4c5b998..da1f728 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 2010 Freescale Semiconductor. + * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -40,10 +40,12 @@ #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif
+#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_RIO #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ @@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif
-#ifdef CONFIG_RIO /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY #define BRIDGE_ID 17
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8568mds/law.c | 3 +-- include/configs/MPC8568MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index e24b72b..c5cf7ba 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -50,7 +50,6 @@ */
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a491650..0c858c9 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007, 2010 Freescale Semiconductor. + * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCIE1 1 /* PCIE controller */ @@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_QE /*
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8569mds/law.c | 3 +-- include/configs/MPC8569MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c index bcd0311..4f4a93b 100644 --- a/board/freescale/mpc8569mds/law.c +++ b/board/freescale/mpc8569mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -52,7 +52,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 814c175..2c2d775 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
+#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ @@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_QE /*
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc86xx/fdt.c | 9 ++++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index ff89ee5..3b96bf5 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,6 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob); +#ifdef CONFIG_SYS_HAS_SRIO +extern void ft_srio_setup(void *blob); +#endif
void ft_cpu_setup(void *blob, bd_t *bd) { @@ -58,4 +61,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob); #endif + +#ifdef CONFIG_SYS_HAS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4e60cbb..cc338e4 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1,7 +1,7 @@ /* * MPC86xx Internal Memory Map * - * Copyright 2004 Freescale Semiconductor + * Copyright 2004, 2011 Freescale Semiconductor * Jeff Brown (Jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -1205,6 +1205,8 @@ typedef struct ccsr_gur { #define MPC86xx_DEVDISR_PCI1 0x80000000 #define MPC86xx_DEVDISR_PCIE1 0x40000000 #define MPC86xx_DEVDISR_PCIE2 0x20000000 +#define MPC86xx_DEVDISR_SRIO 0x00080000 +#define MPC86xx_DEVDISR_RMSG 0x00040000 #define MPC86xx_DEVDISR_CPU0 0x00008000 #define MPC86xx_DEVDISR_CPU1 0x00004000 #define MPC86xx_RSTCR_HRST_REQ 0x00000002
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8641hpcn/law.c | 5 +---- include/configs/MPC8641HPCN.h | 30 +++++++++++++----------------- 2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 30a7b70..08f1eb2 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -53,9 +53,6 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif -#if defined(CONFIG_RIO) - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -#endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index fea0876..dc3b1d7 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2010 Freescale Semiconductor. + * Copyright 2006, 2010-2011 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -57,18 +57,14 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe0000000
-/* - * set this to enable Rapid IO. PCI and RIO are mutually exclusive - */ -/*#define CONFIG_RIO 1*/ +#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */
-#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -319,13 +315,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE #endif -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
/* * General PCI @@ -514,18 +510,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #endif
Signed-off-by: Kumar Gala galak@kernel.crashing.org CC: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8641d/law.c | 1 - include/configs/sbc8641d.h | 15 +++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index a6f60ee..14259d6 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -51,7 +51,6 @@ struct law_entry law_table[] = { #endif SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 90d84eb..f425150 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -57,6 +57,9 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe8000000
+#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ @@ -297,9 +300,9 @@ /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
/* * General PCI @@ -417,10 +420,10 @@ * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
[[PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code] On 06/01/2011 (Thu 10:58) Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org CC: Paul Gortmaker paul.gortmaker@windriver.com
Tested in conjuntion with the mpc85xx dev branch and Peter's patch.
For some reason flash erase doesn't work, but I'm guessing that is a completely unrelated regression that I'll need to track down.
Tested-by: Paul Gortmaker paul.gortmaker@windriver.com
P.
board/sbc8641d/law.c | 1 - include/configs/sbc8641d.h | 15 +++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index a6f60ee..14259d6 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -51,7 +51,6 @@ struct law_entry law_table[] = { #endif SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 90d84eb..f425150 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -57,6 +57,9 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe8000000
+#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_PCI 1 /* Enable PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ @@ -297,9 +300,9 @@ /*
- RapidIO MMU
*/ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
/*
- General PCI
@@ -417,10 +420,10 @@
- BAT2 512M Cache-inhibited, guarded
- 0xc000_0000 512M RapidIO Memory
*/ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
1.7.2.3
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org CC: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8641d/law.c | 1 - include/configs/sbc8641d.h | 15 +++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-)
applied to 85xx
- k
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/mpc8641hpcn/law.c | 5 +---- include/configs/MPC8641HPCN.h | 30 +++++++++++++----------------- 2 files changed, 14 insertions(+), 21 deletions(-)
applied to 85xx
- k
Hello.
On 06-01-2011 19:58, Kumar Gala wrote:
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by: Kumar Galagalak@kernel.crashing.org
arch/powerpc/cpu/mpc86xx/fdt.c | 9 ++++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index ff89ee5..3b96bf5 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c
[...]
@@ -14,6 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob); +#ifdef CONFIG_SYS_HAS_SRIO +extern void ft_srio_setup(void *blob); +#endif
There's no need to enclose the *extern* declaration within #ifdef.
WBR, Sergei
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Removed ifdef protection around externs per Sergei
arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +++- arch/powerpc/cpu/mpc85xx/fdt.c | 7 ++- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 21 ++++++++ arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + board/freescale/corenet_ds/corenet_ds.c | 44 ---------------- include/configs/corenet_ds.h | 17 +++--- 8 files changed, 131 insertions(+), 54 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4a6cc65..98c70e9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -40,6 +40,8 @@
DECLARE_GLOBAL_DATA_PTR;
+extern void srio_init(void); + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -384,6 +386,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init();
+#ifdef CONFIG_SYS_HAS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 53e0596..e7e6a67 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob);
#ifdef CONFIG_MP #include "mp.h" @@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_qportals(blob); #endif + +#ifdef CONFIG_SYS_HAS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 95c73be..99332e6 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -16,6 +16,7 @@ endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o +COBJS-$(CONFIG_SYS_HAS_SRIO) += srio.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 54e60bb..e9dbdc2 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/mp.h> #include <asm/fsl_enet.h> +#include <asm/fsl_serdes.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) return fdt_setprop_string(blob, offset, "phy-connection-type", fsl_phy_enet_if_str[phyc]); } + +#ifdef CONFIG_SYS_HAS_SRIO +void ft_srio_setup(void *blob) +{ +#ifdef CONFIG_SRIO1 + if (!is_serdes_configured(SRIO1)) { + fdt_del_node_and_alias(blob, "rio0"); + } +#else + fdt_del_node_and_alias(blob, "rio0"); +#endif +#ifdef CONFIG_SRIO2 + if (!is_serdes_configured(SRIO2)) { + fdt_del_node_and_alias(blob, "rio1"); + } +#else + fdt_del_node_and_alias(blob, "rio1"); +#endif +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c new file mode 100644 index 0000000..e46d328 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -0,0 +1,86 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 + #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 + #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_SRIO" +#endif + +void srio_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + int srio1_used = 0, srio2_used = 0; + + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + LAW_TRGT_IF_RIO_1); + srio1_used = 1; + printf("SRIO1: enabled\n"); + } else { + printf("SRIO1: disabled\n"); + } + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + LAW_TRGT_IF_RIO_2); + srio2_used = 1; + printf("SRIO2: enabled\n"); + } else { + printf("SRIO2: disabled\n"); + } +#endif + +#ifdef CONFIG_FSL_CORENET + /* On FSL_CORENET devices we can disable individual ports */ + if (!srio1_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); + if (!srio2_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); +#endif + + /* neither port is used - disable everything */ + if (!srio1_used && !srio2_used) { + setbits_be32(&gur->devdisr, _DEVDISR_SRIO1); + setbits_be32(&gur->devdisr, _DEVDISR_SRIO2); + setbits_be32(&gur->devdisr, _DEVDISR_RMU); + } +} diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 0e255ff..6a4279c 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -90,6 +90,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 +#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index f183cf6..232dc72 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -157,34 +157,10 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. @@ -217,24 +193,6 @@ void board_lmb_reserve(struct lmb *lmb) } #endif
-void ft_srio_setup(void *blob) -{ -#ifdef CONFIG_SRIO1 - if (!is_serdes_configured(SRIO1)) { - fdt_del_node_and_alias(blob, "rio0"); - } -#else - fdt_del_node_and_alias(blob, "rio0"); -#endif -#ifdef CONFIG_SRIO2 - if (!is_serdes_configured(SRIO2)) { - fdt_del_node_and_alias(blob, "rio1"); - } -#else - fdt_del_node_and_alias(blob, "rio1"); -#endif -} - void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -242,8 +200,6 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
- ft_srio_setup(blob); - base = getenv_bootm_low(); size = getenv_bootm_size();
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e1cd1b0..477ca09 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -51,6 +51,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */
@@ -265,21 +266,21 @@ /* * RapidIO */ -#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* * General PCI
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Removed ifdef protection around extern per Sergei * Added missing call to srio_init
arch/powerpc/cpu/mpc86xx/cpu_init.c | 7 ++++++- arch/powerpc/cpu/mpc86xx/fdt.c | 7 ++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index 1d35c0c..cf3e4d6 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -34,6 +34,7 @@ #include <asm/fsl_serdes.h> #include <asm/mp.h>
+extern void srio_init(void); void setup_bats(void);
DECLARE_GLOBAL_DATA_PTR; @@ -80,6 +81,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init();
+#ifdef CONFIG_SYS_HAS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index ff89ee5..c3cd062 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,6 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob);
void ft_cpu_setup(void *blob, bd_t *bd) { @@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob); #endif + +#ifdef CONFIG_SYS_HAS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4e60cbb..cc338e4 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1,7 +1,7 @@ /* * MPC86xx Internal Memory Map * - * Copyright 2004 Freescale Semiconductor + * Copyright 2004, 2011 Freescale Semiconductor * Jeff Brown (Jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -1205,6 +1205,8 @@ typedef struct ccsr_gur { #define MPC86xx_DEVDISR_PCI1 0x80000000 #define MPC86xx_DEVDISR_PCIE1 0x40000000 #define MPC86xx_DEVDISR_PCIE2 0x20000000 +#define MPC86xx_DEVDISR_SRIO 0x00080000 +#define MPC86xx_DEVDISR_RMSG 0x00040000 #define MPC86xx_DEVDISR_CPU0 0x00008000 #define MPC86xx_DEVDISR_CPU1 0x00004000 #define MPC86xx_RSTCR_HRST_REQ 0x00000002
On Jan 9, 2011, at 3:16 PM, Kumar Gala wrote:
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Removed ifdef protection around extern per Sergei
- Added missing call to srio_init
arch/powerpc/cpu/mpc86xx/cpu_init.c | 7 ++++++- arch/powerpc/cpu/mpc86xx/fdt.c | 7 ++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 3 files changed, 15 insertions(+), 3 deletions(-)
applied to 85xx
- k
On Jan 9, 2011, at 3:16 PM, Kumar Gala wrote:
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Removed ifdef protection around externs per Sergei
applied to 85xx
- k
Dear Kumar Gala,
In message 1294607813-27723-1-git-send-email-galak@kernel.crashing.org you wrote:
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
We don't use a "CONFIG_SYS_HAS_*" normally; can we use plain CONFIG_SYS_SRIO instead? (yes, I am aware of the CONFIG_SYS_HAS_SERDES precedent, which escaped my attantion during review - that should be fixed, too).
CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
These need to be documented (README).
Best regards,
Wolfgang Denk
On Jan 11, 2011, at 1:09 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1294607813-27723-1-git-send-email-galak@kernel.crashing.org you wrote:
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
We don't use a "CONFIG_SYS_HAS_*" normally; can we use plain CONFIG_SYS_SRIO instead? (yes, I am aware of the CONFIG_SYS_HAS_SERDES precedent, which escaped my attantion during review - that should be fixed, too).
CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
These need to be documented (README).
Changes made, please ACK the first patch in the series.
- k
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO * Added defines to README
README | 18 +++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +++- arch/powerpc/cpu/mpc85xx/fdt.c | 7 ++- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 23 ++++++++- arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + board/freescale/corenet_ds/corenet_ds.c | 44 ---------------- include/configs/corenet_ds.h | 19 ++++--- 9 files changed, 151 insertions(+), 56 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c
diff --git a/README b/README index 68f5fb0..b30df12 100644 --- a/README +++ b/README @@ -2771,6 +2771,24 @@ Low Level (hardware related) configuration options: Disable PCI-Express on systems where it is supported but not required.
+- CONFIG_SYS_SRIO: + Chip has SRIO or not + +- CONFIG_SRIO1: + Board has SRIO 1 port available + +- CONFIG_SRIO2: + Board has SRIO 2 port available + +- CONFIG_SYS_SRIOn_MEM_VIRT: + Virtual Address of SRIO port 'n' memory region + +- CONFIG_SYS_SRIOn_MEM_PHYS: + Physical Address of SRIO port 'n' memory region + +- CONFIG_SYS_SRIOn_MEM_SIZE: + Size of SRIO port 'n' memory region + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4a6cc65..1d016c4 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -40,6 +40,8 @@
DECLARE_GLOBAL_DATA_PTR;
+extern void srio_init(void); + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -384,6 +386,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init();
+#ifdef CONFIG_SYS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 53e0596..00fa752 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob);
#ifdef CONFIG_MP #include "mp.h" @@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_qportals(blob); #endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 95c73be..5dfd65b 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -16,6 +16,7 @@ endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o +COBJS-$(CONFIG_SYS_SRIO) += srio.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 54e60bb..0c166fd 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/mp.h> #include <asm/fsl_enet.h> +#include <asm/fsl_serdes.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) return fdt_setprop_string(blob, offset, "phy-connection-type", fsl_phy_enet_if_str[phyc]); } + +#ifdef CONFIG_SYS_SRIO +void ft_srio_setup(void *blob) +{ +#ifdef CONFIG_SRIO1 + if (!is_serdes_configured(SRIO1)) { + fdt_del_node_and_alias(blob, "rio0"); + } +#else + fdt_del_node_and_alias(blob, "rio0"); +#endif +#ifdef CONFIG_SRIO2 + if (!is_serdes_configured(SRIO2)) { + fdt_del_node_and_alias(blob, "rio1"); + } +#else + fdt_del_node_and_alias(blob, "rio1"); +#endif +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c new file mode 100644 index 0000000..e46d328 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -0,0 +1,86 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 + #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 + #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_SRIO" +#endif + +void srio_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + int srio1_used = 0, srio2_used = 0; + + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + LAW_TRGT_IF_RIO_1); + srio1_used = 1; + printf("SRIO1: enabled\n"); + } else { + printf("SRIO1: disabled\n"); + } + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + LAW_TRGT_IF_RIO_2); + srio2_used = 1; + printf("SRIO2: enabled\n"); + } else { + printf("SRIO2: disabled\n"); + } +#endif + +#ifdef CONFIG_FSL_CORENET + /* On FSL_CORENET devices we can disable individual ports */ + if (!srio1_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); + if (!srio2_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); +#endif + + /* neither port is used - disable everything */ + if (!srio1_used && !srio2_used) { + setbits_be32(&gur->devdisr, _DEVDISR_SRIO1); + setbits_be32(&gur->devdisr, _DEVDISR_SRIO2); + setbits_be32(&gur->devdisr, _DEVDISR_RMU); + } +} diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 0e255ff..6a4279c 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -90,6 +90,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 +#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index f183cf6..232dc72 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -157,34 +157,10 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. @@ -217,24 +193,6 @@ void board_lmb_reserve(struct lmb *lmb) } #endif
-void ft_srio_setup(void *blob) -{ -#ifdef CONFIG_SRIO1 - if (!is_serdes_configured(SRIO1)) { - fdt_del_node_and_alias(blob, "rio0"); - } -#else - fdt_del_node_and_alias(blob, "rio0"); -#endif -#ifdef CONFIG_SRIO2 - if (!is_serdes_configured(SRIO2)) { - fdt_del_node_and_alias(blob, "rio1"); - } -#else - fdt_del_node_and_alias(blob, "rio1"); -#endif -} - void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -242,8 +200,6 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
- ft_srio_setup(blob); - base = getenv_bootm_low(); size = getenv_bootm_size();
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e1cd1b0..d1ac756 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */
@@ -265,21 +266,21 @@ /* * RapidIO */ -#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* * General PCI
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8548cds/law.c | 5 +---- board/freescale/mpc8548cds/tlb.c | 9 ++++----- include/configs/MPC8548CDS.h | 15 ++++++++------- 3 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index e59fee8..5b6943d 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -57,9 +57,6 @@ struct law_entry law_table[] = { #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_RIO_MEM_PHYS - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -#endif };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 2267ad7..b2c1b31 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
/* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#endif + /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4c5b998..ececa38 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 2010 Freescale Semiconductor. + * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -40,10 +40,12 @@ #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif
+#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_RIO #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ @@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif
-#ifdef CONFIG_RIO /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY #define BRIDGE_ID 17
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8568mds/law.c | 3 +-- include/configs/MPC8568MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index e24b72b..c5cf7ba 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -50,7 +50,6 @@ */
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a491650..f684e79 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007, 2010 Freescale Semiconductor. + * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCIE1 1 /* PCIE controller */ @@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_QE /*
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8569mds/law.c | 3 +-- include/configs/MPC8569MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c index bcd0311..4f4a93b 100644 --- a/board/freescale/mpc8569mds/law.c +++ b/board/freescale/mpc8569mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -52,7 +52,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 814c175..3372d18 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
+#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ @@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_QE /*
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
arch/powerpc/cpu/mpc86xx/cpu_init.c | 7 ++++++- arch/powerpc/cpu/mpc86xx/fdt.c | 7 ++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index 1d35c0c..8022024 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -34,6 +34,7 @@ #include <asm/fsl_serdes.h> #include <asm/mp.h>
+extern void srio_init(void); void setup_bats(void);
DECLARE_GLOBAL_DATA_PTR; @@ -80,6 +81,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init();
+#ifdef CONFIG_SYS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index ff89ee5..61f5110 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,6 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob);
void ft_cpu_setup(void *blob, bd_t *bd) { @@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob); #endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4e60cbb..cc338e4 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1,7 +1,7 @@ /* * MPC86xx Internal Memory Map * - * Copyright 2004 Freescale Semiconductor + * Copyright 2004, 2011 Freescale Semiconductor * Jeff Brown (Jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -1205,6 +1205,8 @@ typedef struct ccsr_gur { #define MPC86xx_DEVDISR_PCI1 0x80000000 #define MPC86xx_DEVDISR_PCIE1 0x40000000 #define MPC86xx_DEVDISR_PCIE2 0x20000000 +#define MPC86xx_DEVDISR_SRIO 0x00080000 +#define MPC86xx_DEVDISR_RMSG 0x00040000 #define MPC86xx_DEVDISR_CPU0 0x00008000 #define MPC86xx_DEVDISR_CPU1 0x00004000 #define MPC86xx_RSTCR_HRST_REQ 0x00000002
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8641hpcn/law.c | 5 +---- include/configs/MPC8641HPCN.h | 30 +++++++++++++----------------- 2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 30a7b70..08f1eb2 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -53,9 +53,6 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif -#if defined(CONFIG_RIO) - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -#endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index fea0876..0cca603 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2010 Freescale Semiconductor. + * Copyright 2006, 2010-2011 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -57,18 +57,14 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe0000000
-/* - * set this to enable Rapid IO. PCI and RIO are mutually exclusive - */ -/*#define CONFIG_RIO 1*/ +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */
-#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -319,13 +315,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE #endif -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
/* * General PCI @@ -514,18 +510,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #endif
Signed-off-by: Kumar Gala galak@kernel.crashing.org Tested-by: Paul Gortmaker paul.gortmaker@windriver.com --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/sbc8641d/law.c | 1 - include/configs/sbc8641d.h | 15 +++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index a6f60ee..14259d6 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -51,7 +51,6 @@ struct law_entry law_table[] = { #endif SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 90d84eb..8d9f931 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -57,6 +57,9 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe8000000
+#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ @@ -297,9 +300,9 @@ /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
/* * General PCI @@ -417,10 +420,10 @@ * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
From: Li Yang leoli@freescale.com
The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code.
Signed-off-by: Li Yang leoli@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
include/configs/P2020DS.h | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 24f2498..c2636af 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -45,6 +45,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif
+#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -472,6 +476,24 @@ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif
+/* SRIO1 uses the same window as PCIE2 mem window */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +/* SRIO2 uses the same window as PCIE1 mem window */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
From: Li Yang leoli@freescale.com
The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code.
Signed-off-by: Li Yang leoli@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
include/configs/P2020DS.h | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-)
applied to 85xx
- k
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org Tested-by: Paul Gortmaker paul.gortmaker@windriver.com
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/sbc8641d/law.c | 1 - include/configs/sbc8641d.h | 15 +++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-)
applied to 85xx
- k
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8641hpcn/law.c | 5 +---- include/configs/MPC8641HPCN.h | 30 +++++++++++++----------------- 2 files changed, 14 insertions(+), 21 deletions(-)
applied to 85xx
- k
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
arch/powerpc/cpu/mpc86xx/cpu_init.c | 7 ++++++- arch/powerpc/cpu/mpc86xx/fdt.c | 7 ++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 3 files changed, 15 insertions(+), 3 deletions(-)
applied to 85xx
- k
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8569mds/law.c | 3 +-- include/configs/MPC8569MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
applied to 85xx
- k
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8568mds/law.c | 3 +-- include/configs/MPC8568MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
applied to 85xx
- k
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8548cds/law.c | 5 +---- board/freescale/mpc8548cds/tlb.c | 9 ++++----- include/configs/MPC8548CDS.h | 15 ++++++++------- 3 files changed, 13 insertions(+), 16 deletions(-)
applied to 85xx
- k
Dear Kumar Gala,
In message 1294733436-10264-1-git-send-email-galak@kernel.crashing.org you wrote:
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
- Added defines to README
README | 18 +++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +++- arch/powerpc/cpu/mpc85xx/fdt.c | 7 ++- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 23 ++++++++- arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + board/freescale/corenet_ds/corenet_ds.c | 44 ---------------- include/configs/corenet_ds.h | 19 ++++--- 9 files changed, 151 insertions(+), 56 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c
Acked-by: Wolfgang Denk wd@denx.de
Best regards,
Wolfgang Denk
On Jan 11, 2011, at 3:46 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1294733436-10264-1-git-send-email-galak@kernel.crashing.org you wrote:
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala galak@kernel.crashing.org
- Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
- Added defines to README
README | 18 +++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +++- arch/powerpc/cpu/mpc85xx/fdt.c | 7 ++- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 23 ++++++++- arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + board/freescale/corenet_ds/corenet_ds.c | 44 ---------------- include/configs/corenet_ds.h | 19 ++++--- 9 files changed, 151 insertions(+), 56 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c
Acked-by: Wolfgang Denk wd@denx.de
applied to 85xx
- k
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/mpc8569mds/law.c | 3 +-- include/configs/MPC8569MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
applied to 85xx
- k
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/mpc8568mds/law.c | 3 +-- include/configs/MPC8568MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
applied to 85xx
- k
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote:
Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/mpc8548cds/law.c | 5 +---- board/freescale/mpc8548cds/tlb.c | 9 ++++----- include/configs/MPC8548CDS.h | 15 ++++++++------- 3 files changed, 13 insertions(+), 16 deletions(-)
applied to 85xx
- k
participants (4)
-
Kumar Gala -
Paul Gortmaker -
Sergei Shtylyov -
Wolfgang Denk