[PATCH 0/2] arm: dts: Add Itap Delay Value For High Speed DDR
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC.
Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 + 2 files changed, 2 insertions(+)
DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for eMMC High Speed DDR which is DDR52 speed mode for J7200 SoC according to datasheet for J7200 [1].
[1] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in J7200 datasheet - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
Signed-off-by: Bhavya Kapoor b-kapoor@ti.com --- arch/arm/dts/k3-j7200-main.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index cdb1d6b2a9..18531ba803 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -647,6 +647,7 @@ ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; ti,strobe-sel = <0x77>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>;
DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2 [1].
[1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
Signed-off-by: Bhavya Kapoor b-kapoor@ti.com --- arch/arm/dts/k3-j721s2-main.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index 084f8f5b66..8a86f6ce8e 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -766,6 +766,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent;
Hi Bhavya!
On January 8, 2024 thus sayeth Bhavya Kapoor:
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC.
Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 +
Because of the periodic syncs with the kernel, modifying these dt files in U-Boot will cause confusion. (Which node is correct why did we have to do this in U-Boot and not in the Kernel... bla bla bla) If they absolutely need to go in now please override these nodes in the *-u-boot.dtsi files with a comment so we can keep track of these changes during the next sync with Linux.
~Bryan
On 08/01/24 7:35 pm, Bryan Brattlof wrote:
Hi Bhavya!
On January 8, 2024 thus sayeth Bhavya Kapoor:
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC.
Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 +
Because of the periodic syncs with the kernel, modifying these dt files in U-Boot will cause confusion. (Which node is correct why did we have to do this in U-Boot and not in the Kernel... bla bla bla) If they absolutely need to go in now please override these nodes in the *-u-boot.dtsi files with a comment so we can keep track of these changes during the next sync with Linux.
~Bryan
Hi Bryan, Fyi, This patch went in kernel as well.
Can be tracked below-
https://lore.kernel.org/all/170266085077.3490141.14935960940418963459.b4-ty@...
So , kernel and uboot dt files will remain in sync.
~B-Kapoor
On January 10, 2024 thus sayeth Bhavya Kapoor:
On 08/01/24 7:35 pm, Bryan Brattlof wrote:
Hi Bhavya!
On January 8, 2024 thus sayeth Bhavya Kapoor:
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC.
Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 +
Because of the periodic syncs with the kernel, modifying these dt files in U-Boot will cause confusion. (Which node is correct why did we have to do this in U-Boot and not in the Kernel... bla bla bla) If they absolutely need to go in now please override these nodes in the *-u-boot.dtsi files with a comment so we can keep track of these changes during the next sync with Linux.
~Bryan
Hi Bryan, Fyi, This patch went in kernel as well.
Can be tracked below-
https://lore.kernel.org/all/170266085077.3490141.14935960940418963459.b4-ty@...
So , kernel and uboot dt files will remain in sync.
Sorry I may be missing something. Why do we need these properties in U-Boot now? Why not wait 2 weeks for the v6.8-rc1 tag in Linux and sync everything all at once?
~Bryan
On 07:20-20240110, Bryan Brattlof wrote:
On January 10, 2024 thus sayeth Bhavya Kapoor:
On 08/01/24 7:35 pm, Bryan Brattlof wrote:
Hi Bhavya!
On January 8, 2024 thus sayeth Bhavya Kapoor:
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC.
Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 +
Because of the periodic syncs with the kernel, modifying these dt files in U-Boot will cause confusion. (Which node is correct why did we have to do this in U-Boot and not in the Kernel... bla bla bla) If they absolutely need to go in now please override these nodes in the *-u-boot.dtsi files with a comment so we can keep track of these changes during the next sync with Linux.
~Bryan
Hi Bryan, Fyi, This patch went in kernel as well.
Can be tracked below-
https://lore.kernel.org/all/170266085077.3490141.14935960940418963459.b4-ty@...
So , kernel and uboot dt files will remain in sync.
Sorry I may be missing something. Why do we need these properties in U-Boot now? Why not wait 2 weeks for the v6.8-rc1 tag in Linux and sync everything all at once?
I agree. NAK for the series. Please get this part of dts sync.
participants (3)
-
Bhavya Kapoor -
Bryan Brattlof -
Nishanth Menon