[PATCH v2] arm: dts: Aspeed: add Bletchley dts

Initial introduction of Bletchley equipped with Aspeed 2600 BMC SoC.
Signed-off-by: Potin Lai potin.lai@quantatw.com
---
Change since v1: - Disable mdio0, mdio1, mdio2 - Remove mac0, mac1, mac3 (keep disabled) - Enable mac2, and set to fixed-link --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/ast2600-bletchley.dts | 285 +++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-bletchley.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df844065cd..a172a9f8c6 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -685,7 +685,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-rainier.dtb \ ast2600-slt.dtb \ ast2600-tacoma.dtb \ - ast2600-intel.dtb + ast2600-intel.dtb \ + ast2600-bletchley.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
diff --git a/arch/arm/dts/ast2600-bletchley.dts b/arch/arm/dts/ast2600-bletchley.dts new file mode 100644 index 0000000000..ec14898400 --- /dev/null +++ b/arch/arm/dts/ast2600-bletchley.dts @@ -0,0 +1,285 @@ +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "AST2600 EVB"; + compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + mmc0 = &emmc_slot0; + mmc1 = &sdhci_slot0; + mmc2 = &sdhci_slot1; + spi0 = &fmc; + spi1 = &spi1; + spi2 = &spi2; + ethernet0 = &mac0; + ethernet1 = &mac1; + ethernet2 = &mac2; + ethernet3 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&mac2 { + status = "okay"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default &pinctrl_mac3link_default>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&fmc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fmcquad_default>; + + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@2 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&spi1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default + &pinctrl_spi1cs1_default &pinctrl_spi1wp_default + &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; + + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&spi2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default + &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; + + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@2 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&emmc { + u-boot,dm-pre-reloc; + timing-phase = <0x700ff>; +}; + +&emmc_slot0 { + u-boot,dm-pre-reloc; + status = "okay"; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_default>; + sdhci-drive-type = <1>; +}; + +&sdhci { + timing-phase = <0xc6ffff>; +}; + +&sdhci_slot0 { + status = "okay"; + bus-width = <4>; + pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_default>; + sdhci-drive-type = <1>; +}; + +&sdhci_slot1 { + status = "okay"; + bus-width = <4>; + pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + sdhci-drive-type = <1>; +}; + +&i2c4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; +}; + +&i2c5 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; +}; + +&i2c6 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; +}; + +&i2c7 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; +}; + +&i2c8 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; + +&pcie_bridge1 { + status = "okay"; +}; + +&h2x { + status = "okay"; +}; + +#if 0 +&fsim0 { + status = "okay"; +}; + +&fsim1 { + status = "okay"; +}; +#endif + +&ehci1 { + status = "okay"; +}; + +&display_port { + status = "okay"; +}; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac1-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac2-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; + mac3-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; +}; + +&hace { + status = "okay"; +};

On Tue, Jan 04, 2022 at 06:03:17PM +0800, Potin Lai wrote:
Initial introduction of Bletchley equipped with Aspeed 2600 BMC SoC.
Signed-off-by: Potin Lai potin.lai@quantatw.com
Change since v1:
- Disable mdio0, mdio1, mdio2
- Remove mac0, mac1, mac3 (keep disabled)
- Enable mac2, and set to fixed-link
arch/arm/dts/Makefile | 3 +- arch/arm/dts/ast2600-bletchley.dts | 285 +++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-bletchley.dts
Reviewed-by: Patrick Williams patrick@stwcx.xyz

On Tue, Jan 04, 2022 at 06:03:17PM +0800, Potin Lai wrote:
Initial introduction of Bletchley equipped with Aspeed 2600 BMC SoC.
Signed-off-by: Potin Lai potin.lai@quantatw.com Reviewed-by: Patrick Williams patrick@stwcx.xyz
Change since v1:
- Disable mdio0, mdio1, mdio2
- Remove mac0, mac1, mac3 (keep disabled)
- Enable mac2, and set to fixed-link
arch/arm/dts/Makefile | 3 +- arch/arm/dts/ast2600-bletchley.dts | 285 +++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-bletchley.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df844065cd..a172a9f8c6 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -685,7 +685,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-rainier.dtb \ ast2600-slt.dtb \ ast2600-tacoma.dtb \
- ast2600-intel.dtb
- ast2600-intel.dtb \
- ast2600-bletchley.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
Does this depend on other changes that I missed? We don't have those lines in the Makefile today, thanks.

Hi Tom, Thank you for the reply. It looks like some of changes are only appeared in openbmc u-boot repo.
Hi Joel, Could you advise how to send the patch to openbmc u-boot repo? Thank you.
BRs, Potin -----Original Message----- From: Tom Rini trini@konsulko.com Sent: Wednesday, January 19, 2022 1:48 AM To: Potin Lai (賴柏廷) Potin.Lai@quantatw.com Cc: Albert Aribaud albert.u.boot@aribaud.net; Chia-Wei, Wang chiawei_wang@aspeedtech.com; Dylan Hung dylan_hung@aspeedtech.com; Klaus Heinrich Kiwi klaus@linux.vnet.ibm.com; Joel Stanley joel@jms.id.au; Patrick Williams patrick@stwcx.xyz; u-boot@lists.denx.de Subject: Re: [PATCH v2] arm: dts: Aspeed: add Bletchley dts
On Tue, Jan 04, 2022 at 06:03:17PM +0800, Potin Lai wrote:
Initial introduction of Bletchley equipped with Aspeed 2600 BMC SoC.
Signed-off-by: Potin Lai potin.lai@quantatw.com Reviewed-by: Patrick Williams patrick@stwcx.xyz
Change since v1:
- Disable mdio0, mdio1, mdio2
- Remove mac0, mac1, mac3 (keep disabled)
- Enable mac2, and set to fixed-link
arch/arm/dts/Makefile | 3 +- arch/arm/dts/ast2600-bletchley.dts | 285 +++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-bletchley.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df844065cd..a172a9f8c6 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -685,7 +685,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-rainier.dtb \ ast2600-slt.dtb \ ast2600-tacoma.dtb \
- ast2600-intel.dtb
- ast2600-intel.dtb \
- ast2600-bletchley.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
Does this depend on other changes that I missed? We don't have those lines in the Makefile today, thanks.
-- Tom
participants (4)
-
Patrick Williams
-
Potin Lai
-
Potin Lai (賴柏廷)
-
Tom Rini