[U-Boot] [PATCH V3 0/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements
Hi,
The third incarnation of this series to address various ideas of previous V2 series. I will skip the full blurb and point to V1/V2 links for the usual blurb.
Changes since V2: - Added documentation revisioning info with ARM erratums - patch series are split up to address ARM erratums first followed by TI OMAP conversion - More OMAP3 now get erratum implementation - had to redo rx51 a little - I think is better helps exynos: https://patchwork.ozlabs.org/patch/443271/ https://patchwork.ozlabs.org/patch/441863/ - Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
README | 8 +++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/cp15.c | 29 ++++++++++ arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 15 +++-- arch/arm/cpu/armv7/omap3/board.c | 60 +++++++------------- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 ---- arch/arm/cpu/armv7/omap4/hwinit.c | 4 +- arch/arm/cpu/armv7/omap5/hwinit.c | 23 ++++++++ arch/arm/cpu/armv7/start.S | 53 +++++++++++++++++ .../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 arch/arm/include/asm/arch-omap3/sys_proto.h | 3 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 4 ++ arch/arm/include/asm/armv7.h | 5 ++ board/nokia/rx51/rx51.c | 19 ++++--- include/configs/am3517_crane.h | 6 +- include/configs/am3517_evm.h | 6 +- include/configs/cm_t35.h | 6 +- include/configs/cm_t3517.h | 6 +- include/configs/dig297.h | 6 +- include/configs/mcx.h | 6 +- include/configs/nokia_rx51.h | 6 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_common.h | 4 ++ include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 6 +- include/configs/omap3_mvblx.h | 6 +- include/configs/omap3_pandora.h | 6 +- include/configs/omap3_sdp3430.h | 6 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 6 +- include/configs/tao3530.h | 6 +- include/configs/ti_omap3_common.h | 7 ++- include/configs/ti_omap5_common.h | 3 + include/configs/tricorder.h | 6 +- 37 files changed, 262 insertions(+), 87 deletions(-) create mode 100644 arch/arm/cpu/armv7/cp15.c rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
Regards, Nishanth Menon
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 5 +++++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/cp15.c | 23 +++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 20 ++++++++++++++++++++ arch/arm/include/asm/armv7.h | 3 +++ 5 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/cp15.c
diff --git a/README b/README index a28ff133ee05..11ec37ba4a00 100644 --- a/README +++ b/README @@ -621,6 +621,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply!
+ NOTE: The following can be machine specific errata. These + do have ability to provide rudimentary version and machine + specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_798870 + - Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 409e6f5651b6..43da3e586f71 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -9,7 +9,7 @@ extra-y := start.o
obj-y += cache_v7.o
-obj-y += cpu.o +obj-y += cpu.o cp15.o obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c new file mode 100644 index 000000000000..8ac81c9ba147 --- /dev/null +++ b/arch/arm/cpu/armv7/cp15.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2015 Texas Insturments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CP15 specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/system.h> +#include <asm/cache.h> +#include <asm/armv7.h> +#include <linux/compiler.h> + +void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr)); +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 70048c10aee6..ec46cec9cb1c 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -163,6 +163,26 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
+ mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) + mov r3, r1, lsr #20 @ get variant field + and r3, r3, #0xf @ r3 has CPU variant + and r4, r1, #0xf @ r4 has CPU revision + mov r2, r3, lsl #4 @ shift variant field for combined value + orr r2, r4, r2 @ r2 has combined CPU variant + revision + +#ifdef CONFIG_ARM_ERRATA_798870 + cmp r2, #0x30 @ Applies to lower than R3p0 + bge skip_errata_798870 @ skip if not affected rev + cmp r2, #0x20 @ Applies to including and above R2p0 + blt skip_errata_798870 @ skip if not affected rev + + mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg + orr r0, r0, #1 << 7 @ Enable hazard-detect timeout + b v7_arch_cp15_set_l2aux_ctrl + isb @ Recommended ISB after l2actlr update +skip_errata_798870: +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23cf172..30e0cc3cf3d5 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -93,6 +93,9 @@ extern char __secure_end[];
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev); #endif /* ! __ASSEMBLY__ */
#endif
On 02/25/2015 02:55 PM, Nishanth Menon wrote:
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon nm@ti.com
README | 5 +++++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/cp15.c | 23 +++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 20 ++++++++++++++++++++ arch/arm/include/asm/armv7.h | 3 +++ 5 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/cp15.c
diff --git a/README b/README index a28ff133ee05..11ec37ba4a00 100644 --- a/README +++ b/README @@ -621,6 +621,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply!
NOTE: The following can be machine specific errata. Thesedo have ability to provide rudimentary version and machinespecific checks, but expect no product checks.CONFIG_ARM_ERRATA_798870
- Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 409e6f5651b6..43da3e586f71 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -9,7 +9,7 @@ extra-y := start.o
obj-y += cache_v7.o
-obj-y += cpu.o +obj-y += cpu.o cp15.o obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c new file mode 100644 index 000000000000..8ac81c9ba147 --- /dev/null +++ b/arch/arm/cpu/armv7/cp15.c @@ -0,0 +1,23 @@ +/*
- (C) Copyright 2015 Texas Insturments
- SPDX-License-Identifier: GPL-2.0+
- */
+/*
- CP15 specific code
- */
+#include <common.h> +#include <command.h> +#include <asm/system.h> +#include <asm/cache.h> +#include <asm/armv7.h> +#include <linux/compiler.h>
+void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
u32 cpu_rev_comb, u32 cpu_variant,u32 cpu_rev)+{
- asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
+} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 70048c10aee6..ec46cec9cb1c 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -163,6 +163,26 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
- mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
- mov r3, r1, lsr #20 @ get variant field
- and r3, r3, #0xf @ r3 has CPU variant
- and r4, r1, #0xf @ r4 has CPU revision
- mov r2, r3, lsl #4 @ shift variant field for combined value
- orr r2, r4, r2 @ r2 has combined CPU variant + revision
I think I should move these to beyond r3 as r0-r3 could be corrupted in c invocation OR SMC invocation...
+#ifdef CONFIG_ARM_ERRATA_798870
- cmp r2, #0x30 @ Applies to lower than R3p0
- bge skip_errata_798870 @ skip if not affected rev
- cmp r2, #0x20 @ Applies to including and above R2p0
- blt skip_errata_798870 @ skip if not affected rev
- mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
- orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
- b v7_arch_cp15_set_l2aux_ctrl
- isb @ Recommended ISB after l2actlr update
+skip_errata_798870: +#endif
- mov pc, lr @ back to my caller
ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23cf172..30e0cc3cf3d5 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -93,6 +93,9 @@ extern char __secure_end[];
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
u32 cpu_rev_comb, u32 cpu_variant,u32 cpu_rev);#endif /* ! __ASSEMBLY__ */
#endif
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/cp15.c | 6 ++++++ arch/arm/cpu/armv7/start.S | 11 +++++++++++ arch/arm/include/asm/armv7.h | 2 ++ 4 files changed, 20 insertions(+)
diff --git a/README b/README index 11ec37ba4a00..e538cf061286 100644 --- a/README +++ b/README @@ -624,6 +624,7 @@ The following options need to be configured: NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_798870
- Driver Model diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index 8ac81c9ba147..b44c9f94a822 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr, { asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr)); } + +void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr)); +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ec46cec9cb1c..1f20e12b92f9 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -183,6 +183,17 @@ ENTRY(cpu_init_cp15) skip_errata_798870: #endif
+#ifdef CONFIG_ARM_ERRATA_454179 + cmp r2, #0x21 @ Only on < r2p1 + blt skip_errata_454179 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits + b v7_arch_cp15_set_acr + +skip_errata_454179: +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 30e0cc3cf3d5..434b34de0ce9 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -96,6 +96,8 @@ extern char __secure_end[]; void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, u32 cpu_rev_comb, u32 cpu_variant, u32 cpu_rev); +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev); #endif /* ! __ASSEMBLY__ */
#endif
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/start.S | 11 +++++++++++ 2 files changed, 12 insertions(+)
diff --git a/README b/README index e538cf061286..484ae9ee39a8 100644 --- a/README +++ b/README @@ -624,6 +624,7 @@ The following options need to be configured: NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_430973 CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_798870
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 1f20e12b92f9..45e8578db60c 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -194,6 +194,17 @@ skip_errata_798870: skip_errata_454179: #endif
+#ifdef CONFIG_ARM_ERRATA_430973 + cmp r2, #0x21 @ Only on < r2p1 + blt skip_errata_430973 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x1 << 6) @ Set IBE bit + b v7_arch_cp15_set_acr + +skip_errata_430973: +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/start.S | 11 +++++++++++ 2 files changed, 12 insertions(+)
diff --git a/README b/README index 484ae9ee39a8..5ee789aea627 100644 --- a/README +++ b/README @@ -626,6 +626,7 @@ The following options need to be configured: specific checks, but expect no product checks. CONFIG_ARM_ERRATA_430973 CONFIG_ARM_ERRATA_454179 + CONFIG_ARM_ERRATA_621766 CONFIG_ARM_ERRATA_798870
- Driver Model diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 45e8578db60c..2d92276a0475 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -205,6 +205,17 @@ skip_errata_454179: skip_errata_430973: #endif
+#ifdef CONFIG_ARM_ERRATA_621766 + cmp r2, #0x21 @ Only on < r2p1 + blt skip_errata_621766 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x1 << 5) @ Set L1NEON bit + b v7_arch_cp15_set_acr + +skip_errata_621766: +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 ++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e4217478..9b24369e4dc1 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,14 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg) - PUSH {r4-r11, lr} @ save registers - ROM code may pollute +ENTRY(omap_smc1) + PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers - LDR r12, =0x102 @ Set PL310 control register - value in R0 + MOV r12, r0 @ Service + MOV r0, r1 @ Argument + DSB + DMB .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register - POP {r4-r11, pc} -ENDPROC(set_pl310_ctrl_reg) + POP {r4-r12, pc} +ENDPROC(omap_smc1) diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index db16548fac49..9792761d40a0 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -159,11 +159,11 @@ void init_omap_revision(void) #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { - set_pl310_ctrl_reg(1); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); }
void v7_outer_cache_disable(void) { - set_pl310_ctrl_reg(0); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index e19975efaf50..f425e3af54f5 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void set_pl310_ctrl_reg(u32 val); +void omap_smc1(u32 service, u32 val); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 const base); @@ -57,4 +57,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); + +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 + #endif
On Wed, Feb 25, 2015 at 02:55:13PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 ++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e4217478..9b24369e4dc1 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,14 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ENTRY(omap_smc1)
- PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- MOV r12, r0 @ Service
- MOV r0, r1 @ Argument
- DSB
- DMB .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register
Lets stop hand-crafting that call, we just call smc #0 elsewhere in the code base these days.
On 03/03/2015 11:08 AM, Tom Rini wrote:
On Wed, Feb 25, 2015 at 02:55:13PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 ++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e4217478..9b24369e4dc1 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,14 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ENTRY(omap_smc1)
- PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- MOV r12, r0 @ Service
- MOV r0, r1 @ Argument
- DSB
- DMB .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register
Lets stop hand-crafting that call, we just call smc #0 elsewhere in the code base these days.
And we dont care about: -march=armv5 any-longer?
On 03/03/2015 11:12 AM, Nishanth Menon wrote:
On 03/03/2015 11:08 AM, Tom Rini wrote:
On Wed, Feb 25, 2015 at 02:55:13PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 ++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e4217478..9b24369e4dc1 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,14 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ENTRY(omap_smc1)
- PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- MOV r12, r0 @ Service
- MOV r0, r1 @ Argument
- DSB
- DMB .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register
Lets stop hand-crafting that call, we just call smc #0 elsewhere in the code base these days.
And we dont care about: -march=armv5 any-longer?
:( replacing this - causes build breakage:
Building omap3_overo board... arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' make[2]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1 make[1]: *** [arch/arm/cpu/armv7/omap-common] Error 2 make: *** [arch/arm/cpu/armv7] Error 2 arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' make[2]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [arch/arm/cpu/armv7/omap-common] Error 2 make: *** [arch/arm/cpu/armv7] Error 2 make: *** Waiting for unfinished jobs....
I will retain the hand assembled value for now, if that is ok?
On Tue, Mar 03, 2015 at 11:12:33AM -0600, Nishanth Menon wrote:
On 03/03/2015 11:08 AM, Tom Rini wrote:
On Wed, Feb 25, 2015 at 02:55:13PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 ++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e4217478..9b24369e4dc1 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,14 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ENTRY(omap_smc1)
- PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- MOV r12, r0 @ Service
- MOV r0, r1 @ Argument
- DSB
- DMB .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register
Lets stop hand-crafting that call, we just call smc #0 elsewhere in the code base these days.
And we dont care about: -march=armv5 any-longer?
No, that's not a use-case for these boards any longer, toolchains old enough to not know -march=armv7t are going to have other problems.
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon nm@ti.com --- .../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/cm_t3517.h | 2 +- include/configs/dig297.h | 2 +- include/configs/mcx.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_mvblx.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tao3530.h | 2 +- include/configs/ti_omap3_common.h | 2 +- include/configs/tricorder.h | 2 +- 20 files changed, 19 insertions(+), 19 deletions(-) rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap.h similarity index 100% rename from arch/arm/include/asm/arch-omap3/omap3.h rename to arch/arm/include/asm/arch-omap3/omap.h diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 09ee10c0590b..a4128773ddb2 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 190ef0e71bfb..94398c625eb0 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 9767512a5cf0..56a5506f5c78 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -30,7 +30,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 918032bd753a..ee1b7a0cb5a7 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -30,7 +30,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/dig297.h b/include/configs/dig297.h index c8739ed29490..8791199fc61d 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -36,7 +36,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 26eb2203540f..2cf66c40d6fe 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -26,7 +26,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_OF_LIBFDT #define CONFIG_FIT diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 46fc91e5e197..442e16ae686b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -42,7 +42,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <asm/arch/mem.h> #include <linux/stringify.h>
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bdc08f5864c..4e587e10ffd3 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -18,7 +18,7 @@ #define __OMAP3EVM_CONFIG_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 1185f425501f..a7acc1becbeb 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 4427e88b7e4b..c6cad9388961 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_NAND_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index aeb385f5ff6b..fcef46735835 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -24,7 +24,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index bf1d34dedb4d..20ec3ad15439 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 45feeb577320..b92d67abccf9 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -21,7 +21,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index ac307eb45629..bf5c7a8faf77 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * NOTE: these #defines presume standard SDP jumper settings. diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c5d742c2bd80..611cd5e1a350 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -22,7 +22,7 @@ #define CONFIG_NAND #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 9fbe68a8a2f2..bff9687b3c9c 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -25,7 +25,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 7d2c0d2fa75c..4dfd5cb9fbb7 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3c634ee680d0..f909f6b94a18 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -16,7 +16,7 @@
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#ifndef CONFIG_SPL_BUILD # define CONFIG_DM diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 36621a553cdf..f27cd1b9b061 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -32,7 +32,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_SYS_GENERIC_BOARD
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 2 ++ arch/arm/cpu/armv7/omap3/board.c | 6 ++---- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 ----------- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- 5 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 7695e16d36f5..f3725b267c99 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,7 @@ endif
ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o -obj-y += lowlevel_init.o endif +obj-y += lowlevel_init.o
obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 9b24369e4dc1..7d0f09496d85 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,11 +16,13 @@ #include <asm/arch/spl.h> #include <linux/linkage.h>
+#ifndef CONFIG_OMAP34XX ENTRY(save_boot_params) ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] bx lr ENDPROC(save_boot_params) +#endif
ENTRY(omap_smc1) PUSH {r4-r12, lr} @ save registers - ROM code may pollute diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7bb5f5..51abc4b09e36 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -418,8 +418,7 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) acr |= set_bits;
if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, - acr); + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; @@ -459,8 +458,7 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) static void omap3_invalidate_l2_cache_secure(void) { if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, - 0); + omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 78577b1d1c75..84591b8b5bab 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -27,17 +27,6 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) #endif
-ENTRY(omap3_gp_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Service ID in R12 - MOV r0, r1 @ Copy parameter to R0 - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(omap3_gp_romcode_call) - /* * Funtion for making PPA HAL API calls in secure devices * Input: diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index bcf92fbe658b..c06605d533d3 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -73,6 +73,6 @@ void power_init_r(void); void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); +void omap_smc1(u32 service, u32 val); u32 warm_reset(void); #endif
From: Praveen Rao prao@ti.com
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well.
Signed-off-by: Praveen Rao prao@ti.com Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 7 +++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 4 ++++ include/configs/ti_omap5_common.h | 3 +++ 3 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index a8a474a88be9..f8060555b680 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -381,3 +381,10 @@ void setup_warmreset_time(void) rst_val |= rst_time; writel(rst_val, (*prcm)->prm_rsttime); } + +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); +} diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 103830319a41..37dc9925eae2 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -66,4 +66,8 @@ static inline u32 usec_to_32k(u32 usec) { return div_round_up(32768 * usec, 1000000); } + +void omap_smc1(u32 service, u32 val); +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + #endif diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 925cb42dd38d..09f05f18a75d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -21,6 +21,9 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT
+/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_798870 + #define CONFIG_SYS_CACHELINE_SIZE 64
/* Use General purpose timer 1 */
Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalvala@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index f8060555b680..8d6b59eeb044 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base) (*ctrl)->control_emif2_sdram_config_ext); }
+void init_cpu_configuration(void) +{ + u32 l2actlr; + + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); + /* + * L2ACTLR: Ensure to enable the following: + * 3: Disable clean/evict push to external + * 4: Disable WriteUnique and WriteLineUnique transactions from master + * 8: Disable DVM/CMO message broadcast + */ + l2actlr |= 0x118; + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); +} + void init_omap_revision(void) { /* @@ -342,6 +357,7 @@ void init_omap_revision(void) default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } + init_cpu_configuration(); }
void reset_cpu(ulong ignored)
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap3/board.c | 31 ++++++++++--------------------- include/configs/am3517_crane.h | 4 ++++ include/configs/am3517_evm.h | 4 ++++ include/configs/cm_t35.h | 4 ++++ include/configs/cm_t3517.h | 4 ++++ include/configs/dig297.h | 4 ++++ include/configs/mcx.h | 4 ++++ include/configs/omap3_evm_common.h | 4 ++++ include/configs/omap3_logic.h | 4 ++++ include/configs/omap3_mvblx.h | 4 ++++ include/configs/omap3_pandora.h | 4 ++++ include/configs/omap3_sdp3430.h | 4 ++++ include/configs/tam3517-common.h | 4 ++++ include/configs/tao3530.h | 4 ++++ include/configs/ti_omap3_common.h | 5 +++++ include/configs/tricorder.h | 4 ++++ 16 files changed, 71 insertions(+), 21 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 51abc4b09e36..5587a10cdafd 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */ - omap3_setup_aux_cr(); - #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -408,15 +404,9 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) { - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - if (get_device_type() == GP_DEVICE) { omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); } else { @@ -428,16 +418,15 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) +static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); }
#ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index a4128773ddb2..39e121d9bc99 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -19,6 +19,10 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 94398c625eb0..930d7af31f18 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,6 +19,10 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 56a5506f5c78..451cb5e2fb4f 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -26,6 +26,10 @@ #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index ee1b7a0cb5a7..8c6313832250 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -17,6 +17,10 @@ #define CONFIG_CM_T3517 /* working with CM-T3517 */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 8791199fc61d..932640112b3a 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -23,6 +23,10 @@ #define MACH_TYPE_OMAP3_CPS 2751 #endif #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
/* * High Level Configuration Options diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 2cf66c40d6fe..3fd31842451d 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -16,6 +16,10 @@ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 8885e1758106..aeb769548f92 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -15,6 +15,10 @@ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index fcef46735835..13cd35b16a03 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -18,6 +18,10 @@ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80400000
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 20ec3ad15439..b61297f9ee94 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -23,6 +23,10 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index b92d67abccf9..11d7b86eb10d 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -17,6 +17,10 @@ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index bf5c7a8faf77..1ca79d4ee4dd 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -23,6 +23,10 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index bff9687b3c9c..af259e20bbd2 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -17,6 +17,10 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 4dfd5cb9fbb7..634b441b5768 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -21,6 +21,10 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_OMAP3_TAO3530 2836
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..22f103c8dd8c 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,6 +27,11 @@ # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif
+/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 + /* The chip has SDRC controller */ #define CONFIG_SDRC
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index f27cd1b9b061..1954e62b4097 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -19,6 +19,10 @@ /* High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /*
RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap3/board.c | 45 ++++++++++++--------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + board/nokia/rx51/rx51.c | 19 ++++++----- include/configs/nokia_rx51.h | 4 +++ 4 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 5587a10cdafd..bfbc197bf99c 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -404,31 +404,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, - u32 cpu_variant, u32 cpu_rev) +void __weak omap3_set_aux_cr_secure(u32 acr) { - if (get_device_type() == GP_DEVICE) { - omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = acr; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); - } + struct emu_hal_params emu_romcode_params; + + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = acr; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) { - u32 acr; + /* Write ACR - affects secure banked bits */ + if (get_device_type() == GP_DEVICE) + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); + else + omap3_set_aux_cr_secure(acr);
- /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); + /* Write ACR - affects non-secure banked bits - some erratas need it */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); }
+ #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { @@ -438,9 +437,8 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
- /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); }
/* Invalidate the entire L2 cache from secure mode */ @@ -459,10 +457,9 @@ static void omap3_invalidate_l2_cache_secure(void)
void v7_outer_cache_enable(void) { - /* Set L2EN */ - omap3_update_aux_cr_secure(0x2, 0);
/* + * Set L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in setting both banked bits(in fact this is required * by an erratum) @@ -472,10 +469,8 @@ void v7_outer_cache_enable(void)
void omap3_outer_cache_disable(void) { - /* Clear L2EN */ - omap3_update_aux_cr_secure(0, 0x2); - /* + * Clear L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in clearing both banked bits(in fact this is required * by an erratum) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index c06605d533d3..ff1bf736cf06 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,5 +74,6 @@ void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap_smc1(u32 service, u32 val); +void omap3_set_aux_cr_secure(u32 acr); u32 warm_reset(void); #endif diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 08fcaf21b3c6..3d019b01428b 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
+void omap3_set_aux_cr_secure(u32 acr) +{ + struct emu_hal_params_rx51 emu_romcode_params = { 0, }; + + emu_romcode_params.num_params = 2; + emu_romcode_params.param1 = acr; + + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); +} + /* * Routine: omap3_update_aux_cr_secure_rx51 * Description: Modify the contents Auxiliary Control Register. @@ -350,19 +361,13 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) */ static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) { - struct emu_hal_params_rx51 emu_romcode_params = { 0, }; u32 acr;
/* Read ACR */ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; - - emu_romcode_params.num_params = 2; - emu_romcode_params.param1 = acr; - - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); + omap3_set_aux_cr_secure(acr); }
/* diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 442e16ae686b..152a6e564b00 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -29,6 +29,10 @@ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
On Wed, 25 Feb 2015 14:55:08 -0600 Nishanth Menon nm@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of previous V2 series. I will skip the full blurb and point to V1/V2 links for the usual blurb.
Changes since V2:
- Added documentation revisioning info with ARM erratums
- patch series are split up to address ARM erratums first followed by TI OMAP conversion
- More OMAP3 now get erratum implementation - had to redo rx51 a little
- I think is better helps exynos: https://patchwork.ozlabs.org/patch/443271/ https://patchwork.ozlabs.org/patch/441863/
- Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
Could you perhaps also pick up a workaround for "725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock" for old OMAP3 (r1pX revision of Cortex-A8)?
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=041d42e789aba20296ffcde92173...
This used to be in U-Boot earlier, but seems to have vanished from the current U-Boot code. I would probably submit a patch myself, but I don't have such hardware anymore to test it.
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600 Nishanth Menon nm@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of previous V2 series. I will skip the full blurb and point to V1/V2 links for the usual blurb.
Changes since V2: - Added documentation revisioning info with ARM erratums - patch series are split up to address ARM erratums first followed by TI OMAP conversion - More OMAP3 now get erratum implementation - had to redo rx51 a little - I think is better helps exynos: https://patchwork.ozlabs.org/patch/443271/ https://patchwork.ozlabs.org/patch/441863/ - Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
Could you perhaps also pick up a workaround for "725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock" for old OMAP3 (r1pX revision of Cortex-A8)?
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=041d42e789aba20296ffcde92173f100a9592880This used to be in U-Boot earlier, but seems to have vanished from the current U-Boot code. I would probably submit a patch myself, but I don't have such hardware anymore to test it.
Could I have a review by - I think I screwed up r1-r3 handling in start.S when multiple erratas are enabled - which by some luck, I have'nt hit.. I should probably fix that.
I will hold off adding more erratas or changes for now and look for the current series getting in.. in fact, I am tempted to remove omap3 entirely from this list for now, given the multiple platforms impacted and unless folks are willing to help test those, I am more than happy to just focus on a15 erratum in the first series which benefits my immediate needs and potentially helping exynos as well.
On Thu, 26 Feb 2015 08:50:09 -0600 Nishanth Menon nm@ti.com wrote:
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600 Nishanth Menon nm@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of previous V2 series. I will skip the full blurb and point to V1/V2 links for the usual blurb.
Changes since V2: - Added documentation revisioning info with ARM erratums - patch series are split up to address ARM erratums first followed by TI OMAP conversion - More OMAP3 now get erratum implementation - had to redo rx51 a little - I think is better helps exynos: https://patchwork.ozlabs.org/patch/443271/ https://patchwork.ozlabs.org/patch/441863/ - Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
Could you perhaps also pick up a workaround for "725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock" for old OMAP3 (r1pX revision of Cortex-A8)?
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=041d42e789aba20296ffcde92173f100a9592880This used to be in U-Boot earlier, but seems to have vanished from the current U-Boot code. I would probably submit a patch myself, but I don't have such hardware anymore to test it.
Could I have a review by - I think I screwed up r1-r3 handling in start.S when multiple erratas are enabled - which by some luck, I have'nt hit.. I should probably fix that.
Sadly, I don't have this old hardware anymore. I have lent my first generation beagleboard to another person several years ago and have no idea where it is now. Maybe I should try to get it back one day :)
But taking the "formal" route, I checked who is the current beagleboard maintainer and looks like that's Tom Rini, who is already quite conveniently in the CC ;-)
Basically, this old hardware is either maintained or not. If it is maintained, then probably the board maintainer is the best person to review and test the errata patches.
I will hold off adding more erratas or changes for now and look for the current series getting in.. in fact, I am tempted to remove omap3 entirely from this list for now, given the multiple platforms impacted and unless folks are willing to help test those, I am more than happy to just focus on a15 erratum in the first series which benefits my immediate needs and potentially helping exynos as well.
On Thu, Feb 26, 2015 at 06:14:25PM +0200, Siarhei Siamashka wrote:
On Thu, 26 Feb 2015 08:50:09 -0600 Nishanth Menon nm@ti.com wrote:
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600 Nishanth Menon nm@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of previous V2 series. I will skip the full blurb and point to V1/V2 links for the usual blurb.
Changes since V2: - Added documentation revisioning info with ARM erratums - patch series are split up to address ARM erratums first followed by TI OMAP conversion - More OMAP3 now get erratum implementation - had to redo rx51 a little - I think is better helps exynos: https://patchwork.ozlabs.org/patch/443271/ https://patchwork.ozlabs.org/patch/441863/ - Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
Could you perhaps also pick up a workaround for "725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock" for old OMAP3 (r1pX revision of Cortex-A8)?
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=041d42e789aba20296ffcde92173f100a9592880This used to be in U-Boot earlier, but seems to have vanished from the current U-Boot code. I would probably submit a patch myself, but I don't have such hardware anymore to test it.
Could I have a review by - I think I screwed up r1-r3 handling in start.S when multiple erratas are enabled - which by some luck, I have'nt hit.. I should probably fix that.
Sadly, I don't have this old hardware anymore. I have lent my first generation beagleboard to another person several years ago and have no idea where it is now. Maybe I should try to get it back one day :)
But taking the "formal" route, I checked who is the current beagleboard maintainer and looks like that's Tom Rini, who is already quite conveniently in the CC ;-)
Basically, this old hardware is either maintained or not. If it is maintained, then probably the board maintainer is the best person to review and test the errata patches.
Picking up again, I have original Beagleboards but I need a testcase. Is it as simple as "Linux still boots to login on serial and doesn't segfault everywhere" ?
On Mon, 2 Mar 2015 16:16:08 -0500 Tom Rini trini@konsulko.com wrote:
On Thu, Feb 26, 2015 at 06:14:25PM +0200, Siarhei Siamashka wrote:
On Thu, 26 Feb 2015 08:50:09 -0600 Nishanth Menon nm@ti.com wrote:
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600 Nishanth Menon nm@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of previous V2 series. I will skip the full blurb and point to V1/V2 links for the usual blurb.
Changes since V2: - Added documentation revisioning info with ARM erratums - patch series are split up to address ARM erratums first followed by TI OMAP conversion - More OMAP3 now get erratum implementation - had to redo rx51 a little - I think is better helps exynos: https://patchwork.ozlabs.org/patch/443271/ https://patchwork.ozlabs.org/patch/441863/ - Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
Could you perhaps also pick up a workaround for "725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock" for old OMAP3 (r1pX revision of Cortex-A8)?
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=041d42e789aba20296ffcde92173f100a9592880This used to be in U-Boot earlier, but seems to have vanished from the current U-Boot code. I would probably submit a patch myself, but I don't have such hardware anymore to test it.
Could I have a review by - I think I screwed up r1-r3 handling in start.S when multiple erratas are enabled - which by some luck, I have'nt hit.. I should probably fix that.
Sadly, I don't have this old hardware anymore. I have lent my first generation beagleboard to another person several years ago and have no idea where it is now. Maybe I should try to get it back one day :)
But taking the "formal" route, I checked who is the current beagleboard maintainer and looks like that's Tom Rini, who is already quite conveniently in the CC ;-)
Basically, this old hardware is either maintained or not. If it is maintained, then probably the board maintainer is the best person to review and test the errata patches.
Picking up again, I have original Beagleboards but I need a testcase. Is it as simple as "Linux still boots to login on serial and doesn't segfault everywhere" ?
In one way, this can be verified by just checking that the necessary bits in the system registers are properly set according to the recommendations from the errata lists. AFAIK, only writes to these registers are restricted, so that it has to be done in an OMAP specific way using the SMC calls. But reading them somewhere early in the Linux kernel and doing printk should be fine. I hope that you have access to your own copy of the Cortex-A8 errata list?
Regarding the testcases and the user visible impact. The IBE workaround is needed for Thumb2 support. If it is not applied, then branch prediction is broken and the CPU may end up in a wrong state (ARM vs. Thumb2). You only need to have two large binaries (which do lots of branching) running simultaneously, one compiled as ARM code and another compiled as Thumb2. One of them will eventually die on a context switch due to SIGILL or SIGSEGV.
One might need to be a little bit careful with the IBE workaround, because there is a related problem "687067: BTB invalidate by MVA operations will not work as intended when the IBE bit is enabled" Which exists in all Cortex-A8 cores regardless of the revision. However its impact is only limited to "invalidate by MVA operations", and "invalidate all" operations are not affected. The Linux kernel does not seem to ever use the "invalidate by MVA" operations. But basically, if there is no real need to set the IBE bit, then it should not be set on newer revisions of Cortex-A8 as suggested by Paul Kocialkowski to avoid any theoretical troubles.
Regarding the L1NEON workaround. Unless it is applied to r1pX revisions of Cortex-A8, most of the NEON code can't function and will deadlock the processor. You can try ffmpeg, libjpeg-turbo, pixman or something else to reproduce the problem. This one should be very easy to trigger.
Regarding the 725233 erratum ("PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock"), it was much harder to reproduce. I believe that it might be triggered even now by the pixman library test suite ("./configure && make check") or one of the bundled pixman benchmark programs. But I would not rely on that, because the pixman library has evolved since that time and the exact conditions could have changed.
Thanks for picking this up.
On 03/03/2015 12:45 AM, Siarhei Siamashka wrote: [...]
In one way, this can be verified by just checking that the necessary bits in the system registers are properly set according to the recommendations from the errata lists. AFAIK, only writes to these registers are restricted, so that it has to be done in an OMAP specific way using the SMC calls. But reading them somewhere early in the Linux kernel and doing printk should be fine.
http://paste.ubuntu.org.cn/2522971 a quick patch on v4.0-rc1 to do the same. Sorry, test farm I have access to, is a bit wonky at the moment. (use omap2plus_defconfig)
few of the boards I could cajole logs out are as follows (uses legacy bootloaders, not completely controlled source etc.. and are in a remote location that I cannot update easily):
am335x-evm.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042 am335x-sk.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042 am3517-evm.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x411fc087 ACR=0x000000e2 L2AUXCR=0x00000042 am37x-evm.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042 am57xx-evm.txt:[ 0.000000] XXXX o5_dump_arm_regs:CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040 beagleboard.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042 beaglebone-black.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042 beaglebone.txt:[ 0.000000] XXXX o3_dump_arm_regs:CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042 dra72x-evm.txt:[ 0.000000] XXXX o5_dump_arm_regs:CPUID=0x412fc0f2 L2CTLR=0x00800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040 dra7xx-evm.txt:[ 0.000000] XXXX o5_dump_arm_regs:CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040 omap5-evm.txt:[ 0.000000] XXXX o5_dump_arm_regs:CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
participants (3)
-
Nishanth Menon -
Siarhei Siamashka -
Tom Rini