Initial multiadapter/multibus I2C support.

Atmel AT91RM9200 based boards.

This goes on top of previous patches.

Signed-off-by: Sergey Kubushyn ksi@koi8.net --- diff -purN u-boot-i2c.ORIG/board/cmc_pu2/load_sernum_ethaddr.c u-boot-i2c/board/cmc_pu2/load_sernum_ethaddr.c --- u-boot-i2c.ORIG/board/cmc_pu2/load_sernum_ethaddr.c 2009-02-12 10:43:40.000000000 -0800 +++ u-boot-i2c/board/cmc_pu2/load_sernum_ethaddr.c 2009-02-13 16:29:00.000000000 -0800 @@ -75,7 +75,7 @@ void load_sernum_ethaddr (void) unsigned char *p; unsigned short i, is, id;

-#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C) +#if !defined(CONFIG_HAS_I2C) #error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C) #endif if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data, diff -purN u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/i2c.c u-boot-i2c/cpu/arm920t/at91rm9200/i2c.c --- u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/cpu/arm920t/at91rm9200/i2c.c 1969-12-31 16:00:00.000000000 -0800 @@ -1,202 +0,0 @@ -/* - * i2c Support for Atmel's AT91RM9200 Two-Wire Interface - * - * (c) Rick Bronson - * - * Borrowed heavily from original work by: - * Copyright (c) 2000 Philip Edelbrock phil@stimpy.netroedge.com - * - * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * -*/ -#include <common.h> - -#ifdef CONFIG_HARD_I2C - -#include <i2c.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -#include <at91rm9200_i2c.h> - -/* define DEBUG */ - -/* - * Poll the i2c status register until the specified bit is set. - * Returns 0 if timed out (100 msec) - */ -static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { - int loop_cntr = 10000; - do { - udelay(10); - } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); - - return (loop_cntr > 0); -} - -/* - * Generic i2c master transfer entrypoint - * - * rw == 1 means that this is a read - */ -static int -at91_xfer(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len, int rw) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - int length; - unsigned char *buf; - /* Set the TWI Master Mode Register */ - twi->TWI_MMR = (chip << 16) | (alen << 8) - | ((rw == 1) ? AT91C_TWI_MREAD : 0); - - /* Set TWI Internal Address Register with first messages data field */ - if (alen > 0) - twi->TWI_IADR = addr; - - length = len; - buf = buffer; - if (length && buf) { /* sanity check */ - if (rw) { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { - debug ("at91_i2c: timeout 1\n"); - return 1; - } - *buf++ = twi->TWI_RHR; - } - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 2\n"); - return 1; - } - } else { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - twi->TWI_THR = *buf++; - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { - debug ("at91_i2c: timeout 3\n"); - return 1; - } - } - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 4\n"); - return 1; - } - } - } - return 0; -} - -int -i2c_probe(unsigned char chip) -{ - unsigned char buffer[1]; - - return at91_xfer(chip, 0, 0, buffer, 1, 1); -} - -int -i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 1); -} - -int -i2c_write(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - int i; - unsigned char *buf; - - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { - buf = buffer; - /* do single byte writes */ - for (i = 0; i < len; i++) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - if (at91_xfer(chip, addr, alen, buf++, 1, 0)) - return 1; - addr++; - } - return 0; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 0); -} - -/* - * Main initialization routine - */ -void -i2c_init(int speed, int slaveaddr) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - - *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ - - twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ - twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ - twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ - - /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ - twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); - - debug ("Found AT91 i2c\n"); - return; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - return -1; -} - -unsigned int i2c_get_bus_speed(void) -{ - return CONFIG_SYS_I2C_SPEED; -} - -#endif /* CONFIG_HARD_I2C */ diff -purN u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/Makefile u-boot-i2c/cpu/arm920t/at91rm9200/Makefile --- u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/Makefile 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/cpu/arm920t/at91rm9200/Makefile 2009-02-13 15:36:53.000000000 -0800 @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(SOC).a

-COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ +COBJS = bcm5221.o dm9161.o ether.o interrupts.o \ lxt972.o serial.o usb.o spi.o SOBJS = lowlevel_init.o

diff -purN u-boot-i2c.ORIG/drivers/i2c/at91_i2c.c u-boot-i2c/drivers/i2c/at91_i2c.c --- u-boot-i2c.ORIG/drivers/i2c/at91_i2c.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-i2c/drivers/i2c/at91_i2c.c 2009-02-13 15:52:08.000000000 -0800 @@ -0,0 +1,216 @@ +/* + * i2c Support for Atmel's AT91RM9200 Two-Wire Interface + * + * Copyright (c) 2009 Sergey Kubushyn ksi@koi8.net + * + * Changes for multibus/multiadapter I2C support. + * + * (c) Rick Bronson + * + * Borrowed heavily from original work by: + * Copyright (c) 2000 Philip Edelbrock phil@stimpy.netroedge.com + * + * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * +*/ +#include <common.h> + +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#include <at91rm9200_i2c.h> + +/* define DEBUG */ + +i2c_adap_t at91_i2c_adap; + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Poll the i2c status register until the specified bit is set. + * Returns 0 if timed out (100 msec) + */ +static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { + int loop_cntr = 10000; + do { + udelay(10); + } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); + + return (loop_cntr > 0); +} + +/* + * Generic i2c master transfer entrypoint + * + * rw == 1 means that this is a read + */ +static int +at91_xfer(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len, int rw) +{ + AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; + int length; + unsigned char *buf; + /* Set the TWI Master Mode Register */ + twi->TWI_MMR = (chip << 16) | (alen << 8) + | ((rw == 1) ? AT91C_TWI_MREAD : 0); + + /* Set TWI Internal Address Register with first messages data field */ + if (alen > 0) + twi->TWI_IADR = addr; + + length = len; + buf = buffer; + if (length && buf) { /* sanity check */ + if (rw) { + twi->TWI_CR = AT91C_TWI_START; + while (length--) { + if (!length) + twi->TWI_CR = AT91C_TWI_STOP; + /* Wait until transfer is finished */ + if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { + debug ("at91_i2c: timeout 1\n"); + return 1; + } + *buf++ = twi->TWI_RHR; + } + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + debug ("at91_i2c: timeout 2\n"); + return 1; + } + } else { + twi->TWI_CR = AT91C_TWI_START; + while (length--) { + twi->TWI_THR = *buf++; + if (!length) + twi->TWI_CR = AT91C_TWI_STOP; + if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { + debug ("at91_i2c: timeout 3\n"); + return 1; + } + } + /* Wait until transfer is finished */ + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + debug ("at91_i2c: timeout 4\n"); + return 1; + } + } + } + return 0; +} + +static int at91_i2c_probe(unsigned char chip) +{ + unsigned char buffer[1]; + + return at91_xfer(chip, 0, 0, buffer, 1, 1); +} + +static int at91_i2c_read (unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* we only allow one address byte */ + if (alen > 1) + return 1; + /* XXX assume an ATMEL AT24C16 */ + if (alen == 1) { +#if 0 /* EEPROM code already sets this correctly */ + chip |= (addr >> 8) & 0xff; +#endif + addr = addr & 0xff; + } +#endif + return at91_xfer(chip, addr, alen, buffer, len, 1); +} + +static int at91_i2c_write(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + int i; + unsigned char *buf; + + /* we only allow one address byte */ + if (alen > 1) + return 1; + /* XXX assume an ATMEL AT24C16 */ + if (alen == 1) { + buf = buffer; + /* do single byte writes */ + for (i = 0; i < len; i++) { +#if 0 /* EEPROM code already sets this correctly */ + chip |= (addr >> 8) & 0xff; +#endif + addr = addr & 0xff; + if (at91_xfer(chip, addr, alen, buf++, 1, 0)) + return 1; + addr++; + } + return 0; + } +#endif + return at91_xfer(chip, addr, alen, buffer, len, 0); +} + +/* + * Main initialization routine + */ +static void at91_i2c_init(int speed, int slaveaddr) +{ + AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; + + *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ + + twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ + twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ + twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ + + /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ + twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); + + debug ("Found AT91 i2c\n"); + return; +} + +static unsigned int at91_i2c_set_bus_speed(unsigned int speed) +{ + return CONFIG_SYS_AT91_I2C_SPEED; +} + +static unsigned int at91_i2c_get_bus_speed(void) +{ + return CONFIG_SYS_AT91_I2C_SPEED; +} + + +i2c_adap_t at91_i2c_adap = { + .init = at91_i2c_init, + .probe = at91_i2c_probe, + .read = at91_i2c_read, + .write = at91_i2c_write, + .set_bus_speed = at91_i2c_set_bus_speed, + .get_bus_speed = at91_i2c_get_bus_speed, + .speed = CONFIG_SYS_AT91_I2C_SPEED, + .slaveaddr = CONFIG_SYS_AT91_I2C_SLAVE, + .init_done = 0, + .name = "at91_i2c" +}; diff -purN u-boot-i2c.ORIG/drivers/i2c/i2c_core.c u-boot-i2c/drivers/i2c/i2c_core.c --- u-boot-i2c.ORIG/drivers/i2c/i2c_core.c 2009-02-13 16:34:36.000000000 -0800 +++ u-boot-i2c/drivers/i2c/i2c_core.c 2009-02-13 15:52:58.000000000 -0800 @@ -6,6 +6,10 @@ #include <common.h> #include <i2c.h>

+#ifdef CONFIG_AT91_I2C +extern i2c_adap_t at91_i2c_adap; +#endif + #ifdef CONFIG_BFIN_TWI_I2C extern i2c_adap_t bfin_twi_i2c_adap; #endif diff -purN u-boot-i2c.ORIG/drivers/i2c/Makefile u-boot-i2c/drivers/i2c/Makefile --- u-boot-i2c.ORIG/drivers/i2c/Makefile 2009-02-13 16:34:36.000000000 -0800 +++ u-boot-i2c/drivers/i2c/Makefile 2009-02-13 16:26:58.000000000 -0800 @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk

LIB := $(obj)libi2c.a

+COBJS-$(CONFIG_AT91_I2C) += at91_i2c.o COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_MXC_I2C) += mxc_i2c.o Binary files u-boot-i2c.ORIG/.git/index and u-boot-i2c/.git/index differ diff -purN u-boot-i2c.ORIG/include/configs/cmc_pu2.h u-boot-i2c/include/configs/cmc_pu2.h --- u-boot-i2c.ORIG/include/configs/cmc_pu2.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/cmc_pu2.h 2009-02-13 16:18:53.000000000 -0800 @@ -96,11 +96,14 @@

#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */

-#define CONFIG_HARD_I2C +#define CONFIG_HAS_I2C

-#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ +#ifdef CONFIG_HAS_I2C +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ #define CONFIG_SYS_I2C_RTC_ADDR 0x32 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 @@ -136,7 +139,7 @@ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MISC

-#if defined(CONFIG_HARD_I2C) +#if defined(CONFIG_HAS_I2C) #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C diff -purN u-boot-i2c.ORIG/include/configs/kb9202.h u-boot-i2c/include/configs/kb9202.h --- u-boot-i2c.ORIG/include/configs/kb9202.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/kb9202.h 2009-02-13 16:10:08.000000000 -0800 @@ -128,7 +128,11 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 256

-#define CONFIG_HARD_I2C +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap}

#define CONFIG_ENV_IS_IN_EEPROM

@@ -142,8 +146,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ diff -purN u-boot-i2c.ORIG/include/configs/m501sk.h u-boot-i2c/include/configs/m501sk.h --- u-boot-i2c.ORIG/include/configs/m501sk.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/m501sk.h 2009-02-13 16:11:36.000000000 -0800 @@ -94,9 +94,11 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100 -#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_ENV_IS_IN_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 diff -purN u-boot-i2c.ORIG/include/configs/mp2usb.h u-boot-i2c/include/configs/mp2usb.h --- u-boot-i2c.ORIG/include/configs/mp2usb.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/mp2usb.h 2009-02-13 16:14:57.000000000 -0800 @@ -115,11 +115,14 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15

-#undef CONFIG_HARD_I2C +#undef CONFIG_HAS_I2C

-#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ +#ifdef CONFIG_HAS_I2C +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ #define CONFIG_SYS_I2C_RTC_ADDR 0x32 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 @@ -131,7 +134,7 @@

#define CONFIG_BOOTDELAY 3

-#if !defined(CONFIG_HARD_I2C) +#if !defined(CONFIG_HAS_I2C) #define CONFIG_TIMESTAMP #endif

@@ -154,7 +157,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP

-#if defined(CONFIG_HARD_I2C) +#if defined(CONFIG_HAS_I2C)

#define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM