[U-Boot] [PATCH] ARM: add marvell specific cache operation
For Marvell sheeva 88SV331xV5 core, it has one special cache asm code to do the clean and valid in one line.
Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/lib/cache.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..ae8f7e0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -33,11 +33,15 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) arm1136_cache_flush(); #endif #ifdef CONFIG_ARM926EJS +#if defined(CONFIG_SHEEVA_88SV331xV5) + asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0)); +#else /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); #endif +#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void);
-----Original Message----- From: Lei Wen [mailto:leiwen@marvell.com] Sent: Thursday, June 16, 2011 2:34 PM To: u-boot@lists.denx.de; Prafulla Wadaskar; Wadaskar@marvell.com; Prafulla Wadaskar; adrian.wenl@gmail.com Subject: [PATCH] ARM: add marvell specific cache operation
For Marvell sheeva 88SV331xV5 core, it has one special cache asm code to do the clean and valid in one line.
Signed-off-by: Lei Wen leiwen@marvell.com
arch/arm/lib/cache.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..ae8f7e0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -33,11 +33,15 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) arm1136_cache_flush(); #endif #ifdef CONFIG_ARM926EJS +#if defined(CONFIG_SHEEVA_88SV331xV5)
- asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+#else
Hi Lei I had pushed similar code long back but it was not accepted at that time. You may push this with proper explanation- 1. What this code exactly does and how this change is important for SHEEVA SoCs and boards mainlined so far.
Regards.. Prafulla . .
/* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); #endif +#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void);
-- 1.7.0.4
Hi Prafulla,
On Thu, Jun 16, 2011 at 5:31 PM, Prafulla Wadaskar prafulla@marvell.com wrote:
-----Original Message----- From: Lei Wen [mailto:leiwen@marvell.com] Sent: Thursday, June 16, 2011 2:34 PM To: u-boot@lists.denx.de; Prafulla Wadaskar; Wadaskar@marvell.com; Prafulla Wadaskar; adrian.wenl@gmail.com Subject: [PATCH] ARM: add marvell specific cache operation
For Marvell sheeva 88SV331xV5 core, it has one special cache asm code to do the clean and valid in one line.
Signed-off-by: Lei Wen leiwen@marvell.com
arch/arm/lib/cache.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..ae8f7e0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -33,11 +33,15 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) arm1136_cache_flush(); #endif #ifdef CONFIG_ARM926EJS +#if defined(CONFIG_SHEEVA_88SV331xV5)
- asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+#else
Hi Lei I had pushed similar code long back but it was not accepted at that time. You may push this with proper explanation-
- What this code exactly does and how this change is important for SHEEVA SoCs and boards mainlined so far.
Thanks for your suggestion.
The original implementation only drain write buffer. It cannot assure that when using dma from device to memory, the device cannot read the obsolete content of that range. Only invalidate cache would do that way.
This new adding assemble code for flushing has this meaning as: "DCache Clean All and Invalidate. Cleans all lines in the DCache, then invalidates the cache." It is slightly different from common arm core, as when we want invalidate the cache, we need to invalidate each cache entry.
That is the reason why I add this specific implementation for Marvell core only.
Best regards, Lei
participants (3)
-
Lei Wen -
Lei Wen -
Prafulla Wadaskar