[PATCH 0/7] Enable QoS for DSS on J7 family of TI SoCs
Hello All, This series adds the QoS for DSS on J721E, J721S2 and J784S4 family of SoCs.
Before adding the support, cleanup is done for AM62A QoS support[0] and common bit mask defines are moved to the common file so that they are not defined every time we add QoS support for a new K3 platform.
Before adding QoS support, we need to map the ORDERID to the traffic type (RT/NRT). On J721E, ORDERID 0-7 and 8-15 are two groups which needs to be mapped. We are mapping 0-7 to NRT and 8-15 ORDERID as RT for both NAVSS0_NBSS_NB0 and NAVSS0_NBSS_NB1 On J721S2 and J784S4, we have 3 groups, 0-3, 4-9, 10-15. Here we are mapping first two groups as NRT and 10-15 as RT for both NAVSS0_NBSS_NB0 and NAVSS0_NBSS_NB1.
[0]: https://lore.kernel.org/all/20230414072725.8802-1-a-bhatia1@ti.com/
Jayesh Choudhary (7): arm: mach-k3: am62a_qos: Move common bit MACROS to k3_qos header file arm: mach-k3: j721e: Enable QoS for DSS arm: mach-k3: j721s2: Enable QoS for DSS arm: mach-k3: j784s4: Enable QoS for DSS configs: j721e_evm_r5_defconfig: Enable CONFIG_K3_QOS configs: j721s2_evm_r5_defconfig: Enable CONFIG_K3_QOS configs: j784s4_evm_r5_defconfig: Enable CONFIG_K3_QOS
arch/arm/mach-k3/include/mach/k3-qos.h | 74 +++++++++++ arch/arm/mach-k3/j721e/j721e_init.c | 28 ++++ arch/arm/mach-k3/j721s2/j721s2_init.c | 30 +++++ arch/arm/mach-k3/j784s4/j784s4_init.c | 30 +++++ arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 ----------- arch/arm/mach-k3/r5/j721e/Makefile | 1 + arch/arm/mach-k3/r5/j721e/j721e_qos.h | 96 ++++++++++++++ arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 ++++++++++++++++++ arch/arm/mach-k3/r5/j721s2/Makefile | 1 + arch/arm/mach-k3/r5/j721s2/j721s2_qos.h | 79 +++++++++++ arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c | 109 +++++++++++++++ arch/arm/mach-k3/r5/j784s4/Makefile | 1 + arch/arm/mach-k3/r5/j784s4/j784s4_qos.h | 83 ++++++++++++ arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c | 109 +++++++++++++++ configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + 17 files changed, 769 insertions(+), 74 deletions(-) create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c
QoS bit mapping are common across all K3 SoCs so move those defines to common header file (k3_qos.h). This ensures that we do not define these for each SoC.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++++++++++++++++++++++++++ arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 -------------------------- 2 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h index e00e1de5b9..6ed5704803 100644 --- a/arch/arm/mach-k3/include/mach/k3-qos.h +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -9,6 +9,80 @@
#include <linux/kernel.h>
+#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0) + +#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4) + +#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8) + +#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12) + +#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16) + +#define ATYPE_0 (0 << 28) +#define ATYPE_1 (1 << 28) +#define ATYPE_2 (2 << 28) +#define ATYPE_3 (3 << 28) + struct k3_qos_data { u32 reg; u32 val; diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h index c74d69a28f..84a6dc7240 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h @@ -6,80 +6,6 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */
-#define QOS_0 (0 << 0) -#define QOS_1 (1 << 0) -#define QOS_2 (2 << 0) -#define QOS_3 (3 << 0) -#define QOS_4 (4 << 0) -#define QOS_5 (5 << 0) -#define QOS_6 (6 << 0) -#define QOS_7 (7 << 0) - -#define ORDERID_0 (0 << 4) -#define ORDERID_1 (1 << 4) -#define ORDERID_2 (2 << 4) -#define ORDERID_3 (3 << 4) -#define ORDERID_4 (4 << 4) -#define ORDERID_5 (5 << 4) -#define ORDERID_6 (6 << 4) -#define ORDERID_7 (7 << 4) -#define ORDERID_8 (8 << 4) -#define ORDERID_9 (9 << 4) -#define ORDERID_10 (10 << 4) -#define ORDERID_11 (11 << 4) -#define ORDERID_12 (12 << 4) -#define ORDERID_13 (13 << 4) -#define ORDERID_14 (14 << 4) -#define ORDERID_15 (15 << 4) - -#define ASEL_0 (0 << 8) -#define ASEL_1 (1 << 8) -#define ASEL_2 (2 << 8) -#define ASEL_3 (3 << 8) -#define ASEL_4 (4 << 8) -#define ASEL_5 (5 << 8) -#define ASEL_6 (6 << 8) -#define ASEL_7 (7 << 8) -#define ASEL_8 (8 << 8) -#define ASEL_9 (9 << 8) -#define ASEL_10 (10 << 8) -#define ASEL_11 (11 << 8) -#define ASEL_12 (12 << 8) -#define ASEL_13 (13 << 8) -#define ASEL_14 (14 << 8) -#define ASEL_15 (15 << 8) - -#define EPRIORITY_0 (0 << 12) -#define EPRIORITY_1 (1 << 12) -#define EPRIORITY_2 (2 << 12) -#define EPRIORITY_3 (3 << 12) -#define EPRIORITY_4 (4 << 12) -#define EPRIORITY_5 (5 << 12) -#define EPRIORITY_6 (6 << 12) -#define EPRIORITY_7 (7 << 12) - -#define VIRTID_0 (0 << 16) -#define VIRTID_1 (1 << 16) -#define VIRTID_2 (2 << 16) -#define VIRTID_3 (3 << 16) -#define VIRTID_4 (4 << 16) -#define VIRTID_5 (5 << 16) -#define VIRTID_6 (6 << 16) -#define VIRTID_7 (7 << 16) -#define VIRTID_8 (8 << 16) -#define VIRTID_9 (9 << 16) -#define VIRTID_10 (10 << 16) -#define VIRTID_11 (11 << 16) -#define VIRTID_12 (12 << 16) -#define VIRTID_13 (13 << 16) -#define VIRTID_14 (14 << 16) -#define VIRTID_15 (15 << 16) - -#define ATYPE_0 (0 << 28) -#define ATYPE_1 (1 << 28) -#define ATYPE_2 (2 << 28) -#define ATYPE_3 (3 << 28) - #define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 #define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 #define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
On 5/22/24 6:37 AM, Jayesh Choudhary wrote:
QoS bit mapping are common across all K3 SoCs so move those defines to common header file (k3_qos.h). This ensures that we do not define these for each SoC.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com
arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++++++++++++++++++++++++++ arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 -------------------------- 2 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h index e00e1de5b9..6ed5704803 100644 --- a/arch/arm/mach-k3/include/mach/k3-qos.h +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -9,6 +9,80 @@
#include <linux/kernel.h>
+#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0)
+#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4)
+#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8)
+#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12)
+#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16)
This all seem like it could be made into some macro, something like
#define K3_QOS(qos, orderid, asel, epriority, virtid, atype) \ (qos << 0 | \ orderid << 4 | \ asel << 8 | \ etc..
Then use that instead of raw values. That might also make it more clear we are setting the other values to 0 when we are setting these registers:
.val = K3_QOS(0, 15, 0, 0, 0, 3),
Andrew
+#define ATYPE_0 (0 << 28) +#define ATYPE_1 (1 << 28) +#define ATYPE_2 (2 << 28) +#define ATYPE_3 (3 << 28)
- struct k3_qos_data { u32 reg; u32 val;
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h index c74d69a28f..84a6dc7240 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h @@ -6,80 +6,6 @@
- Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
-#define QOS_0 (0 << 0) -#define QOS_1 (1 << 0) -#define QOS_2 (2 << 0) -#define QOS_3 (3 << 0) -#define QOS_4 (4 << 0) -#define QOS_5 (5 << 0) -#define QOS_6 (6 << 0) -#define QOS_7 (7 << 0)
-#define ORDERID_0 (0 << 4) -#define ORDERID_1 (1 << 4) -#define ORDERID_2 (2 << 4) -#define ORDERID_3 (3 << 4) -#define ORDERID_4 (4 << 4) -#define ORDERID_5 (5 << 4) -#define ORDERID_6 (6 << 4) -#define ORDERID_7 (7 << 4) -#define ORDERID_8 (8 << 4) -#define ORDERID_9 (9 << 4) -#define ORDERID_10 (10 << 4) -#define ORDERID_11 (11 << 4) -#define ORDERID_12 (12 << 4) -#define ORDERID_13 (13 << 4) -#define ORDERID_14 (14 << 4) -#define ORDERID_15 (15 << 4)
-#define ASEL_0 (0 << 8) -#define ASEL_1 (1 << 8) -#define ASEL_2 (2 << 8) -#define ASEL_3 (3 << 8) -#define ASEL_4 (4 << 8) -#define ASEL_5 (5 << 8) -#define ASEL_6 (6 << 8) -#define ASEL_7 (7 << 8) -#define ASEL_8 (8 << 8) -#define ASEL_9 (9 << 8) -#define ASEL_10 (10 << 8) -#define ASEL_11 (11 << 8) -#define ASEL_12 (12 << 8) -#define ASEL_13 (13 << 8) -#define ASEL_14 (14 << 8) -#define ASEL_15 (15 << 8)
-#define EPRIORITY_0 (0 << 12) -#define EPRIORITY_1 (1 << 12) -#define EPRIORITY_2 (2 << 12) -#define EPRIORITY_3 (3 << 12) -#define EPRIORITY_4 (4 << 12) -#define EPRIORITY_5 (5 << 12) -#define EPRIORITY_6 (6 << 12) -#define EPRIORITY_7 (7 << 12)
-#define VIRTID_0 (0 << 16) -#define VIRTID_1 (1 << 16) -#define VIRTID_2 (2 << 16) -#define VIRTID_3 (3 << 16) -#define VIRTID_4 (4 << 16) -#define VIRTID_5 (5 << 16) -#define VIRTID_6 (6 << 16) -#define VIRTID_7 (7 << 16) -#define VIRTID_8 (8 << 16) -#define VIRTID_9 (9 << 16) -#define VIRTID_10 (10 << 16) -#define VIRTID_11 (11 << 16) -#define VIRTID_12 (12 << 16) -#define VIRTID_13 (13 << 16) -#define VIRTID_14 (14 << 16) -#define VIRTID_15 (15 << 16)
-#define ATYPE_0 (0 << 28) -#define ATYPE_1 (1 << 28) -#define ATYPE_2 (2 << 28) -#define ATYPE_3 (3 << 28)
- #define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 #define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 #define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
On Wed, May 22, 2024 at 10:21:28AM -0500, Andrew Davis wrote:
On 5/22/24 6:37 AM, Jayesh Choudhary wrote:
QoS bit mapping are common across all K3 SoCs so move those defines to common header file (k3_qos.h). This ensures that we do not define these for each SoC.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com
arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++++++++++++++++++++++++++ arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 -------------------------- 2 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h index e00e1de5b9..6ed5704803 100644 --- a/arch/arm/mach-k3/include/mach/k3-qos.h +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -9,6 +9,80 @@ #include <linux/kernel.h> +#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0)
+#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4)
+#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8)
+#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12)
+#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16)
This all seem like it could be made into some macro, something like
#define K3_QOS(qos, orderid, asel, epriority, virtid, atype) \ (qos << 0 | \ orderid << 4 | \ asel << 8 | \ etc..
Then use that instead of raw values. That might also make it more clear we are setting the other values to 0 when we are setting these registers:
.val = K3_QOS(0, 15, 0, 0, 0, 3),
This sounds good to me too and to be clear, move in one patch, clean up macro follow-up patch in this series.
Hello Tom, Andrew,
On 23/05/24 04:36, Tom Rini wrote:
On Wed, May 22, 2024 at 10:21:28AM -0500, Andrew Davis wrote:
On 5/22/24 6:37 AM, Jayesh Choudhary wrote:
QoS bit mapping are common across all K3 SoCs so move those defines to common header file (k3_qos.h). This ensures that we do not define these for each SoC.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com
arch/arm/mach-k3/include/mach/k3-qos.h | 74 ++++++++++++++++++++++++++ arch/arm/mach-k3/r5/am62ax/am62a_qos.h | 74 -------------------------- 2 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h index e00e1de5b9..6ed5704803 100644 --- a/arch/arm/mach-k3/include/mach/k3-qos.h +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -9,6 +9,80 @@ #include <linux/kernel.h> +#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0)
+#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4)
+#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8)
+#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12)
+#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16)
This all seem like it could be made into some macro, something like
#define K3_QOS(qos, orderid, asel, epriority, virtid, atype) \ (qos << 0 | \ orderid << 4 | \ asel << 8 | \ etc..
Then use that instead of raw values. That might also make it more clear we are setting the other values to 0 when we are setting these registers:
.val = K3_QOS(0, 15, 0, 0, 0, 3),
This sounds good to me too and to be clear, move in one patch, clean up macro follow-up patch in this series.
Okay so 1st patch will be similar to this. And in the next patch, macros will be defined and cleanup for arch/arm/mach-k3/r5/am62a/am62ax_qos_uboot.c will be done in an atomic step. Rest of the platforms will be added after that.
Also, just for clarity, this implies changes in k3-resource-partitioning tool which would be generating these files. So is it okay to post v2 with manual changes here and then picking up the changes in the tool later according to the final file template that we settle on?
Warm Regards, Jayesh
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to greater than 7. ATYPE 3 is selected so that the traffic takes non-coherent path and does not have a conflict with coherent traffic from C7x (deep-learning applications). Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources using setup_navss_nb() function call that sets the threadmap for NBSS registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])
Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more details.
[0]: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- arch/arm/mach-k3/j721e/j721e_init.c | 28 +++++ arch/arm/mach-k3/r5/j721e/Makefile | 1 + arch/arm/mach-k3/r5/j721e/j721e_qos.h | 96 +++++++++++++++ arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 ++++++++++++++++++++ 4 files changed, 250 insertions(+) create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index c2024f2500..e9ed8cb267 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -23,6 +23,22 @@ #include "../sysfw-loader.h" #include "../common.h"
+/* NAVSS North Bridge (NB) registers */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03803000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-7 to VBUSM.C thread number + * Bit[1] maps orderID 8-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM) @@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void) } #endif
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -288,6 +311,11 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif spl_enable_cache(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); }
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile index 78325db402..07bfb0dd93 100644 --- a/arch/arm/mach-k3/r5/j721e/Makefile +++ b/arch/arm/mach-k3/r5/j721e/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721e_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h b/arch/arm/mach-k3/r5/j721e/j721e_qos.h new file mode 100644 index 0000000000..9ec0b7c630 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define PULSAR_SL_MCU_0_MEMBDG_RMST0 0x45D10000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST0 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_MEMBDG_RMST1 0x45D11000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST1 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA2_UL_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define ICSS_G_MAIN_0_PR1_EXT_VBUSM 0x45D80000 +#define ICSS_G_MAIN_1_PR1_EXT_VBUSM 0x45D80400 +#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000 +#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D82C00 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST0 0x45D84000 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST1 0x45D84400 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST0 0x45D84800 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST1 0x45D84C00 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST0 0x45D85000 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST1 0x45D85400 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST0 0x45D85800 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST1 0x45D85C00 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define K3_C66_COREPAC_MAIN_0_C66_CFG 0x45D87000 +#define K3_C66_COREPAC_MAIN_1_C66_CFG 0x45D87400 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D88800 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D89800 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D89C00 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D8A000 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D8A400 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45D8A800 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45D8AC00 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45D8B000 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45D8B400 +#define VPFE_MAIN_0_VBUSM_DMA 0x45D8C000 +#define VPE_MAIN_0_VPDMA_MST0 0x45D8C400 +#define VPE_MAIN_0_VPDMA_MST1 0x45D8C800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_HP 0x45D90000 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_LP 0x45D90400 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_HP 0x45D90800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_LP 0x45D90C00 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_HP 0x45D91000 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_LP 0x45D91400 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_HP 0x45D91800 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_LP 0x45D91C00 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_HP 0x45D92000 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_LP 0x45D92400 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_HP 0x45D92800 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_LP 0x45D92C00 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_HP 0x45D93000 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_LP 0x45D93400 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_HP 0x45D93800 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_LP 0x45D93C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D98000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D98400 +#define USB3P0SS_16FFC_MAIN_1_MSTR0 0x45D98800 +#define USB3P0SS_16FFC_MAIN_1_MSTW0 0x45D98C00 +#define USB3P0SS_16FFC_MAIN_2_MSTR0 0x45D99000 +#define USB3P0SS_16FFC_MAIN_2_MSTW0 0x45D99400 +#define MLBSS2P0_MAIN_0_MLBSS_DMA_VBUSP 0x45D99C00 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9A000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9B000 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B400 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_RD 0x45D9B800 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_WR 0x45D9BC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_0_CPU0_PMST 0x45DA4000 +#define PULSAR_SL_MAIN_0_CPU1_PMST 0x45DA4400 +#define PULSAR_SL_MAIN_1_CPU0_PMST 0x45DA4800 +#define PULSAR_SL_MAIN_1_CPU1_PMST 0x45DA4C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_D5520MP2_MAIN_0_M_VBUSM_R 0x45DC0400 +#define K3_D5520MP2_MAIN_0_M_VBUSM_W 0x45DC0800 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_R 0x45DC0C00 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_W 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_R_ASYNC 0x45DC5000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_W_ASYNC 0x45DC5800 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_R_ASYNC 0x45DC6000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_W_ASYNC 0x45DC6800 diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c new file mode 100644 index 0000000000..c829057200 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j721e Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + */ + +#include <asm/arch/k3-qos.h> +#include "j721e_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 0, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 2, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 3, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 4, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 5, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 4, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 5, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 6, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 7, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 6, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 7, + .val = ATYPE_3 | ORDERID_15, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 8, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 12, + .val = 0xfedcba98, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 2 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 4, + .val = 0xfedcba98, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 8, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 12, + .val = 0xfedcba98, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data);
On 5/22/24 6:37 AM, Jayesh Choudhary wrote:
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to greater than 7. ATYPE 3 is selected so that the traffic takes non-coherent path and does
So this is the part I'm not sure about, this change is not just a performance adjustment, it can and does break things. The ORDERID setting is fine with me, but changing ATYPE should be done in a separate patch so it can be debated on its own.
not have a conflict with coherent traffic from C7x (deep-learning applications). Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources using setup_navss_nb() function call that sets the threadmap for NBSS registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])
Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more details.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com
arch/arm/mach-k3/j721e/j721e_init.c | 28 +++++ arch/arm/mach-k3/r5/j721e/Makefile | 1 + arch/arm/mach-k3/r5/j721e/j721e_qos.h | 96 +++++++++++++++ arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 ++++++++++++++++++++ 4 files changed, 250 insertions(+) create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index c2024f2500..e9ed8cb267 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -23,6 +23,22 @@ #include "../sysfw-loader.h" #include "../common.h"
+/* NAVSS North Bridge (NB) registers */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03803000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/*
- Thread Map for North Bridge Configuration
- Each bit is for each VBUSM source.
- Bit[0] maps orderID 0-7 to VBUSM.C thread number
- Bit[1] maps orderID 8-15 to VBUSM.C thread number
- When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
- When bit has value 1: VBUSM.C thread 2 (real time traffic)
- */
+#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1)
- #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void) } #endif
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */ +static void setup_navss_nb(void) +{
- writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
- writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
- /*
- This uninitialized global variable would normal end up in the .bss section,
- but the .bss is cleared between writing and reading this variable, so move
@@ -288,6 +311,11 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif spl_enable_cache();
if (IS_ENABLED(CONFIG_CPU_V7R))
setup_navss_nb();setup_qos(); }
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile index 78325db402..07bfb0dd93 100644 --- a/arch/arm/mach-k3/r5/j721e/Makefile +++ b/arch/arm/mach-k3/r5/j721e/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721e_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h b/arch/arm/mach-k3/r5/j721e/j721e_qos.h new file mode 100644 index 0000000000..9ec0b7c630 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Keystone3 Quality of service endpoint definitions
- Auto generated by K3 Resource Partitioning Tool
- Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
- */
+#define PULSAR_SL_MCU_0_MEMBDG_RMST0 0x45D10000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST0 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_MEMBDG_RMST1 0x45D11000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST1 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA2_UL_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define ICSS_G_MAIN_0_PR1_EXT_VBUSM 0x45D80000 +#define ICSS_G_MAIN_1_PR1_EXT_VBUSM 0x45D80400 +#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000 +#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D82C00 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST0 0x45D84000 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST1 0x45D84400 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST0 0x45D84800 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST1 0x45D84C00 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST0 0x45D85000 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST1 0x45D85400 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST0 0x45D85800 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST1 0x45D85C00 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define K3_C66_COREPAC_MAIN_0_C66_CFG 0x45D87000 +#define K3_C66_COREPAC_MAIN_1_C66_CFG 0x45D87400 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D88800 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D89800 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D89C00 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D8A000 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D8A400 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45D8A800 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45D8AC00 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45D8B000 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45D8B400 +#define VPFE_MAIN_0_VBUSM_DMA 0x45D8C000 +#define VPE_MAIN_0_VPDMA_MST0 0x45D8C400 +#define VPE_MAIN_0_VPDMA_MST1 0x45D8C800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_HP 0x45D90000 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_LP 0x45D90400 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_HP 0x45D90800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_LP 0x45D90C00 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_HP 0x45D91000 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_LP 0x45D91400 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_HP 0x45D91800 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_LP 0x45D91C00 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_HP 0x45D92000 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_LP 0x45D92400 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_HP 0x45D92800 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_LP 0x45D92C00 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_HP 0x45D93000 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_LP 0x45D93400 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_HP 0x45D93800 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_LP 0x45D93C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D98000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D98400 +#define USB3P0SS_16FFC_MAIN_1_MSTR0 0x45D98800 +#define USB3P0SS_16FFC_MAIN_1_MSTW0 0x45D98C00 +#define USB3P0SS_16FFC_MAIN_2_MSTR0 0x45D99000 +#define USB3P0SS_16FFC_MAIN_2_MSTW0 0x45D99400 +#define MLBSS2P0_MAIN_0_MLBSS_DMA_VBUSP 0x45D99C00 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9A000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9B000 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B400 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_RD 0x45D9B800 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_WR 0x45D9BC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_0_CPU0_PMST 0x45DA4000 +#define PULSAR_SL_MAIN_0_CPU1_PMST 0x45DA4400 +#define PULSAR_SL_MAIN_1_CPU0_PMST 0x45DA4800 +#define PULSAR_SL_MAIN_1_CPU1_PMST 0x45DA4C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_D5520MP2_MAIN_0_M_VBUSM_R 0x45DC0400 +#define K3_D5520MP2_MAIN_0_M_VBUSM_W 0x45DC0800 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_R 0x45DC0C00 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_W 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_R_ASYNC 0x45DC5000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_W_ASYNC 0x45DC5800 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_R_ASYNC 0x45DC6000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_W_ASYNC 0x45DC6800 diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c new file mode 100644 index 0000000000..c829057200 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- j721e Quality of Service (QoS) Configuration Data
- Auto generated from K3 Resource Partitioning tool
- */
+#include <asm/arch/k3-qos.h> +#include "j721e_qos.h"
+struct k3_qos_data qos_data[] = {
- /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0,
0x100 being the instance, and 0x4 * x being the specific device register right? That could be encoded in a macro (the "Resource Partitioning tool" would be updated to generate that too).
Andrew
.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 0,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 1,.val = ATYPE_3 | ORDERID_15,- },
- /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 2,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 3,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 2,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 3,.val = ATYPE_3 | ORDERID_15,- },
- /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 4,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 5,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 4,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 5,.val = ATYPE_3 | ORDERID_15,- },
- /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 6,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 7,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 6,.val = ATYPE_3 | ORDERID_15,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 7,.val = ATYPE_3 | ORDERID_15,- },
- /* Following registers set 1:1 mapping for orderID MAP1/MAP2
* remap registers. orderID x is remapped to orderID x again* This is to ensure orderID from MAP register is unchanged*/- /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0,.val = 0x76543210,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4,.val = 0xfedcba98,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 8,.val = 0x76543210,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 12,.val = 0xfedcba98,- },
- /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 2 groups */
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0,.val = 0x76543210,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 4,.val = 0xfedcba98,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 8,.val = 0x76543210,- },
- {
.reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 12,.val = 0xfedcba98,- },
+};
+u32 qos_count = ARRAY_SIZE(qos_data);
Hello Andrew,
On 22/05/24 21:14, Andrew Davis wrote:
On 5/22/24 6:37 AM, Jayesh Choudhary wrote:
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to greater than 7. ATYPE 3 is selected so that the traffic takes non-coherent path and does
So this is the part I'm not sure about, this change is not just a performance adjustment, it can and does break things. The ORDERID setting is fine with me, but changing ATYPE should be done in a separate patch so it can be debated on its own.
not have a conflict with coherent traffic from C7x (deep-learning applications). Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources using setup_navss_nb() function call that sets the threadmap for NBSS registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])
Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more details.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com
arch/arm/mach-k3/j721e/j721e_init.c | 28 +++++ arch/arm/mach-k3/r5/j721e/Makefile | 1 + arch/arm/mach-k3/r5/j721e/j721e_qos.h | 96 +++++++++++++++ arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 ++++++++++++++++++++ 4 files changed, 250 insertions(+) create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index c2024f2500..e9ed8cb267 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c
[...]
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c new file mode 100644 index 0000000000..c829057200 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- j721e Quality of Service (QoS) Configuration Data
- Auto generated from K3 Resource Partitioning tool
- */
+#include <asm/arch/k3-qos.h> +#include "j721e_qos.h"
+struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0,
0x100 being the instance, and 0x4 * x being the specific device register right? That could be encoded in a macro (the "Resource Partitioning tool" would be updated to generate that too).
Andrew
Okay both val and reg could be updated.
+ .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + },
[...]
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4, + .val = 0xfedcba98, + },
From the looks of it, these register and val can also be encoded as K3_QOS_GROUP_REG and K3_QOS_GROUP_VAL_HIGH (0xfedcba98) and K3_QOS_GROUP_VAL_LOW (0x76543210)????
[...]
+u32 qos_count = ARRAY_SIZE(qos_data);
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to greater than 9. ATYPE 3 is selected so that the traffic takes non-coherent path and does not have a conflict with coherent traffic from C7x (deep-learning applications). Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources using setup_navss_nb() function call that sets the threadmap for NBSS registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])
Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more details.
[0]: https://www.ti.com/lit/zip/spruj28
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- arch/arm/mach-k3/j721s2/j721s2_init.c | 30 +++++ arch/arm/mach-k3/r5/j721s2/Makefile | 1 + arch/arm/mach-k3/r5/j721s2/j721s2_qos.h | 79 +++++++++++++ arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c | 109 ++++++++++++++++++ 4 files changed, 219 insertions(+) create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos.h create mode 100644 arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c
diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index fe9766e9b4..05453fcad4 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -22,6 +22,24 @@ #include "../sysfw-loader.h" #include "../common.h"
+/* NAVSS North Bridge (NB) */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-3 to VBUSM.C thread number + * Bit[1] maps orderID 4-9 to VBUSM.C thread number + * Bit[2] maps orderID 10-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) +#define NB_THREADMAP_BIT2 BIT(2) + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, @@ -123,6 +141,13 @@ void k3_mmc_restart_clock(void) } }
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -295,6 +320,11 @@ void board_init_f(ulong dummy) do_dt_magic(); #endif k3_mem_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } #endif
diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile index 8588c5e4c3..89c0284b56 100644 --- a/arch/arm/mach-k3/r5/j721s2/Makefile +++ b/arch/arm/mach-k3/r5/j721s2/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721s2_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h new file mode 100644 index 0000000000..ab3e4773a4 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 +#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 +#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 +#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 +#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 +#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 +#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 +#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 +#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 +#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 +#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 +#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 +#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 +#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 +#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 +#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 +#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 +#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 +#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 +#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 +#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 +#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 +#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 +#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c new file mode 100644 index 0000000000..e8ad87bdac --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j721s2 Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + */ + +#include <asm/arch/k3-qos.h> +#include "j721s2_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 0, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 2, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 3, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 4, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 5, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 4, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 5, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 6, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 7, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 6, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 7, + .val = ATYPE_3 | ORDERID_15, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 4, + .val = 0xfedcba98, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data);
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to greater than 9. ATYPE 3 is selected so that the traffic takes non-coherent path and does not have a conflict with coherent traffic from C7x (deep-learning applications). Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources using setup_navss_nb() function call that sets the threadmap for NBSS registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])
Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more details.
[0]: https://www.ti.com/lit/zip/spruj52
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- arch/arm/mach-k3/j784s4/j784s4_init.c | 30 +++++ arch/arm/mach-k3/r5/j784s4/Makefile | 1 + arch/arm/mach-k3/r5/j784s4/j784s4_qos.h | 83 +++++++++++++ arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c | 109 ++++++++++++++++++ 4 files changed, 223 insertions(+) create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos.h create mode 100644 arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c
diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 1ce13e0f49..07b5d7d750 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -23,6 +23,24 @@
#define J784S4_MAX_DDR_CONTROLLERS 4
+/* NAVSS North Bridge (NB) */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-3 to VBUSM.C thread number + * Bit[1] maps orderID 4-9 to VBUSM.C thread number + * Bit[2] maps orderID 10-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) +#define NB_THREADMAP_BIT2 BIT(2) + struct fwl_data infra_cbass0_fwls[] = { { "PSC0", 5, 1 }, { "PLL_CTRL0", 6, 1 }, @@ -94,6 +112,13 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 7); }
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -210,6 +235,11 @@ void board_init_f(ulong dummy) { k3_spl_init(); k3_mem_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); }
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile b/arch/arm/mach-k3/r5/j784s4/Makefile index 9ce88305f5..0fd6cabd3f 100644 --- a/arch/arm/mach-k3/r5/j784s4/Makefile +++ b/arch/arm/mach-k3/r5/j784s4/Makefile @@ -5,3 +5,4 @@
obj-y += clk-data.o obj-y += dev-data.o +obj-y += j784s4_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h new file mode 100644 index 0000000000..5851f889fe --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 +#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 +#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 +#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 +#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 +#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 +#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 +#define PCIE_G3X4_128_MAIN_2_PCIE_MST_RD 0x45D9CC00 +#define PCIE_G3X4_128_MAIN_3_PCIE_MST_WR 0x45D9D400 +#define PCIE_G3X4_128_MAIN_2_PCIE_MST_WR 0x45D9D800 +#define PCIE_G3X4_128_MAIN_3_PCIE_MST_RD 0x45D9DC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 +#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 +#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 +#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 +#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 +#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 +#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 +#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 +#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 +#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 +#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 +#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 +#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 +#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 +#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 +#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 +#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 +#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c new file mode 100644 index 0000000000..2713741733 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j784s4 Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + */ + +#include <asm/arch/k3-qos.h> +#include "j784s4_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 0, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 1, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 2, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 3, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 4, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 5, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 4, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 5, + .val = ATYPE_3 | ORDERID_15, + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 6, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 7, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 6, + .val = ATYPE_3 | ORDERID_15, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + 0x4 * 7, + .val = ATYPE_3 | ORDERID_15, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */ + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 4, + .val = 0xfedcba98, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data);
Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- configs/j721e_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index cea48b2613..5d48f48367 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J721E=y CONFIG_K3_EARLY_CONS=y +CONFIG_K3_QOS=y CONFIG_TARGET_J721E_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- configs/j721s2_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 3c958cafbe..d53c5e33d6 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J721S2=y CONFIG_K3_EARLY_CONS=y +CONFIG_K3_QOS=y CONFIG_TARGET_J721S2_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
Enable CONFIG_K3_QOS to set QoS registers in R5 boot stage.
Signed-off-by: Jayesh Choudhary j-choudhary@ti.com --- configs/j784s4_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index f5fe743220..d1bcf792d7 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J784S4=y CONFIG_K3_EARLY_CONS=y +CONFIG_K3_QOS=y CONFIG_TARGET_J784S4_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
participants (3)
-
Andrew Davis -
Jayesh Choudhary -
Tom Rini