Signed-off-by: Andre Schwarz andre.schwarz@matrix-vision.de --- include/configs/MERGERBOX.h | 619 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 619 insertions(+), 0 deletions(-) create mode 100644 include/configs/MERGERBOX.h

diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h new file mode 100644 index 0000000..f9681cd --- /dev/null +++ b/include/configs/MERGERBOX.h @@ -0,0 +1,619 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz andre.schwarz@matrix-vision.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <version.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC837x 1 +#define CONFIG_MPC8377 1 + +#define CONFIG_SYS_TEXT_BASE 0xFC000000 + +#define CONFIG_PCI 1 + +#define CONFIG_MASK_AER_AO +#define CONFIG_DISPLAY_AER_FULL + +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + */ +#define CONFIG_TSEC_ENET + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#define CONFIG_PCIE +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word stored in EEPROM. + */ +#define CONFIG_SYS_HRCW_LOW 0 +#define CONFIG_SYS_HRCW_HIGH 0 + +/* Arbiter Configuration Register */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 +#define CONFIG_SYS_ACR_RPTCNT 3 + +/* System Priority Control Regsiter */ +#define CONFIG_SYS_SPCR_TSECEP 3 + +/* System Clock Configuration Register */ +#define CONFIG_SYS_SCCR_TSEC1CM 3 +#define CONFIG_SYS_SCCR_TSEC2CM 0 +#define CONFIG_SYS_SCCR_SDHCCM 3 +#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */ +#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 3 +#define CONFIG_SYS_SCCR_PCIEXP2CM 3 +#define CONFIG_SYS_SCCR_PCICM 1 +#define CONFIG_SYS_SCCR_SATACM 0xFF + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x087c0000 +#define CONFIG_SYS_SICRL 0x40000000 + +/* + * Output Buffer Impedance + */ +#define CONFIG_SYS_OBIR 0x30000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_83XX_DDR_USES_CS0 + +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\ + DDRCDR_NZ_HIZ | DDRCDR_ODT |\ + DDRCDR_Q_DRN) + +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + +#define CONFIG_SYS_DDR_MODE_WEAK +#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2 +#define CONFIG_SYS_DDR_CPO 0x1f + +/* SPD table located at offset 0x20 in extended adressing ROM + * used for HRCW fetch after power-on reset + */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x50 +#define SPD_EEPROM_OFFSET 0x20 +#define SPD_EEPROM_ADDR_LEN 2 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (512*1024) +#define CONFIG_SYS_MALLOC_LEN (512*1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ + CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 +#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_FSL_ELBC 1 + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_SIZE 64 + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ + OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\ + OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + */ +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 + +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\ + BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\ + OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\ + OR_FCM_TRLX | OR_FCM_EHTR) + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +#define CONFIG_CONSOLE ttyS0 +#define CONFIG_BAUDRATE 115200 + +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 120000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20) +#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE +#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20) +#define CONFIG_SYS_PCI_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI_IO_SIZE (1 << 20) + +#ifdef CONFIG_PCIE +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20) +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20) +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20) + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20) +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20) +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20) +#endif + +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +/* + * TSEC + */ +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_SYS_VSC8601_SKEWFIX +#define CONFIG_SYS_VSC8601_SKEW_TX 3 +#define CONFIG_SYS_VSC8601_SKEW_RX 3 + +#define CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x10 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 + +#define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_HAS_ETH0 + +/* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_USB +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_SATA + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 + +#define CONFIG_RBTREE +#define CONFIG_LZO + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND" +#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)" + +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LOAD_ADDR 0x2000000 +#define CONFIG_LOADADDR 0x4000000 +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#define CONFIG_SYS_MEMTEST_START (60<<20) +#define CONFIG_SYS_MEMTEST_END (70<<20) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ +#define CONFIG_HIGH_BATS 1 + +/* DDR: cache cacheable */ +#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE + +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* unused */ +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* unused */ +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* PCI MEM space: cacheable */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +/* PCI MMIO space: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * I2C EEPROM settings + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_SIZE 0x4000 + +/* + * Environment Configuration + */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0xFFD00000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* + * Video + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SM501_PCI +#define VIDEO_FB_LITTLE_ENDIAN +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) + +/* + * SPI + */ +#define CONFIG_MPC8XXX_SPI + +/* + * USB + */ +#define CONFIG_SYS_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +/* + * + */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "s" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1000 + +#define MV_CI MergerBox +#define MV_VCI MergerBox +#define MV_FPGA_DATA 0xfc100000 +#define MV_FPGA_SIZE 0x00200000 + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM 0x02800000 +#define MV_DTB_ADDR_RAM 0x00600000 +#define MV_INITRD_ADDR_RAM 0x01000000 +#define MV_FITADDR 0xfc300000 +#define MV_SPLAH_ADDR 0xffe00000 + +#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\ + "then; run fitboot;else;run ubiboot;fi;" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0"\ + "stdin=serial\0"\ + "stdout=serial\0"\ + "stderr=serial\0"\ + "boot_sqfs=1\0"\ + "usb_dr_mode=host\0"\ + "bootfile=MergerBox.fit\0"\ + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\ + "fpga=0\0"\ + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\ + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\ + "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\ + "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\ + "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\ + "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\ + "fitaddr=" MK_STR(MV_FITADDR) "\0"\ + "mv_version=" U_BOOT_VERSION "\0"\ + "mtdids=" MTDIDS_DEFAULT "\0"\ + "mtdparts=" MTDPARTS_DEFAULT "\0"\ + "dhcp_client_id=" MK_STR(MV_CI) "\0"\ + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"\ + "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\ + "protect off all;erase $uboota +0xC0000;"\ + "cp.b $loadaddr $uboota $filesize\0"\ + "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\ + "cp.b $loadaddr $fpgadata $filesize\0"\ + "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\ + "cp.b $loadaddr $fitaddr $filesize\0"\ + "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\ + "rootfstype=squashfs\0"\ + "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\ + "rootfstype=ubifs\0"\ + "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\ + "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\ + "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\ + "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\ + "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\ + "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\ + "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\ + "imxtract $fitaddr ramdisk $mv_initrd_ram;"\ + "imxtract $fitaddr fdt $mv_dtb_ram\0"\ + "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\ + "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\ + "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\ + "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\ + "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\ + "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\ + "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\ + "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\ + "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\ + "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\ + "" + +#undef MK_STR +#undef XMK_STR + +/* + * FPGA + */ +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 + +#endif

Signed-off-by: Andre Schwarz andre.schwarz@matrix-vision.de --- doc/README.mergerbox | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) create mode 100644 doc/README.mergerbox

diff --git a/doc/README.mergerbox b/doc/README.mergerbox new file mode 100644 index 0000000..1994b65 --- /dev/null +++ b/doc/README.mergerbox @@ -0,0 +1,59 @@ +Matrix Vision MergerBox +----------------------- + +1. Board Description + + The MergerBox is a 120x160mm single board computing platform + for 3D Full-HD digital video processing. + + Power Supply is 10-32VDC. + +2 System Components + +2.1 CPU + Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. + 256 MByte DDR-II memory @ 333MHz data rate. + 64 MByte Nor Flash on local bus. + 1 GByte Nand Flash on FCM. + 1 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F with 4-Port hub. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. + 2 PCIe x1 busses on local mPCIe and cutom expansion connector. + 2 SATA host ports. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 Graphics + SM107 emebedded video controller driving a 5" 800x480 TFT panel. + Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. + +2.3 FPGA + Altera Cyclone-IV EP4C115 with several PCI DMA engines. + Connects to 7x Gennum 3G-SDI transceivers as video interconnect + as well as a HDMI v1.4 compliant output for 3D monitoring. + Utilizes two more DDR-II controllers providing 256MB memory. + +2.4 I2C + Bus1: + AD7418 @ 0x50 for voltage/temp. monitoring. + SX8650 @ 0x90 touch controller for HMI. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + Bus2: + mPCIe SMBus + SiI9022A @ 0x72/0xC0 HDMI transmitter. + TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. + LMH1983 @ 0xCA video PLL. + DS1338C @ 0xD0 real-time clock with embedded crystal. + 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. + +3 Flash layout. + + reset vector is 0x00000100, i.e. low boot. + + 00000000 u-boot binary. + 00100000 FPGA raw bit file. + 00300000 FIT image holding kernel, dtb and rescue squashfs. + 03d00000 u-boot environment. + 03e00000 splash image + + mtd partitions are propagated to linux kernel via device tree blob.

Signed-off-by: Andre Schwarz andre.schwarz@matrix-vision.de --- MAINTAINERS | 1 + boards.cfg | 1 + 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS index 4756f14..0720659 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -442,6 +442,7 @@ Peter De Schrijver p2@mind.be

Andre Schwarz andre.schwarz@matrix-vision.de

+ mergerbox MPC8377 mvbc_p MPC5200 mvblm7 MPC8343 mvsmr MPC5200 diff --git a/boards.cfg b/boards.cfg index 45c3102..ad10f11 100644 --- a/boards.cfg +++ b/boards.cfg @@ -471,6 +471,7 @@ MPC837XEMDS powerpc mpc83xx mpc837xemds freesca MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI MPC837XERDB powerpc mpc83xx mpc837xerdb freescale kmeter1 powerpc mpc83xx kmeter1 keymile +MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP

Signed-off-by: Andre Schwarz andre.schwarz@matrix-vision.de --- board/matrix_vision/mergerbox/Makefile | 51 ++++++ board/matrix_vision/mergerbox/fpga.c | 175 +++++++++++++++++++++ board/matrix_vision/mergerbox/fpga.h | 30 ++++ board/matrix_vision/mergerbox/mergerbox.c | 241 +++++++++++++++++++++++++++++ board/matrix_vision/mergerbox/mergerbox.h | 67 ++++++++ board/matrix_vision/mergerbox/pci.c | 134 ++++++++++++++++ board/matrix_vision/mergerbox/sm107.c | 126 +++++++++++++++ 7 files changed, 824 insertions(+), 0 deletions(-) create mode 100644 board/matrix_vision/mergerbox/Makefile create mode 100644 board/matrix_vision/mergerbox/fpga.c create mode 100644 board/matrix_vision/mergerbox/fpga.h create mode 100644 board/matrix_vision/mergerbox/mergerbox.c create mode 100644 board/matrix_vision/mergerbox/mergerbox.h create mode 100644 board/matrix_vision/mergerbox/pci.c create mode 100644 board/matrix_vision/mergerbox/sm107.c

diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile new file mode 100644 index 0000000..2b78c98 --- /dev/null +++ b/board/matrix_vision/mergerbox/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o pci.o fpga.o sm107.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c new file mode 100644 index 0000000..673bc2c --- /dev/null +++ b/board/matrix_vision/mergerbox/fpga.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2011 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include "mergerbox.h" +#include "fpga.h" + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + passive_serial, + Altera_EP2C20_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mergerbox_init_fpga(void) +{ + debug("Initialize FPGA interface\n"); + fpga_init(); + fpga_add(fpga_altera, &cyclone2); + + return 1; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + dvo &= ~FPGA_CONFIG; + gpio->dat = dvo; + udelay(5); + dvo |= FPGA_CONFIG; + gpio->dat = dvo; + + return assert; +} + +int fpga_done_fn(int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + int result = 0; + + udelay(10); + debug("CONF_DONE check ... "); + if (gpio->dat & FPGA_CONF_DONE) { + debug("high\n"); + result = 1; + } else + debug("low\n"); + + return result; +} + +int fpga_status_fn(int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + int result = 0; + + debug("STATUS check ... "); + if (gpio->dat & FPGA_STATUS) { + debug("high\n"); + result = 1; + } else + debug("low\n"); + + return result; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + debug("CLOCK %s\n", assert_clk ? "high" : "low"); + if (assert_clk) + dvo |= FPGA_CCLK; + else + dvo &= ~FPGA_CCLK; + + if (flush) + gpio->dat = dvo; + + return assert_clk; +} + +static inline int _write_fpga(u8 val, int dump) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + int i; + u32 dvo = gpio->dat; + + if (dump) + debug(" %02x -> ", val); + for (i = 0; i < 8; i++) { + dvo &= ~FPGA_CCLK; + gpio->dat = dvo; + dvo &= ~FPGA_DIN; + if (dump) + debug("%d ", val&1); + if (val & 1) + dvo |= FPGA_DIN; + gpio->dat = dvo; + dvo |= FPGA_CCLK; + gpio->dat = dvo; + val >>= 1; + } + if (dump) + debug("\n"); + + return 0; +} + +int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i], 0); + debug("\n"); + + return FPGA_SUCCESS; +} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h new file mode 100644 index 0000000..fccff9f --- /dev/null +++ b/board/matrix_vision/mergerbox/fpga.h @@ -0,0 +1,30 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mergerbox_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c new file mode 100644 index 0000000..8616205 --- /dev/null +++ b/board/matrix_vision/mergerbox/mergerbox.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> +#include <fdt_support.h> +#include <spd_sdram.h> +#include "mergerbox.h" +#include "fpga.h" +#include "../common/mv_common.h" + +static void setup_serdes(void) +{ + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); +} + +#if defined(CONFIG_SYS_DRAM_TEST) +int testdram(void) +{ + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +phys_size_t initdram(int board_type) +{ + u32 msize; + + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; + + /* Enable PCI_CLK[0:1] */ + clk->occr |= 0xc0000000; + udelay(2000); + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize_log2; + + msize = CONFIG_SYS_DDR_SIZE; + msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + __asm__ __volatile__("sync"); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); +#endif + setup_serdes(); + + return msize << 20; +} + +int checkboard(void) +{ + puts("Board: Matrix Vision MergerBox\n"); + + return 0; +} + +int misc_init_r(void) +{ + u16 dim; + int result; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; + unsigned char mac[6], mac_verify[6]; + char *s = getenv("reset_env"); + + for (dim = 10; dim < 180; dim += 5) { + mergerbox_tft_dim(dim); + udelay(100000); + } + + if (s) + mv_reset_environment(); + + i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); + + /* check if Matrix Vision prefix present and export to env */ + if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { + printf("valid MAC found in eeprom: %pM\n", mac); + eth_setenv_enetaddr("ethaddr", mac); + } else { + printf("no valid MAC found in eeprom.\n"); + + /* no: check the env */ + if (!eth_getenv_enetaddr("ethaddr", mac)) { + printf("no valid MAC found in env either.\n"); + /* TODO: ask for valid MAC */ + } else { + printf("valid MAC found in env: %pM\n", mac); + printf("updating MAC in eeprom.\n"); + + do { + result = test_and_clear_bit(20, &gpio->dat); + if (result) + printf("unprotect EEPROM failed !\n"); + udelay(20000); + } while(result); + + i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); + udelay(20000); + + do { + result = test_and_set_bit(20, &gpio->dat); + if (result) + printf("protect EEPROM failed !\n"); + udelay(20000); + } while(result); + + printf("verify MAC %pM ... ", mac); + i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); + + if (!strncmp((char *)mac, (char *)mac_verify, 6)) + printf("ok.\n"); + else + /* TODO: retry or do something useful */ + printf("FAILED (got %pM) !\n", mac_verify); + } + } + + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + + iopd->dat &= ~TFT_SPI_CPLD_CS; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + + iopd->dat |= TFT_SPI_CPLD_CS; +} + +/* control backlight pwm (display brightness). + * allow values 0-250 with 0 = turn off and 250 = max brightness + */ +void mergerbox_tft_dim(u16 value) +{ + struct spi_slave *slave; + u16 din; + u16 dout = 0; + + if (value > 0 && value < 250) + dout = 0x4000 | value; + + slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); + spi_claim_bus(slave); + spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); + spi_release_bus(slave); + spi_free_slave(slave); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); + ft_pci_setup(blob, bd); +} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h new file mode 100644 index 0000000..d666d07 --- /dev/null +++ b/board/matrix_vision/mergerbox/mergerbox.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __MERGERBOX_H__ +#define __MERGERBOX_H__ + +#define MV_GPIO + +/* + * GPIO Bank 1 + */ +#define TFT_SPI_EN (0x80000000>>0) +#define FPGA_CONFIG (0x80000000>>1) +#define FPGA_STATUS (0x80000000>>2) +#define FPGA_CONF_DONE (0x80000000>>3) +#define FPGA_DIN (0x80000000>>4) +#define FPGA_CCLK (0x80000000>>5) +#define MAN_RST (0x80000000>>6) +#define FPGA_SYS_RST (0x80000000>>7) +#define WD_WDI (0x80000000>>8) +#define TFT_RST (0x80000000>>9) +#define HISCON_GPIO1 (0x80000000>>10) +#define HISCON_GPIO2 (0x80000000>>11) +#define B2B_GPIO2 (0x80000000>>12) +#define CCU_GPIN (0x80000000>>13) +#define CCU_GPOUT (0x80000000>>14) +#define TFT_GPIO0 (0x80000000>>15) +#define TFT_GPIO1 (0x80000000>>16) +#define TFT_GPIO2 (0x80000000>>17) +#define TFT_GPIO3 (0x80000000>>18) +#define B2B_GPIO0 (0x80000000>>19) +#define B2B_GPIO1 (0x80000000>>20) +#define TFT_SPI_CPLD_CS (0x80000000>>21) +#define TFT_SPI_CS (0x80000000>>22) +#define CCU_PWR_EN (0x80000000>>23) +#define B2B_GPIO3 (0x80000000>>24) +#define CCU_PWR_STAT (0x80000000>>25) + +#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) +#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ + TFT_SPI_CPLD_CS) +#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) + +/* + * GPIO Bank 2 + */ +#define SPI_FLASH_WP (0x80000000>>10) +#define SYS_EEPROM_WP (0x80000000>>11) +#define SPI_FLASH_CS (0x80000000>>22) + +#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) +#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) +#define MV_GPIO2_ODE 0 + +void mergerbox_tft_dim(u16 value); + +#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c new file mode 100644 index 0000000..8bc8342 --- /dev/null +++ b/board/matrix_vision/mergerbox/pci.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <mpc83xx.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> +#include "mergerbox.h" +#include "fpga.h" +#include "../common/mv_common.h" + +static struct pci_region pci_regions[] = { + { + .bus_start = CONFIG_SYS_PCI_MEM_BASE, + .phys_start = CONFIG_SYS_PCI_MEM_PHYS, + .size = CONFIG_SYS_PCI_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + .bus_start = CONFIG_SYS_PCI_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, + .size = CONFIG_SYS_PCI_MMIO_SIZE, + .flags = PCI_REGION_MEM + }, + { + .bus_start = CONFIG_SYS_PCI_IO_BASE, + .phys_start = CONFIG_SYS_PCI_IO_PHYS, + .size = CONFIG_SYS_PCI_IO_SIZE, + .flags = PCI_REGION_IO + } +}; + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; + + volatile gpio83xx_t *gpio; + gpio = (gpio83xx_t *)&immr->gpio[0]; + + gpio->dat = MV_GPIO1_DAT; + gpio->odr = MV_GPIO1_ODE; + gpio->dir = MV_GPIO1_OUT; + + gpio = (gpio83xx_t *)&immr->gpio[1]; + + gpio->dat = MV_GPIO2_DAT; + gpio->odr = MV_GPIO2_ODE; + gpio->dir = MV_GPIO2_OUT; + + printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, + immr->sysconf.sicrl); + + /* Enable PCI_CLK[0:1] */ + clk->occr |= 0xc0000000; + udelay(2000); + + mergerbox_init_fpga(); + mv_load_fpga(); + + mergerbox_tft_dim(0); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + udelay(2000); + + mpc83xx_pci_init(1, reg); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); +} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c new file mode 100644 index 0000000..db716b2 --- /dev/null +++ b/board/matrix_vision/mergerbox/sm107.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/io.h> +#include <ns16550.h> +#include <netdev.h> +#include <sm501.h> +#include <pci.h> +#include "../common/mv_common.h" + +#ifdef CONFIG_VIDEO +static const SMI_REGS init_regs_800x480[] = { + /* set endianess to little endian */ + {0x0005c, 0x00000000}, + /* PCI drive 12mA */ + {0x00004, 0x42401001}, + /* current clock */ + {0x0003c, 0x310a1818}, + /* clocks for pm0... */ + {0x00040, 0x0002184f}, + {0x00044, 0x2a1a0a01}, + /* GPIO */ + {0x10008, 0x00000000}, + {0x1000C, 0x00000000}, + /* panel control regs */ + {0x80000, 0x0f017106}, + {0x80004, 0x0}, + {0x80008, 0x0}, + {0x8000C, 0x00000000}, + {0x80010, 0x0c800c80}, + /* width 0x320 */ + {0x80014, 0x03200000}, + /* height 0x1e0 */ + {0x80018, 0x01E00000}, + {0x8001C, 0x0}, + {0x80020, 0x01df031f}, + {0x80024, 0x041f031f}, + {0x80028, 0x00800347}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00000000}, + /* ZV[0:7] */ + {0x00008, 0x00ff0000}, + /* 24-Bit TFT */ + {0x0000c, 0x3f000000}, + {0, 0} +}; + +/* + * Returns SM107 register base address. First thing called in the driver. + */ +unsigned int board_video_init(void) +{ + pci_dev_t devbusfn; + u32 addr; + + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, + (u32 *)&addr); + return addr & 0xfffffffe; + } + + return 0; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen(unsigned int base) +{ +} + +/* + * Returns SM107 framebuffer address + */ +unsigned int board_video_get_fb(void) +{ + pci_dev_t devbusfn; + u32 addr; + + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, + (u32 *)&addr); + addr &= 0xfffffffe; +#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET + addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; +#endif + return addr; + } + + printf("board_video_get_fb(): FAILED\n"); + + return 0; +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs(void) +{ + return init_regs_800x480; +} + +int board_get_width(void) +{ + return 800; +} + +int board_get_height(void) +{ + return 480; +} +#endif