From: Zhong Hongbo bocui107@gmail.com

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - Replace the magic numbers with variable name. Change for V2: - Change the type of the return value from unsinged int to unsinged long for s3c64xx_get_base_uart function. - Delete const for the local variable. --- arch/arm/include/asm/arch-s3c64xx/nand.h | 72 ++++++++++++++++++++++++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 79 ++------------------------- board/samsung/smdk6400/lowlevel_init.S | 1 + drivers/mtd/nand/s3c64xx.c | 58 +++++++++++++------- 4 files changed, 116 insertions(+), 94 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h

diff --git a/arch/arm/include/asm/arch-s3c64xx/nand.h b/arch/arm/include/asm/arch-s3c64xx/nand.h new file mode 100644 index 0000000..a1bf3ab --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/nand.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2012 + * Zhong Hongbo bocui107@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_NAND_H__ +#define __ASM_ARCH_NAND_H__ + +#define NFCONF_OFFSET 0x00 +#define NFCONT_OFFSET 0x04 + +#define NFCONF_ECC_4BIT (1<<24) + +#define NFCONT_ECC_ENC (1<<18) +#define NFCONT_WP (1<<16) +#define NFCONT_MECCLOCK (1<<7) +#define NFCONT_SECCLOCK (1<<6) +#define NFCONT_INITMECC (1<<5) +#define NFCONT_INITSECC (1<<4) +#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) +#define NFCONT_CS_ALT (1<<2) +#define NFCONT_CS (1<<1) +#define NFCONT_ENABLE (1<<0) + +#define NFSTAT_ECCENCDONE (1<<7) +#define NFSTAT_ECCDECDONE (1<<6) +#define NFSTAT_RnB (1<<0) + +#define NFESTAT0_ECCBUSY (1<<31) + +#ifndef __ASSEMBLY__ +/* NAND FLASH */ +struct s3c64xx_nand { + u32 nfconf; + u32 nfcont; + u32 nfcmmd; + u32 nfaddr; + u32 nfdata; + u32 nfmeccdata0; + u32 nfmeccdata1; + u32 nfseccdata0; + u32 nfsblk; + u32 nfeblk; + u32 nfstat; + u32 nfestat0; + u32 nfestat1; + u32 nfmecc0; + u32 nfmecc1; + u32 nfsecc; + u32 nfmlcbitpt; +}; +#endif + +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index 10b3324..d6c5dd9 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -556,80 +556,6 @@ */ #define ELFIN_NAND_BASE 0x70200000

-#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 - -#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_4BIT (1<<24) - -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<2) -#define NFCONT_CS (1<<1) -#define NFCONT_ENABLE (1<<0) - -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) - -#define NFESTAT0_ECCBUSY (1<<31) - /* * Interrupt */ @@ -890,6 +816,11 @@ static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) { return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); } + +static inline unsigned long s3c64xx_get_base_nand(void) +{ + return ELFIN_NAND_BASE; +} #endif

#endif /*__S3C6400_H__*/ diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index f7ce176..8bded44 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -34,6 +34,7 @@ #include <config.h> #include <version.h>

+#include <asm/arch/nand.h> #include <asm/arch/s3c6400.h>

#ifdef CONFIG_SERIAL1 diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index 87f0341..3199bf1 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -31,6 +31,7 @@ #include <linux/mtd/nand.h>

#include <asm/arch/s3c6400.h> +#include <asm/arch/nand.h>

#include <asm/io.h> #include <asm/errno.h> @@ -42,6 +43,11 @@ static int nand_cs[MAX_CHIPS] = {0, 1}; #define printf(arg...) do {} while (0) #endif

+static inline struct s3c64xx_nand *s3c_get_base_nand(void) +{ + return (struct s3c64xx_nand *)s3c64xx_get_base_nand(); +} + /* Nand flash definition values by jsgood */ #ifdef S3C_NAND_DEBUG /* @@ -64,7 +70,8 @@ static void print_oob(const char *header, struct mtd_info *mtd)

static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) { - int ctrl = readl(NFCONT); + struct s3c64xx_nand *nand = s3c_get_base_nand(); + int ctrl = readl(&nand->nfcont);

switch (chip) { case -1: @@ -80,7 +87,7 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) return; }

- writel(ctrl, NFCONT); + writel(ctrl, &nand->nfcont); }

/* @@ -89,15 +96,16 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) */ static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { + struct s3c64xx_nand *nand = s3c_get_base_nand(); struct nand_chip *this = mtd->priv;

if (ctrl & NAND_CTRL_CHANGE) { if (ctrl & NAND_CLE) - this->IO_ADDR_W = (void __iomem *)NFCMMD; + this->IO_ADDR_W = (void *)&nand->nfcmmd; else if (ctrl & NAND_ALE) - this->IO_ADDR_W = (void __iomem *)NFADDR; + this->IO_ADDR_W = (void *)&nand->nfaddr; else - this->IO_ADDR_W = (void __iomem *)NFDATA; + this->IO_ADDR_W = (void *)&nand->nfdata; if (ctrl & NAND_NCE) s3c_nand_select_chip(mtd, *(int *)this->priv); else @@ -114,7 +122,9 @@ static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) */ static int s3c_nand_device_ready(struct mtd_info *mtdinfo) { - return !!(readl(NFSTAT) & NFSTAT_RnB); + struct s3c64xx_nand *nand = s3c_get_base_nand(); + + return !!(readl(&nand->nfstat) & NFSTAT_RnB); }

#ifdef CONFIG_SYS_S3C_NAND_HWECC @@ -124,6 +134,7 @@ static int s3c_nand_device_ready(struct mtd_info *mtdinfo) */ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) { + struct s3c64xx_nand *nand = s3c_get_base_nand(); u_long nfcont, nfconf;

/* @@ -131,12 +142,12 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) * those with non-zero ID[3][3:2], which anyway only holds for ST * (Numonyx) chips */ - nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT; + nfconf = readl(&nand->nfconf) & ~NFCONF_ECC_4BIT;

- writel(nfconf, NFCONF); + writel(nfconf, &nand->nfconf);

/* Initialize & unlock */ - nfcont = readl(NFCONT); + nfcont = readl(&nand->nfcont); nfcont |= NFCONT_INITECC; nfcont &= ~NFCONT_MECCLOCK;

@@ -145,7 +156,7 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) else if (mode == NAND_ECC_READ) nfcont &= ~NFCONT_ECC_ENC;

- writel(nfcont, NFCONT); + writel(nfcont, &nand->nfcont); }

/* @@ -156,14 +167,15 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { + struct s3c64xx_nand *nand = s3c_get_base_nand(); u_long nfcont, nfmecc0;

/* Lock */ - nfcont = readl(NFCONT); + nfcont = readl(&nand->nfcont); nfcont |= NFCONT_MECCLOCK; - writel(nfcont, NFCONT); + writel(nfcont, &nand->nfcont);

- nfmecc0 = readl(NFMECC0); + nfmecc0 = readl(&nand->nfmecc0);

ecc_code[0] = nfmecc0 & 0xff; ecc_code[1] = (nfmecc0 >> 8) & 0xff; @@ -185,18 +197,19 @@ static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - int ret = -1; + struct s3c64xx_nand *nand = s3c_get_base_nand(); u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr; u_char err_type, repaired; + int ret = -1;

/* SLC: Write ecc to compare */ nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0]; nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2]; - writel(nfmeccdata0, NFMECCDATA0); - writel(nfmeccdata1, NFMECCDATA1); + writel(nfmeccdata0, &nand->nfmeccdata0); + writel(nfmeccdata1, &nand->nfmeccdata1);

/* Read ecc status */ - nfestat0 = readl(NFESTAT0); + nfestat0 = readl(&nand->nfestat0); err_type = nfestat0 & 0x3;

switch (err_type) { @@ -254,15 +267,20 @@ static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, */ int board_nand_init(struct nand_chip *nand) { + struct s3c64xx_nand *nand_reg = s3c_get_base_nand(); static int chip_n; + unsigned int nfcont;

if (chip_n >= MAX_CHIPS) return -ENODEV;

- NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6; + nfcont = readl(&nand_reg->nfcont); + nfcont &= ~NFCONT_WP; + nfcont |= NFCONT_ENABLE | 0x6; + writel(nfcont, &nand_reg->nfcont);

- nand->IO_ADDR_R = (void __iomem *)NFDATA; - nand->IO_ADDR_W = (void __iomem *)NFDATA; + nand->IO_ADDR_R = (void *)&nand_reg->nfdata; + nand->IO_ADDR_W = (void *)&nand_reg->nfdata; nand->cmd_ctrl = s3c_nand_hwcontrol; nand->dev_ready = s3c_nand_device_ready; nand->select_chip = s3c_nand_select_chip;

From: Zhong Hongbo bocui107@gmail.com

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - None. Change for V2: - Change the type of the return value from unsinged int to unsinged long for s3c64xx_get_base_nand function. --- arch/arm/cpu/arm1176/s3c64xx/Makefile | 1 + arch/arm/cpu/arm1176/s3c64xx/pwm.c | 189 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-s3c64xx/pwm.h | 70 ++++++++++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 56 ++------- arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 59 --------- include/configs/smdk6400.h | 3 + 6 files changed, 272 insertions(+), 106 deletions(-) create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h

diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index 0785b19..966663f 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -32,6 +32,7 @@ SOBJS = reset.o

COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o COBJS-y += timer.o +COBJS-$(CONFIG_PWM) += pwm.o

OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))

diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c b/arch/arm/cpu/arm1176/s3c64xx/pwm.c new file mode 100644 index 0000000..d46470a --- /dev/null +++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2012 + * + * Zhong Hongbo bocui107@gmail.com + * + * based on arch/arm/cpu/armv7/s5p-common/sromc.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <errno.h> +#include <pwm.h> +#include <asm/io.h> +#include <asm/arch/s3c6400.h> +#include <asm/arch/pwm.h> + +int pwm_enable(int pwm_id) +{ + const struct s3c_timer *pwm = + (struct s3c_timer *)s3c64xx_get_base_timer(); + unsigned long tcon; + + tcon = readl(&pwm->tcon); + tcon |= TCON_START(pwm_id); + + writel(tcon, &pwm->tcon); + + return 0; +} + +void pwm_disable(int pwm_id) +{ + const struct s3c_timer *pwm = + (struct s3c_timer *)s3c64xx_get_base_timer(); + unsigned long tcon; + + tcon = readl(&pwm->tcon); + tcon &= ~TCON_START(pwm_id); + + writel(tcon, &pwm->tcon); +} + +static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) +{ + unsigned long tin_parent_rate; + unsigned int div; + + tin_parent_rate = get_PCLK(); + + for (div = 2; div <= 16; div *= 2) { + if ((tin_parent_rate / (div << 16)) < freq) + return tin_parent_rate / div; + } + + return tin_parent_rate / 16; +} + +#define NS_IN_HZ (1000000000UL) + +int pwm_config(int pwm_id, int duty_ns, int period_ns) +{ + const struct s3c_timer *pwm = + (struct s3c_timer *)s3c64xx_get_base_timer(); + unsigned int offset; + unsigned long tin_rate; + unsigned long tin_ns; + unsigned long period; + unsigned long tcon; + unsigned long tcnt; + unsigned long tcmp; + + /* + * We currently avoid using 64bit arithmetic by using the + * fact that anything faster than 1GHz is easily representable + * by 32bits. + */ + if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) + return -ERANGE; + + if (duty_ns > period_ns) + return -EINVAL; + + period = NS_IN_HZ / period_ns; + + /* Check to see if we are changing the clock rate of the PWM */ + tin_rate = pwm_calc_tin(pwm_id, period); + + tin_ns = NS_IN_HZ / tin_rate; + tcnt = period_ns / tin_ns; + + /* Note, counters count down */ + tcmp = duty_ns / tin_ns; + tcmp = tcnt - tcmp; + + /* + * the pwm hw only checks the compare register after a decrement, + * so the pin never toggles if tcmp = tcnt + */ + if (tcmp == tcnt) + tcmp--; + + if (tcmp < 0) + tcmp = 0; + + /* Update the PWM register block. */ + offset = pwm_id * 3; + if (pwm_id < 4) { + writel(tcnt, &pwm->tcntb0 + offset); + writel(tcmp, &pwm->tcmpb0 + offset); + } + + tcon = readl(&pwm->tcon); + tcon |= TCON_UPDATE(pwm_id); + if (pwm_id < 4) + tcon |= TCON_AUTO_RELOAD(pwm_id); + else + tcon |= TCON4_AUTO_RELOAD; + writel(tcon, &pwm->tcon); + + tcon &= ~TCON_UPDATE(pwm_id); + writel(tcon, &pwm->tcon); + + return 0; +} + +int pwm_init(int pwm_id, int div, int invert) +{ + u32 val; + const struct s3c_timer *pwm = + (struct s3c_timer *)s3c64xx_get_base_timer(); + unsigned long timer_rate_hz; + unsigned int offset, prescaler; + + /* + * Timer Freq(HZ) = + * PWM_CLK / { (prescaler_value + 1) * (divider_value) } + */ + + val = readl(&pwm->tcfg0); + if (pwm_id < 2) { + prescaler = PRESCALER_0; + val &= ~0xff; + val |= (prescaler & 0xff); + } else { + prescaler = PRESCALER_1; + val &= ~(0xff << 8); + val |= (prescaler & 0xff) << 8; + } + writel(val, &pwm->tcfg0); + val = readl(&pwm->tcfg1); + val &= ~(0xf << MUX_DIV_SHIFT(pwm_id)); + val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); + writel(val, &pwm->tcfg1); + + timer_rate_hz = get_PCLK() / ((prescaler + 1) * + (div + 1)); + + timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ; + + /* set count value */ + offset = pwm_id * 3; + writel(timer_rate_hz, &pwm->tcntb0 + offset); + + val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); + if (invert && (pwm_id < 4)) + val |= TCON_INVERTER(pwm_id); + writel(val, &pwm->tcon); + + pwm_enable(pwm_id); + + return 0; +} diff --git a/arch/arm/include/asm/arch-s3c64xx/pwm.h b/arch/arm/include/asm/arch-s3c64xx/pwm.h new file mode 100644 index 0000000..1e18f8c --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/pwm.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * based on arch/arm/include/asm/arch-s5pc1xx/pwm.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ + +/* Divider MUX */ +#define MUX_DIV_1 0 /* 1/1 period */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ + +#define MUX_DIV_SHIFT(x) (x * 4) + +#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) + +#define TCON_START(x) (1 << TCON_OFFSET(x)) +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) +#define TCON4_AUTO_RELOAD (1 << 22) + +#define TCFG1_DMA(x) (x << 20) + +#ifndef __ASSEMBLY__ +struct s3c_timer { + unsigned int tcfg0; + unsigned int tcfg1; + unsigned int tcon; + unsigned int tcntb0; + unsigned int tcmpb0; + unsigned int tcnto0; + unsigned int tcntb1; + unsigned int tcmpb1; + unsigned int tcnto1; + unsigned int tcntb2; + unsigned int res1; + unsigned int tcnto2; + unsigned int tcntb3; + unsigned int res2; + unsigned int tcnto3; + unsigned int tcntb4; + unsigned int tcnto4; + unsigned int tint_cstat; +}; +#endif +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index 77b9509..b884763 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -31,6 +31,10 @@ #ifndef __S3C6400_H__ #define __S3C6400_H__

+#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) +#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! +#endif + #define S3C64XX_UART_CHANNELS 3 #define S3C64XX_SPI_CHANNELS 2

@@ -587,51 +591,6 @@ */ #define ELFIN_TIMER_BASE 0x7F006000

-#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ -#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4, 16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF * 1) -#define COUNT_4_OFF (TCON_4_ONOFF * 0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT * 1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF * 1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) - #if defined(CONFIG_CLK_400_100_50) #define STARTUP_AMDIV 400 #define STARTUP_MDIV 400 @@ -749,8 +708,6 @@

#ifndef __ASSEMBLY__

-#include "s3c64x0.h" - static inline unsigned long s3c64xx_get_base_uart(void) { return ELFIN_UART_BASE; @@ -760,6 +717,11 @@ static inline unsigned long s3c64xx_get_base_nand(void) { return ELFIN_NAND_BASE; } + +static inline unsigned long s3c64xx_get_base_timer(void) +{ + return ELFIN_TIMER_BASE; +} #endif

#endif /*__S3C6400_H__*/ diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h deleted file mode 100644 index 7add68c..0000000 --- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2003 - * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : S3C64XX.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C64XX SoC - ************************************************/ - -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ - -#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) -#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! -#endif - -#include <asm/types.h> - -/* PWM TIMER (see manual chapter 10) */ -typedef struct { - volatile u32 TCNTB; - volatile u32 TCMPB; - volatile u32 TCNTO; -} s3c64xx_timer; - -typedef struct { - volatile u32 TCFG0; - volatile u32 TCFG1; - volatile u32 TCON; - s3c64xx_timer ch[4]; - volatile u32 TCNTB4; - volatile u32 TCNTO4; -} s3c64xx_timers; - -#endif /*__S3C64XX_H__*/ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 47326d6..3642a5c 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -141,6 +141,9 @@

#define CONFIG_SYS_HZ 1000

+/* PWM */ +#define CONFIG_PWM 1 + /*----------------------------------------------------------------------- * Stack sizes *

From: Zhong Hongbo bocui107@gmail.com

It just only do the memory init. The memory depend on the design of board.

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - None. Change for V2: - None. --- arch/arm/cpu/arm1176/s3c64xx/Makefile | 2 +- arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 135 ------------------------------- board/samsung/smdk6400/Makefile | 2 +- board/samsung/smdk6400/mem_init.S | 135 +++++++++++++++++++++++++++++++ 4 files changed, 137 insertions(+), 137 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S create mode 100644 board/samsung/smdk6400/mem_init.S

diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index 966663f..2f37431 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o

SOBJS = reset.o

-COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o +COBJS-$(CONFIG_S3C64XX) += speed.o COBJS-y += timer.o COBJS-$(CONFIG_PWM) += pwm.o

diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S deleted file mode 100644 index df88cba..0000000 --- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * Copyright (C) 2008 - * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/s3c6400.h> - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - /* DMC1 base address 0x7e001000 */ - ldr r0, =ELFIN_DMC1_BASE - - ldr r1, =0x4 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - - ldr r1, =DMC_DDR_REFRESH_PRD - str r1, [r0, #INDEX_DMC_REFRESH_PRD] - - ldr r1, =DMC_DDR_CAS_LATENCY - str r1, [r0, #INDEX_DMC_CAS_LATENCY] - - ldr r1, =DMC_DDR_t_DQSS - str r1, [r0, #INDEX_DMC_T_DQSS] - - ldr r1, =DMC_DDR_t_MRD - str r1, [r0, #INDEX_DMC_T_MRD] - - ldr r1, =DMC_DDR_t_RAS - str r1, [r0, #INDEX_DMC_T_RAS] - - ldr r1, =DMC_DDR_t_RC - str r1, [r0, #INDEX_DMC_T_RC] - - ldr r1, =DMC_DDR_t_RCD - ldr r2, =DMC_DDR_schedule_RCD - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RCD] - - ldr r1, =DMC_DDR_t_RFC - ldr r2, =DMC_DDR_schedule_RFC - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RFC] - - ldr r1, =DMC_DDR_t_RP - ldr r2, =DMC_DDR_schedule_RP - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RP] - - ldr r1, =DMC_DDR_t_RRD - str r1, [r0, #INDEX_DMC_T_RRD] - - ldr r1, =DMC_DDR_t_WR - str r1, [r0, #INDEX_DMC_T_WR] - - ldr r1, =DMC_DDR_t_WTR - str r1, [r0, #INDEX_DMC_T_WTR] - - ldr r1, =DMC_DDR_t_XP - str r1, [r0, #INDEX_DMC_T_XP] - - ldr r1, =DMC_DDR_t_XSR - str r1, [r0, #INDEX_DMC_T_XSR] - - ldr r1, =DMC_DDR_t_ESR - str r1, [r0, #INDEX_DMC_T_ESR] - - ldr r1, =DMC1_MEM_CFG - str r1, [r0, #INDEX_DMC_MEMORY_CFG] - - ldr r1, =DMC1_MEM_CFG2 - str r1, [r0, #INDEX_DMC_MEMORY_CFG2] - - ldr r1, =DMC1_CHIP0_CFG - str r1, [r0, #INDEX_DMC_CHIP_0_CFG] - - ldr r1, =DMC_DDR_32_CFG - str r1, [r0, #INDEX_DMC_USER_CONFIG] - - /* DMC0 DDR Chip 0 configuration direct command reg */ - ldr r1, =DMC_NOP0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Precharge All */ - ldr r1, =DMC_PA0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Auto Refresh 2 time */ - ldr r1, =DMC_AR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* MRS */ - ldr r1, =DMC_mDDR_EMR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Mode Reg */ - ldr r1, =DMC_mDDR_MR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Enable DMC1 */ - mov r1, #0x0 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - -check_dmc1_ready: - ldr r1, [r0, #INDEX_DMC_MEMC_STATUS] - mov r2, #0x3 - and r1, r1, r2 - cmp r1, #0x1 - bne check_dmc1_ready - nop - - mov pc, lr - - .ltorg diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile index 0d3e63b..645c8e2 100644 --- a/board/samsung/smdk6400/Makefile +++ b/board/samsung/smdk6400/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o

COBJS-y := smdk6400.o -SOBJS := lowlevel_init.o +SOBJS := lowlevel_init.o mem_init.o

SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S new file mode 100644 index 0000000..df88cba --- /dev/null +++ b/board/samsung/smdk6400/mem_init.S @@ -0,0 +1,135 @@ +/* + * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 + * + * Copyright (C) 2008 + * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/s3c6400.h> + + .globl mem_ctrl_asm_init +mem_ctrl_asm_init: + /* DMC1 base address 0x7e001000 */ + ldr r0, =ELFIN_DMC1_BASE + + ldr r1, =0x4 + str r1, [r0, #INDEX_DMC_MEMC_CMD] + + ldr r1, =DMC_DDR_REFRESH_PRD + str r1, [r0, #INDEX_DMC_REFRESH_PRD] + + ldr r1, =DMC_DDR_CAS_LATENCY + str r1, [r0, #INDEX_DMC_CAS_LATENCY] + + ldr r1, =DMC_DDR_t_DQSS + str r1, [r0, #INDEX_DMC_T_DQSS] + + ldr r1, =DMC_DDR_t_MRD + str r1, [r0, #INDEX_DMC_T_MRD] + + ldr r1, =DMC_DDR_t_RAS + str r1, [r0, #INDEX_DMC_T_RAS] + + ldr r1, =DMC_DDR_t_RC + str r1, [r0, #INDEX_DMC_T_RC] + + ldr r1, =DMC_DDR_t_RCD + ldr r2, =DMC_DDR_schedule_RCD + orr r1, r1, r2 + str r1, [r0, #INDEX_DMC_T_RCD] + + ldr r1, =DMC_DDR_t_RFC + ldr r2, =DMC_DDR_schedule_RFC + orr r1, r1, r2 + str r1, [r0, #INDEX_DMC_T_RFC] + + ldr r1, =DMC_DDR_t_RP + ldr r2, =DMC_DDR_schedule_RP + orr r1, r1, r2 + str r1, [r0, #INDEX_DMC_T_RP] + + ldr r1, =DMC_DDR_t_RRD + str r1, [r0, #INDEX_DMC_T_RRD] + + ldr r1, =DMC_DDR_t_WR + str r1, [r0, #INDEX_DMC_T_WR] + + ldr r1, =DMC_DDR_t_WTR + str r1, [r0, #INDEX_DMC_T_WTR] + + ldr r1, =DMC_DDR_t_XP + str r1, [r0, #INDEX_DMC_T_XP] + + ldr r1, =DMC_DDR_t_XSR + str r1, [r0, #INDEX_DMC_T_XSR] + + ldr r1, =DMC_DDR_t_ESR + str r1, [r0, #INDEX_DMC_T_ESR] + + ldr r1, =DMC1_MEM_CFG + str r1, [r0, #INDEX_DMC_MEMORY_CFG] + + ldr r1, =DMC1_MEM_CFG2 + str r1, [r0, #INDEX_DMC_MEMORY_CFG2] + + ldr r1, =DMC1_CHIP0_CFG + str r1, [r0, #INDEX_DMC_CHIP_0_CFG] + + ldr r1, =DMC_DDR_32_CFG + str r1, [r0, #INDEX_DMC_USER_CONFIG] + + /* DMC0 DDR Chip 0 configuration direct command reg */ + ldr r1, =DMC_NOP0 + str r1, [r0, #INDEX_DMC_DIRECT_CMD] + + /* Precharge All */ + ldr r1, =DMC_PA0 + str r1, [r0, #INDEX_DMC_DIRECT_CMD] + + /* Auto Refresh 2 time */ + ldr r1, =DMC_AR0 + str r1, [r0, #INDEX_DMC_DIRECT_CMD] + str r1, [r0, #INDEX_DMC_DIRECT_CMD] + + /* MRS */ + ldr r1, =DMC_mDDR_EMR0 + str r1, [r0, #INDEX_DMC_DIRECT_CMD] + + /* Mode Reg */ + ldr r1, =DMC_mDDR_MR0 + str r1, [r0, #INDEX_DMC_DIRECT_CMD] + + /* Enable DMC1 */ + mov r1, #0x0 + str r1, [r0, #INDEX_DMC_MEMC_CMD] + +check_dmc1_ready: + ldr r1, [r0, #INDEX_DMC_MEMC_STATUS] + mov r2, #0x3 + and r1, r1, r2 + cmp r1, #0x1 + bne check_dmc1_ready + nop + + mov pc, lr + + .ltorg

From: Zhong Hongbo bocui107@gmail.com

Adopt the new SPL framework to implement the SPL booting of the nand flash for S3C6400.

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - None. Change for V2: - seprate some code. --- arch/arm/cpu/arm1176/start.S | 16 +--- board/samsung/smdk6400/Makefile | 29 +++++- board/samsung/smdk6400/lowlevel_init.S | 22 ++-- board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++++++++++-- board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++++++++++++++++++++++ drivers/mtd/nand/s3c64xx.c | 4 +- include/configs/smdk6400.h | 21 +++-- 7 files changed, 221 insertions(+), 49 deletions(-) create mode 100644 board/samsung/smdk6400/tools/mksmdk6400_image.c

diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index d613641..761b7fe 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -51,7 +51,7 @@

.globl _start _start: b reset -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -164,7 +164,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * flush v4 I/D caches */ @@ -357,21 +357,14 @@ clbss_l:cmp r0, r1 /* clear loop... */ add r0, r0, #4 b clbss_l clbss_e: -#ifndef CONFIG_NAND_SPL bl coloured_LED_init bl red_led_on #endif -#endif

/* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot - -_nand_boot: .word nand_boot -#else ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 @@ -384,7 +377,6 @@ _nand_boot: .word nand_boot

_board_init_r_ofs: .word board_init_r - _start -#endif

_rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -398,7 +390,7 @@ _mmu_table_base: .word mmu_table #endif

-#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * we assume that cache operation is done before. (eg. cleanup_before_linux()) * actually, we don't need to do anything about cache if not use d-cache in @@ -576,4 +568,4 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile index 645c8e2..f7fa667 100644 --- a/board/samsung/smdk6400/Makefile +++ b/board/samsung/smdk6400/Makefile @@ -28,15 +28,34 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(BOARD).o

+ifndef CONFIG_SPL_BUILD COBJS-y := smdk6400.o +endif + SOBJS := lowlevel_init.o mem_init.o

-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +ifdef CONFIG_SPL_BUILD +COBJS-y += smdk6400_nand_spl.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) + +ALL := $(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL += $(OBJTREE)/tools/mk$(BOARD)spl +endif + +all: $(ALL) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS))

-$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) +ifdef CONFIG_SPL_BUILD +$(OBJTREE)/tools/mk$(BOARD)spl: tools/mksmdk6400_image.c + $(HOSTCC) tools/mksmdk6400_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +endif

#########################################################################

diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 45887f3..93172e7 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -84,18 +84,12 @@ lowlevel_init: str r3, [r0, #oVECTADDR] str r3, [r1, #oVECTADDR]

+#ifdef CONFIG_SPL_BUILD /* init system clock */ - bl system_clock_init + bl system_clock_init

-#ifndef CONFIG_NAND_SPL - /* for UART */ - bl uart_asm_init -#endif - -#ifdef CONFIG_BOOT_NAND /* simple init for NAND */ - bl nand_asm_init -#endif + bl nand_asm_init

/* Memory subsystem address 0x7e00f120 */ ldr r0, =ELFIN_MEM_SYS_CFG @@ -105,6 +99,12 @@ lowlevel_init: str r1, [r0]

bl mem_ctrl_asm_init +#endif + +#ifndef CONFIG_SPL_BUILD + /* for UART */ + bl uart_asm_init +#endif

/* Wakeup support. Don't know if it's going to be used, untested. */ ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) @@ -244,7 +244,7 @@ wait_for_async: mov pc, lr

-#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * uart_asm_init: Initialize UART's pins */ @@ -256,7 +256,7 @@ uart_asm_init: mov pc, lr #endif

-#ifdef CONFIG_BOOT_NAND +#ifdef CONFIG_SPL_BUILD /* * NAND Interface init for SMDK6400 */ diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/board/samsung/smdk6400/smdk6400_nand_spl.c index a023284..34649a2 100644 --- a/board/samsung/smdk6400/smdk6400_nand_spl.c +++ b/board/samsung/smdk6400/smdk6400_nand_spl.c @@ -1,13 +1,6 @@ /* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de + * Copyright (C) 2012 + * Zhong Hongbo bocui107@gmail.com * * See file CREDITS for list of people who contributed to this * project. @@ -29,9 +22,55 @@ */

#include <common.h> +#include <config.h> +#include <nand.h>

void board_init_f(unsigned long bootflag) { - relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); + /* + * We call relocate_code() with relocation target same as the + * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting + * skipped. Instead, only .bss initialization will happen. That's + * all we need + */ + relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE); +} + +void board_init_r(gd_t *id, ulong dest_addr) +{ + __attribute__((noreturn)) void (*uboot)(void); + + spl_nand_copy(); + /* + * Jump to U-Boot image + */ + uboot = (void *)CONFIG_SYS_UBOOT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +void spl_nand_copy(void) +{ + /* + * Init board specific nand support + */ + nand_init(); + /* + * Load U-Boot image from NAND into RAM + */ + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_UBOOT_BASE); + +#ifdef CONFIG_NAND_ENV_DST + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST); + +#ifdef CONFIG_ENV_OFFSET_REDUND + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); +#endif +#endif + + nand_deselect(); } diff --git a/board/samsung/smdk6400/tools/mksmdk6400_image.c b/board/samsung/smdk6400/tools/mksmdk6400_image.c new file mode 100644 index 0000000..1a51913 --- /dev/null +++ b/board/samsung/smdk6400/tools/mksmdk6400_image.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <fcntl.h> +#include <errno.h> +#include <string.h> +#include <sys/stat.h> + +#define CHECKSUM_OFFSET (14*1024-4) +#define BUFSIZE (16*1024) +#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ + | S_IWGRP | S_IROTH | S_IWOTH) +/* +* Requirement: +* IROM code reads first 14K bytes from boot device. +* It then calculates the checksum of 14K-4 bytes and compare with data at +* 14K-4 offset. +* +* This function takes two filenames: +* IN "u-boot-spl.bin" and +* OUT "u-boot-mmc-spl.bin" as filenames. +* It reads the "u-boot-spl.bin" in 16K buffer. +* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. +* It writes the buffer to "u-boot-mmc-spl.bin" file. +*/ + +int main(int argc, char **argv) +{ + int i, len; + unsigned char buffer[BUFSIZE] = {0}; + int ifd, ofd; + unsigned int checksum = 0, count; + + if (argc != 3) { + printf(" %d Wrong number of arguments\n", argc); + exit(EXIT_FAILURE); + } + + ifd = open(argv[1], O_RDONLY); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[1], strerror(errno)); + exit(EXIT_FAILURE); + } + + ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[2], strerror(errno)); + if (ifd) + close(ifd); + exit(EXIT_FAILURE); + } + + len = lseek(ifd, 0, SEEK_END); + lseek(ifd, 0, SEEK_SET); + + count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; + + if (read(ifd, buffer, count) != count) { + fprintf(stderr, "%s: Can't read %s: %s\n", + argv[0], argv[1], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++) + checksum += buffer[i]; + + memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum)); + + if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { + fprintf(stderr, "%s: Can't write %s: %s\n", + argv[0], argv[2], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + return EXIT_SUCCESS; +} diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index 3199bf1..b85b641 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -39,7 +39,7 @@ #define MAX_CHIPS 2 static int nand_cs[MAX_CHIPS] = {0, 1};

-#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD #define printf(arg...) do {} while (0) #endif

@@ -285,7 +285,7 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = s3c_nand_device_ready; nand->select_chip = s3c_nand_select_chip; nand->options = 0; -#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD nand->read_byte = nand_read_byte; nand->write_buf = nand_write_buf; nand->read_buf = nand_read_buf; diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 06b85bf..41c7163 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -238,11 +238,10 @@ #define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */ #define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */

-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */ - -#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ +/* Offset to RAM U-Boot image */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 * 1024) +/* Size of RAM U-Boot image */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024)

/* NAND chip page size */ #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -266,8 +265,6 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63}

-/* Boot configuration (define only one of next 3) */ -#define CONFIG_BOOT_NAND /* None of these are currently implemented. Left from the original Samsung * version for reference #define CONFIG_BOOT_NOR @@ -275,7 +272,15 @@ #define CONFIG_BOOT_ONENAND */

-#define CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_SPL_NAND +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_STACK CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_MALLOC_LEN +#define CONFIG_SPL_LIBGENERIC_SUPPORT + #define CONFIG_NAND_S3C64XX /* Unimplemented or unsupported. See comment above. #define CONFIG_ONENAND

From: Zhong Hongbo bocui107@gmail.com

When It do not need to relocat for u-boot, the offset(r9) of relocation should be set zero.

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - Replace mov with moveq. Change for V2: - Seprate some code. --- arch/arm/cpu/arm1176/start.S | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 761b7fe..dd1b73b 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -252,6 +252,7 @@ stack_setup:

adr r0, _start cmp r0, r6 + moveq r9, #0 beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs

From: Zhong Hongbo bocui107@gmail.com

Switch to use read/writel function and clear the relevant variable.

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - Use C language to re-write reset function. - Replace the magic numbers witch variale name. Change for V2: - merge clock patch. - Change the type of return for s3c64xx_get_base_clock function. --- arch/arm/cpu/arm1176/s3c64xx/Makefile | 6 +- arch/arm/cpu/arm1176/s3c64xx/reset.S | 34 ---- arch/arm/cpu/arm1176/s3c64xx/reset.c | 39 +++++ arch/arm/cpu/arm1176/s3c64xx/speed.c | 50 +++++-- arch/arm/include/asm/arch-s3c64xx/clock.h | 163 ++++++++++++++++++++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 219 +-------------------------- board/samsung/smdk6400/lowlevel_init.S | 3 + board/samsung/smdk6400/setup.h | 47 ++++++ drivers/usb/host/s3c64xx-hcd.c | 30 ++++- 9 files changed, 321 insertions(+), 270 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.S create mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.c create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h create mode 100644 board/samsung/smdk6400/setup.h

diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index 28786bf..16be887 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -28,13 +28,11 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(SOC).o

-SOBJS = reset.o - -COBJS-$(CONFIG_S3C64XX) += speed.o srom.o +COBJS-$(CONFIG_S3C64XX) += speed.o srom.o reset.o COBJS-y += timer.o COBJS-$(CONFIG_PWM) += pwm.o

-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) +OBJS := $(addprefix $(obj), $(COBJS-y))

all: $(obj).depend $(START) $(LIB)

diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S deleted file mode 100644 index eae572e..0000000 --- a/arch/arm/cpu/arm1176/s3c64xx/reset.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2009 Samsung Electronics. - * Minkyu Kang mk7.kang@samsung.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/s3c6400.h> - -.globl reset_cpu -reset_cpu: - ldr r1, =ELFIN_CLOCK_POWER_BASE - ldr r2, [r1, #SYS_ID_OFFSET] - ldr r3, =0xffff - and r2, r3, r2, lsr #12 - str r2, [r1, #SW_RST_OFFSET] -_loop_forever: - b _loop_forever diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.c b/arch/arm/cpu/arm1176/s3c64xx/reset.c new file mode 100644 index 0000000..773cffa --- /dev/null +++ b/arch/arm/cpu/arm1176/s3c64xx/reset.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/s3c6400.h> +#include <asm/arch/clock.h> + +void reset_cpu(ulong addr) +{ + unsigned long sys_id; + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); + + sys_id = readl(&clk->sys_id); + sys_id >>= 12; + sys_id &= 0xffff; + writel(sys_id, &clk->sw_rst); +} diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c index 11962ac..05b44b9 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/speed.c +++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c @@ -31,12 +31,13 @@ */

#include <common.h> +#include <asm/io.h> #include <asm/arch/s3c6400.h> +#include <asm/arch/clock.h>

#define APLL 0 #define MPLL 1 #define EPLL 2 - /* ------------------------------------------------------------------------- */ /* * NOTE: This describes the proper use of this file. @@ -50,17 +51,20 @@

static ulong get_PLLCLK(int pllreg) { + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); + ulong r, m, p, s;

switch (pllreg) { case APLL: - r = APLL_CON_REG; + r = readl(&clk->apll_con); break; case MPLL: - r = MPLL_CON_REG; + r = readl(&clk->mpll_con); break; case EPLL: - r = EPLL_CON0_REG; + r = readl(&clk->epll_con0); break; default: hang(); @@ -76,9 +80,11 @@ static ulong get_PLLCLK(int pllreg) /* return ARMCORE frequency */ ulong get_ARMCLK(void) { + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); ulong div;

- div = CLK_DIV0_REG; + div = readl(&clk->clk_div0);

return get_PLLCLK(APLL) / ((div & 0x7) + 1); } @@ -92,16 +98,20 @@ ulong get_FCLK(void) /* return HCLK frequency */ ulong get_HCLK(void) { + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); ulong fclk; + ulong other;

- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1; - uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1; + uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1; + uint hclk_div = ((readl(&clk->clk_div0) >> 8) & 0x1) + 1;

/* * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on * s3c6400 and is always 0, and it is indeed running in ASYNC mode */ - if (OTHERS_REG & 0x80) + other = readl(&clk->others); + if (other & 0x80) fclk = get_FCLK(); /* SYNC Mode */ else fclk = get_PLLCLK(MPLL); /* ASYNC Mode */ @@ -112,11 +122,15 @@ ulong get_HCLK(void) /* return PCLK frequency */ ulong get_PCLK(void) { + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); ulong fclk; - uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1; - uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1; + uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1; + uint pre_div = ((readl(&clk->clk_div0) >> 12) & 0xf) + 1; + ulong other;

- if (OTHERS_REG & 0x80) + other = readl(&clk->others); + if (other & 0x80) fclk = get_FCLK(); /* SYNC Mode */ else fclk = get_PLLCLK(MPLL); /* ASYNC Mode */ @@ -132,14 +146,20 @@ ulong get_UCLK(void)

int print_cpuinfo(void) { - printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000); + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); + ulong other; + + printf("\nCPU: S3C64XX@%luMHz\n", get_ARMCLK() / 1000000); printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ", get_FCLK() / 1000000, get_HCLK() / 1000000, get_PCLK() / 1000000);

- if (OTHERS_REG & 0x80) - printf("(SYNC Mode) \n"); + other = readl(&clk->others); + if (other & 0x80) + printf("(SYNC Mode)\n"); else - printf("(ASYNC Mode) \n"); + printf("(ASYNC Mode)\n"); + return 0; } diff --git a/arch/arm/include/asm/arch-s3c64xx/clock.h b/arch/arm/include/asm/arch-s3c64xx/clock.h new file mode 100644 index 0000000..9e3660c --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/clock.h @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2012 + * Hongbo Zhong bocui107@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H_ +#define __ASM_ARM_ARCH_CLOCK_H_ + +#define APLL_LOCK_OFFSET 0x00 +#define MPLL_LOCK_OFFSET 0x04 +#define EPLL_LOCK_OFFSET 0x08 +#define APLL_CON_OFFSET 0x0C +#define MPLL_CON_OFFSET 0x10 +#define EPLL_CON0_OFFSET 0x14 +#define EPLL_CON1_OFFSET 0x18 +#define CLK_SRC_OFFSET 0x1C +#define CLK_DIV0_OFFSET 0x20 +#define CLK_DIV1_OFFSET 0x24 +#define CLK_DIV2_OFFSET 0x28 +#define OTHERS_OFFSET 0x900 +#define RST_STAT_OFFSET 0x904 +#define WAKEUP_STAT_OFFSET 0x908 +#define INF_REG0_OFFSET 0xA00 + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_S3C6400) +struct s3c64xx_clock { + unsigned int apll_lock; + unsigned int mpll_lock; + unsigned int epll_lock; + unsigned int apll_con; + unsigned int mpll_con; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int clk_src; + unsigned int clk_div0; + unsigned int clk_div1; + unsigned int clk_div2; + unsigned int clk_out; + unsigned int hclk_gate; + unsigned int pclk_gate; + unsigned int sclk_gate; + unsigned char res1[0xc4]; + unsigned int ahb_con0; + unsigned int ahb_con1; + unsigned int ahb_con2; + unsigned char res2[0x04]; + unsigned int sdma_sel; + unsigned int sw_rst; + unsigned int sys_id; + unsigned char res3[0x4]; + unsigned int mem_sys_cfg; + unsigned int qos_override0; + unsigned int qos_override1; + unsigned int mem_cfg_stat; + unsigned char res4[0x6d4]; + unsigned int pwr_cfg; + unsigned int eint_mask; + unsigned char res5[0x4]; + unsigned int normal_cfg; + unsigned int stop_cfg; + unsigned int sleep_cfg; + unsigned char res6[0x4]; + unsigned int osc_freq; + unsigned int osc_stable; + unsigned int pwr_stable; + unsigned char res7[0x4]; + unsigned int mtc_stable; + unsigned char res8[0xcc]; + unsigned int others; + unsigned int rst_stat; + unsigned int wakeup_stat; + unsigned int blk_pwr_stat; + unsigned int inf_reg0; + unsigned int inf_reg1; + unsigned int inf_reg2; + unsigned int inf_reg3; + unsigned int inf_reg4; + unsigned int inf_reg5; + unsigned int inf_reg6; + unsigned int inf_reg7; +}; + +#else +struct s3c64xx_clock { + unsigned int apll_lock; + unsigned int mpll_lock; + unsigned int epll_lock; + unsigned int apll_con; + unsigned int mpll_con; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int clk_src; + unsigned int clk_div0; + unsigned int clk_div1; + unsigned int clk_div2; + unsigned int clk_out; + unsigned int hclk_gate; + unsigned int pclk_gate; + unsigned int sclk_gate; + unsigned int mem0_clk_gate; + unsigned char res1[0xc0]; + unsigned int ahb_con0; + unsigned int ahb_con1; + unsigned int ahb_con2; + unsigned int clk_src2; + unsigned int sdma_sel; + unsigned char sw_rst; + unsigned int sys_id; + unsigned char res3[0x4]; + unsigned int mem_sys_cfg; + unsigned char res4[0x4]; + unsigned int qos_override1; + unsigned int mem_cfg_stat; + unsigned char res5[0x6d4]; + unsigned int pwr_cfg; + unsigned int eint_mask; + unsigned char res6[0x4]; + unsigned int normal_cfg; + unsigned int stop_cfg; + unsigned int sleep_cfg; + unsigned int stop_mem_cfg; + unsigned int osc_freq; + unsigned int osc_stable; + unsigned int pwr_stable; + unsigned char res7[0x4]; + unsigned int mtc_stable; + unsigned char res8[0x4]; + unsigned int misc_con; + unsigned char res9[0xc8]; + unsigned int others; + unsigned int rst_stat; + unsigned int wakeup_stat; + unsigned int blk_pwr_stat; + unsigned int inf_reg0; + unsigned int inf_reg1; + unsigned int inf_reg2; + unsigned int inf_reg3; + unsigned int inf_reg4; + unsigned int inf_reg5; + unsigned int inf_reg6; + unsigned int inf_reg7; +}; +#endif /* CONFIG_S3C6400 */ +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index d2ee9d2..b1537c1 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -42,168 +42,6 @@

#define ELFIN_CLOCK_POWER_BASE 0x7e00f000

-/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - - /* * GPIO */ @@ -583,58 +421,6 @@ */ #define ELFIN_TIMER_BASE 0x7F006000

-#if defined(CONFIG_CLK_400_100_50) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_533_133_66) -#define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_667_133_66) -#define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#endif - -#define STARTUP_PCLKDIV 3 -#define STARTUP_HCLKX2DIV 1 -#define STARTUP_HCLKDIV 1 -#define STARTUP_MPLLDIV 1 -#define STARTUP_APLLDIV 0 - -#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ - (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) -#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) - -#if defined(CONFIG_SYNC_MODE) -#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#else -#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_AMDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#endif - - /*----------------------------------------------------------------------- * Physical Memory Map */ @@ -719,6 +505,11 @@ static inline unsigned long s3c64xx_get_base_sromc(void) { return ELFIN_SROM_BASE; } + +static inline unsigned long s3c64xx_get_base_clock(void) +{ + return ELFIN_CLOCK_POWER_BASE; +} #endif

#endif /*__S3C6400_H__*/ diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 93172e7..dbf12ef 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -35,8 +35,11 @@ #include <version.h>

#include <asm/arch/nand.h> +#include <asm/arch/clock.h> #include <asm/arch/s3c6400.h>

+#include "setup.h" + _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE

diff --git a/board/samsung/smdk6400/setup.h b/board/samsung/smdk6400/setup.h new file mode 100644 index 0000000..91b1c48 --- /dev/null +++ b/board/samsung/smdk6400/setup.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SMDK6400_SETUP_H__ +#define __SMDK6400_SETUP_H__ + +#define STARTUP_AMDIV 533 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 + +#define STARTUP_PCLKDIV 3 +#define STARTUP_HCLKX2DIV 1 +#define STARTUP_HCLKDIV 1 +#define STARTUP_MPLLDIV 1 +#define STARTUP_APLLDIV 0 + +#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ + (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) + +#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | (STARTUP_PDIV << 8) | \ + STARTUP_SDIV) + +#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | (STARTUP_PDIV << 8) | \ + STARTUP_SDIV) + +#endif diff --git a/drivers/usb/host/s3c64xx-hcd.c b/drivers/usb/host/s3c64xx-hcd.c index cd295da..74b5951 100644 --- a/drivers/usb/host/s3c64xx-hcd.c +++ b/drivers/usb/host/s3c64xx-hcd.c @@ -25,21 +25,45 @@ */

#include <common.h> +#include <asm/io.h> #include <asm/arch/s3c6400.h> +#include <asm/arch/clock.h>

int usb_cpu_init(void) { - OTHERS_REG |= 0x10000; + unsigned int val; + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); + + val = readl(&clk->others); + val |= 0x10000; + writel(val, &clk->others); + return 0; }

int usb_cpu_stop(void) { - OTHERS_REG &= ~0x10000; + unsigned int val; + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); + + val = readl(&clk->others); + val &= ~0x10000; + writel(val, &clk->others); + return 0; }

void usb_cpu_init_fail(void) { - OTHERS_REG &= ~0x10000; + unsigned int val; + struct s3c64xx_clock *clk = + (struct s3c64xx_clock *)s3c64xx_get_base_clock(); + + val = readl(&clk->others); + val &= ~0x10000; + writel(val, &clk->others); + + return 0; }

From: Zhong Hongbo bocui107@gmail.com

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - Replace the magic numbers with variable name. - Use C language to implement memory initialization. Change for V2: - None. --- arch/arm/include/asm/arch-s3c64xx/dmc.h | 62 +++++++++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 178 +-------------------------- board/samsung/smdk6400/Makefile | 3 +- board/samsung/smdk6400/dmc_init.c | 110 +++++++++++++++++ board/samsung/smdk6400/lowlevel_init.S | 2 +- board/samsung/smdk6400/mem_init.S | 135 -------------------- board/samsung/smdk6400/setup.h | 85 +++++++++++++ 7 files changed, 265 insertions(+), 310 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/dmc.h create mode 100644 board/samsung/smdk6400/dmc_init.c delete mode 100644 board/samsung/smdk6400/mem_init.S

diff --git a/arch/arm/include/asm/arch-s3c64xx/dmc.h b/arch/arm/include/asm/arch-s3c64xx/dmc.h new file mode 100644 index 0000000..758e750 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/dmc.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef __ASM_ARCH_DMC_H__ +#define __ASM_ARCH_DMC_H__ + +#ifndef __ASSEMBLY__ + +struct s3c64xx_dmc { + unsigned int memstat; + unsigned int memcmd; + unsigned int directcmd; + unsigned int memcfg; + unsigned int refresh; + unsigned int caslat; + unsigned int t_dqss; + unsigned int t_mrd; + unsigned int t_ras; + unsigned int t_rc; + unsigned int t_rcd; + unsigned int t_rfc; + unsigned int t_rp; + unsigned int t_rrd; + unsigned int t_wr; + unsigned int t_wtr; + unsigned int t_xp; + unsigned int t_xsr; + unsigned int t_esr; + unsigned int memcfg2; +#if defined(CONFIG_S3C6410) + unsigned int memcfg3; + unsigned char res1[0xac]; +#else + unsigned char res1[0xb0]; +#endif + unsigned int id_0_cfg[16]; + unsigned char res2[0xc0]; + unsigned int chip_0_cfg; + unsigned int chip_1_cfg; + unsigned char res3[0xf8]; + unsigned int user_status; + unsigned int user_config; +}; +#endif +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index 1da327a..45a8918 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -41,191 +41,18 @@ #include <asm/hardware.h>

#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* - * GPIO - */ #define ELFIN_GPIO_BASE 0x7f008000 - -/* - * Bus Matrix - */ #define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 - -/* - * Memory controller - */ #define ELFIN_SROM_BASE 0x70000000 - -/* - * SDRAM Controller - */ #define ELFIN_DMC0_BASE 0x7e000000 #define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ #define ELFIN_NAND_BASE 0x70200000 - -/* - * Interrupt - */ #define ELFIN_VIC0_BASE_ADDR 0x71200000 #define ELFIN_VIC1_BASE_ADDR 0x71300000 - -/* - * Watchdog timer - */ #define ELFIN_WATCHDOG_BASE 0x7E004000 - -/* - * UART - */ #define ELFIN_UART_BASE 0x7F005000 - -/* - * PWM timer - */ #define ELFIN_TIMER_BASE 0x7F006000

-/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - #ifndef __ASSEMBLY__

static inline unsigned long s3c64xx_get_base_uart(void) @@ -252,6 +79,11 @@ static inline unsigned long s3c64xx_get_base_clock(void) { return ELFIN_CLOCK_POWER_BASE; } + +static inline unsigned long s3c64xx_get_base_dmc1(void) +{ + return ELFIN_DMC1_BASE; +} #endif

#endif /*__S3C6400_H__*/ diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile index f7fa667..e21a8c1 100644 --- a/board/samsung/smdk6400/Makefile +++ b/board/samsung/smdk6400/Makefile @@ -31,8 +31,9 @@ LIB = $(obj)lib$(BOARD).o ifndef CONFIG_SPL_BUILD COBJS-y := smdk6400.o endif +COBJS-y += dmc_init.o

-SOBJS := lowlevel_init.o mem_init.o +SOBJS := lowlevel_init.o

ifdef CONFIG_SPL_BUILD COBJS-y += smdk6400_nand_spl.o diff --git a/board/samsung/smdk6400/dmc_init.c b/board/samsung/smdk6400/dmc_init.c new file mode 100644 index 0000000..776536c --- /dev/null +++ b/board/samsung/smdk6400/dmc_init.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/dmc.h> +#include <asm/arch/s3c6400.h> +#include "setup.h" + +void memory_timing_parameter(struct s3c64xx_dmc *dmc) +{ + + writel(DMC_DDR_REFRESH_PRD, &dmc->refresh); + + writel(DMC_DDR_CAS_LATENCY, &dmc->caslat); + + writel(DMC_DDR_t_DQSS, &dmc->t_dqss); + + writel(DMC_DDR_t_MRD, &dmc->t_mrd); + + writel(DMC_DDR_t_RAS, &dmc->t_ras); + + writel(DMC_DDR_t_RC, &dmc->t_rc); + + writel((DMC_DDR_t_RFC | DMC_DDR_schedule_RFC), &dmc->t_rfc); + + writel((DMC_DDR_t_RP | DMC_DDR_schedule_RP), &dmc->t_rp); + + writel(DMC_DDR_t_RRD, &dmc->t_rrd); + + writel(DMC_DDR_t_WR, &dmc->t_wr); + + writel(DMC_DDR_t_WTR, &dmc->t_wtr); + + writel(DMC_DDR_t_XP, &dmc->t_xp); + + writel(DMC_DDR_t_XSR, &dmc->t_xsr); + + writel(DMC_DDR_t_ESR, &dmc->t_esr); +} + +void memory_init_sequence(struct s3c64xx_dmc *dmc) +{ + /* DMC0 DDR Chip 0 configuration direct command reg */ + writel(DMC_NOP0, &dmc->directcmd); + + /* Precharge All */ + writel(DMC_PA0, &dmc->directcmd); + + /* Auto Refresh 2 time */ + writel(DMC_AR0, &dmc->directcmd); + writel(DMC_AR0, &dmc->directcmd); + + /* MRS */ + writel(DMC_mDDR_EMR0, &dmc->directcmd); + + /* Mode Reg */ + writel(DMC_mDDR_MR0, &dmc->directcmd); +} + +void mem_ctrl_init(void) +{ + struct s3c64xx_dmc *dmc = (struct s3c64xx_dmc *)s3c64xx_get_base_dmc1(); + unsigned long val; + + /* Change the DRAM controller to 'Config' state */ + val = readl(&dmc->memcmd); + val &= ~0x7; + val |= 0x4; + writel(val, &dmc->memcmd); + + memory_timing_parameter(dmc); + + writel(DMC1_MEM_CFG, &dmc->memcfg); + writel(DMC1_MEM_CFG2, &dmc->memcfg2); + + writel(DMC1_CHIP0_CFG, &dmc->chip_0_cfg); + writel(DMC_DDR_32_CFG, &dmc->user_config); + + memory_init_sequence(dmc); + + /* Enable DMC1 */ + writel(0x0, &dmc->memcmd); + + /* Check memory statute: 0x1 means 'Ready' */ + do { + val = readl(&dmc->memstat); + val &= 0x3; + } while (val != 0x1); +} diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 57989bc..e142217 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -103,7 +103,7 @@ lowlevel_init: mov r1, #S3C64XX_MEM_SYS_CFG_NAND str r1, [r0]

- bl mem_ctrl_asm_init + bl mem_ctrl_init #endif

#ifndef CONFIG_SPL_BUILD diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S deleted file mode 100644 index df88cba..0000000 --- a/board/samsung/smdk6400/mem_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * Copyright (C) 2008 - * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/s3c6400.h> - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - /* DMC1 base address 0x7e001000 */ - ldr r0, =ELFIN_DMC1_BASE - - ldr r1, =0x4 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - - ldr r1, =DMC_DDR_REFRESH_PRD - str r1, [r0, #INDEX_DMC_REFRESH_PRD] - - ldr r1, =DMC_DDR_CAS_LATENCY - str r1, [r0, #INDEX_DMC_CAS_LATENCY] - - ldr r1, =DMC_DDR_t_DQSS - str r1, [r0, #INDEX_DMC_T_DQSS] - - ldr r1, =DMC_DDR_t_MRD - str r1, [r0, #INDEX_DMC_T_MRD] - - ldr r1, =DMC_DDR_t_RAS - str r1, [r0, #INDEX_DMC_T_RAS] - - ldr r1, =DMC_DDR_t_RC - str r1, [r0, #INDEX_DMC_T_RC] - - ldr r1, =DMC_DDR_t_RCD - ldr r2, =DMC_DDR_schedule_RCD - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RCD] - - ldr r1, =DMC_DDR_t_RFC - ldr r2, =DMC_DDR_schedule_RFC - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RFC] - - ldr r1, =DMC_DDR_t_RP - ldr r2, =DMC_DDR_schedule_RP - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RP] - - ldr r1, =DMC_DDR_t_RRD - str r1, [r0, #INDEX_DMC_T_RRD] - - ldr r1, =DMC_DDR_t_WR - str r1, [r0, #INDEX_DMC_T_WR] - - ldr r1, =DMC_DDR_t_WTR - str r1, [r0, #INDEX_DMC_T_WTR] - - ldr r1, =DMC_DDR_t_XP - str r1, [r0, #INDEX_DMC_T_XP] - - ldr r1, =DMC_DDR_t_XSR - str r1, [r0, #INDEX_DMC_T_XSR] - - ldr r1, =DMC_DDR_t_ESR - str r1, [r0, #INDEX_DMC_T_ESR] - - ldr r1, =DMC1_MEM_CFG - str r1, [r0, #INDEX_DMC_MEMORY_CFG] - - ldr r1, =DMC1_MEM_CFG2 - str r1, [r0, #INDEX_DMC_MEMORY_CFG2] - - ldr r1, =DMC1_CHIP0_CFG - str r1, [r0, #INDEX_DMC_CHIP_0_CFG] - - ldr r1, =DMC_DDR_32_CFG - str r1, [r0, #INDEX_DMC_USER_CONFIG] - - /* DMC0 DDR Chip 0 configuration direct command reg */ - ldr r1, =DMC_NOP0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Precharge All */ - ldr r1, =DMC_PA0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Auto Refresh 2 time */ - ldr r1, =DMC_AR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* MRS */ - ldr r1, =DMC_mDDR_EMR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Mode Reg */ - ldr r1, =DMC_mDDR_MR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Enable DMC1 */ - mov r1, #0x0 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - -check_dmc1_ready: - ldr r1, [r0, #INDEX_DMC_MEMC_STATUS] - mov r2, #0x3 - and r1, r1, r2 - cmp r1, #0x1 - bne check_dmc1_ready - nop - - mov pc, lr - - .ltorg diff --git a/board/samsung/smdk6400/setup.h b/board/samsung/smdk6400/setup.h index 5e97b27..63a4a8d 100644 --- a/board/samsung/smdk6400/setup.h +++ b/board/samsung/smdk6400/setup.h @@ -49,4 +49,89 @@

#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ (STARTUP_HCLKDIV + 1)) + +#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 + +/* + * Memory Chip direct command + */ +#define DMC_NOP0 0x0c0000 +#define DMC_NOP1 0x1c0000 +#define DMC_PA0 0x000000 /* Precharge all */ +#define DMC_PA1 0x100000 +#define DMC_AR0 0x040000 /* Autorefresh */ +#define DMC_AR1 0x140000 +#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ +#define DMC_SDR_MR1 0x180032 +#define DMC_DDR_MR0 0x080162 +#define DMC_DDR_MR1 0x180162 +#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ +#define DMC_mDDR_MR1 0x180032 +#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ +#define DMC_mSDR_EMR1 0x1a0000 +#define DMC_DDR_EMR0 0x090000 +#define DMC_DDR_EMR1 0x190000 +#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ +#define DMC_mDDR_EMR1 0x1a0000 + +/* + * Physical Memory Map + */ +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ +#define DMC1_MEM_CFG2 0xB45 +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ + +/* Memory Parameters */ +/* DDR Parameters */ +#define DDR_tREFRESH 7800 /* ns */ +#define DDR_tRAS 45 /* ns (min: 45ns)*/ +#define DDR_tRC 68 /* ns (min: 67.5ns)*/ +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ +#define DDR_tRFC 80 /* ns (min: 80ns)*/ +#define DDR_tRP 23 /* ns (min: 22.5ns)*/ +#define DDR_tRRD 15 /* ns (min: 15ns)*/ +#define DDR_tWR 15 /* ns (min: 15ns)*/ +#define DDR_tXSR 120 /* ns (min: 120ns)*/ +#define DDR_CASL 3 /* CAS Latency 3 */ + +/* + * mDDR memory configuration + */ +#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) + +#define DMC_DDR_BA_EMRS 2 +#define DMC_DDR_MEM_CASLAT 3 +#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) +#define DMC_DDR_t_DQSS 1 +#define DMC_DDR_t_MRD 2 +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +#define DMC_DDR_t_DQSS 1 +#define DMC_DDR_t_MRD 2 +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +#define DMC_DDR_t_XP 2 +#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) +#define DMC_DDR_t_ESR DMC_DDR_t_XSR +#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) +#define DMC_DDR_USER_CONFIG 1 #endif

From: Zhong Hongbo bocui107@gmail.com

Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V3: - None. Change for V2: - None. --- include/configs/smdk6400.h | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index fa5b1c5..2b49647 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -108,9 +108,6 @@ #define CONFIG_CMD_LOADB #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND -#if defined(CONFIG_BOOT_ONENAND) -#define CONFIG_CMD_ONENAND -#endif #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT @@ -266,13 +263,6 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63}

-/* None of these are currently implemented. Left from the original Samsung - * version for reference -#define CONFIG_BOOT_NOR -#define CONFIG_BOOT_MOVINAND -#define CONFIG_BOOT_ONENAND -*/ - #define CONFIG_SPL #define CONFIG_SPL_NAND #define CONFIG_SPL_NAND_SIMPLE @@ -283,11 +273,6 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_NAND_S3C64XX -/* Unimplemented or unsupported. See comment above. -#define CONFIG_ONENAND -#define CONFIG_MOVINAND -*/ - /* Settings as above boot configuration */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_BOOTARGS "console=ttySAC,115200"