[U-Boot] [PATCH 0/8] EXYNOS5: Enable I2C support
This patch set enables I2C support for EXYNOS5. This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5. Multichannel support has been added to the s3c24x0 I2C driver. s3c24x0_i2c struct has been moved to a common place as it can used by different SOC's.
Rajeshwari Shinde (8): EXYNOS: CLK: Add i2c clock EXYNOS: Add I2C base address. EXYNOS: PINMUX: Add pinmux support for I2C I2C: Move struct s3c24x0_i2c to a common place. I2C: S3C24X0: Add offset to calculate next i2c channel base address I2C: Modify the I2C driver for EXYNOS5 I2C: Add support for Multi channel CONFIG: SMDK5250: I2C: Enable I2C
This patchset depends on the following patch: "[U-Boot] [PATCH 1/2] exynos5: pinmux: Added default pinumx settings"
arch/arm/cpu/armv7/exynos/clock.c | 33 ++++ arch/arm/cpu/armv7/exynos/pinmux.c | 32 +++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/cpu.h | 3 + arch/arm/include/asm/arch-exynos/pinmux.h | 8 + arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 - drivers/i2c/s3c24x0_i2c.c | 277 ++++++++++++++++++++------- drivers/i2c/s3c24x0_i2c.h | 46 +++++ include/configs/smdk5250.h | 8 + 9 files changed, 336 insertions(+), 82 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..3b86b0c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); }
+/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = ((readl(&clk->div_top1)) >> 24); + ratio &= (0x7); + aclk_66_pre = sclk/(ratio+1); + ratio = readl(&clk->div_top0); + ratio &= (0x7); + aclk_66 = aclk_66_pre/(ratio+1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); }
+unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..72dc655 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -30,6 +30,7 @@
unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);
Hi,
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Just a few nits, otherwise:
Acked-by: Simon Glass sjg@chromium.org
arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..3b86b0c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); }
+/*
- I2C
- exynos5: obtaining the I2C clock
- */
+static unsigned long exynos5_get_i2c_clk(void) +{
struct exynos5_clock *clk =(struct exynos5_clock *)samsung_get_base_clock();unsigned long aclk_66, aclk_66_pre, sclk;unsigned int ratio;sclk = get_pll_clk(MPLL);ratio = ((readl(&clk->div_top1)) >> 24);
Remove extra brackets around this
ratio &= (0x7);aclk_66_pre = sclk/(ratio+1);ratio = readl(&clk->div_top0);ratio &= (0x7);aclk_66 = aclk_66_pre/(ratio+1);return aclk_66;+}
unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); }
+unsigned long get_i2c_clk(void) +{
if (cpu_is_exynos5()) {return exynos5_get_i2c_clk();} else {debug("I2C clock is not set for this CPU\n");return 0;
I think the return 0 needs a tab
}+}
unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..72dc655 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -30,6 +30,7 @@
unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); -- 1.7.4.4
This patch adds the base address for I2C.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- arch/arm/include/asm/arch-exynos/cpu.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..175fd12 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -47,6 +47,7 @@ #define EXYNOS4_SROMC_BASE 0x12570000 #define EXYNOS4_USBPHY_BASE 0x125B0000 #define EXYNOS4_UART_BASE 0x13800000 +#define EXYNOS4_I2C_BASE 0x13860000 #define EXYNOS4_ADC_BASE 0x13910000 #define EXYNOS4_PWMTIMER_BASE 0x139D0000 #define EXYNOS4_MODEM_BASE 0x13A00000 @@ -73,6 +74,7 @@ #define EXYNOS5_USBOTG_BASE 0x12480000 #define EXYNOS5_USBPHY_BASE 0x12480000 #define EXYNOS5_UART_BASE 0x12C00000 +#define EXYNOS5_I2C_BASE 0x12C60000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_GPIO_PART2_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 @@ -132,6 +134,7 @@ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) +SAMSUNG_BASE(i2c, I2C_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This patch adds the base address for I2C.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
arch/arm/include/asm/arch-exynos/cpu.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..175fd12 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -47,6 +47,7 @@ #define EXYNOS4_SROMC_BASE 0x12570000 #define EXYNOS4_USBPHY_BASE 0x125B0000 #define EXYNOS4_UART_BASE 0x13800000 +#define EXYNOS4_I2C_BASE 0x13860000 #define EXYNOS4_ADC_BASE 0x13910000 #define EXYNOS4_PWMTIMER_BASE 0x139D0000 #define EXYNOS4_MODEM_BASE 0x13A00000 @@ -73,6 +74,7 @@ #define EXYNOS5_USBOTG_BASE 0x12480000 #define EXYNOS5_USBPHY_BASE 0x12480000 #define EXYNOS5_UART_BASE 0x12C00000 +#define EXYNOS5_I2C_BASE 0x12C60000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_GPIO_PART2_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 @@ -132,6 +134,7 @@ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) +SAMSUNG_BASE(i2c, I2C_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -- 1.7.4.4
This patch adds pinmux code for I2C.
Signed-off-by: Leela Krishna Amudala l.krishna@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- This patch depends on the following patch: "[U-Boot] [PATCH 1/2] exynos5: pinmux: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 32 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/pinmux.h | 8 +++++++ 2 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 11f4b71..103bcbb 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -170,6 +170,38 @@ int exynos5_pinmux_config(int peripheral, int flags) s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); } break; + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h index 306f521..b3b7f80 100644 --- a/arch/arm/include/asm/arch-exynos/pinmux.h +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This patch adds pinmux code for I2C.
Signed-off-by: Leela Krishna Amudala l.krishna@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
This patch depends on the following patch: "[U-Boot] [PATCH 1/2] exynos5: pinmux: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 32 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/pinmux.h | 8 +++++++ 2 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 11f4b71..103bcbb 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -170,6 +170,38 @@ int exynos5_pinmux_config(int peripheral, int flags) s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); } break;
case PERIPH_ID_I2C0:s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));break;case PERIPH_ID_I2C1:s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));break;case PERIPH_ID_I2C2:s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));break;case PERIPH_ID_I2C3:s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));break;case PERIPH_ID_I2C4:s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));break;case PERIPH_ID_I2C5:s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));break;case PERIPH_ID_I2C6:s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));break;case PERIPH_ID_I2C7:s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1;diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h index 306f521..b3b7f80 100644 --- a/arch/arm/include/asm/arch-exynos/pinmux.h +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -30,6 +30,14 @@
*/ enum periph_id {
PERIPH_ID_I2C0,PERIPH_ID_I2C1,PERIPH_ID_I2C2,PERIPH_ID_I2C3,PERIPH_ID_I2C4,PERIPH_ID_I2C5,PERIPH_ID_I2C6,PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,-- 1.7.4.4
struct s3c24x0_i2c is being moved to common local header file so that the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 -------- drivers/i2c/s3c24x0_i2c.h | 33 +++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 10 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index ca978c9..0f75c31 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -343,16 +343,6 @@ struct s3c24x0_watchdog { u32 wtcnt; };
- -/* IIC (see manual chapter 20) */ -struct s3c24x0_i2c { - u32 iiccon; - u32 iicstat; - u32 iicadd; - u32 iicds; -}; - - /* IIS (see manual chapter 21) */ struct s3c24x0_i2s { #ifdef __BIG_ENDIAN diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h new file mode 100644 index 0000000..2dd4b06 --- /dev/null +++ b/drivers/i2c/s3c24x0_i2c.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _S3C24X0_I2C_H +#define _S3C24X0_I2C_H + +struct s3c24x0_i2c { + u32 iiccon; + u32 iicstat; + u32 iicadd; + u32 iicds; + u32 iiclc; +}; +#endif /* _S3C24X0_I2C_H */
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
struct s3c24x0_i2c is being moved to common local header file so that the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 -------- drivers/i2c/s3c24x0_i2c.h | 33 +++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 10 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index ca978c9..0f75c31 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -343,16 +343,6 @@ struct s3c24x0_watchdog { u32 wtcnt; };
-/* IIC (see manual chapter 20) */ -struct s3c24x0_i2c {
u32 iiccon;u32 iicstat;u32 iicadd;u32 iicds;-};
/* IIS (see manual chapter 21) */ struct s3c24x0_i2s { #ifdef __BIG_ENDIAN diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h new file mode 100644 index 0000000..2dd4b06 --- /dev/null +++ b/drivers/i2c/s3c24x0_i2c.h @@ -0,0 +1,33 @@ +/*
- Copyright (C) 2012 Samsung Electronics
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _S3C24X0_I2C_H +#define _S3C24X0_I2C_H
+struct s3c24x0_i2c {
u32 iiccon;u32 iicstat;u32 iicadd;u32 iicds;u32 iiclc;+};
+#endif /* _S3C24X0_I2C_H */
1.7.4.4
As exynos has more than one i2c channels. This patch adds offset padding for struct s3c24x0_i2c, in order to get the new base address of next i2c channel.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- drivers/i2c/s3c24x0_i2c.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index 2dd4b06..d357a0a 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -29,5 +29,8 @@ struct s3c24x0_i2c { u32 iicadd; u32 iicds; u32 iiclc; +#ifdef CONFIG_EXYNOS5 + uchar res1[0xffec]; +#endif }; #endif /* _S3C24X0_I2C_H */
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
As exynos has more than one i2c channels. This patch adds offset padding for struct s3c24x0_i2c, in order to get the new base address of next i2c channel.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
This is a bit ugly, but I understand the reason for it at present.
Acked-by: Simon Glass sjg@chromium.org
drivers/i2c/s3c24x0_i2c.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index 2dd4b06..d357a0a 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -29,5 +29,8 @@ struct s3c24x0_i2c { u32 iicadd; u32 iicds; u32 iiclc; +#ifdef CONFIG_EXYNOS5
uchar res1[0xffec];+#endif };
#endif /* _S3C24X0_I2C_H */
1.7.4.4
This patch modifies the S3C I2C driver to suppport EXYNOS5. The cahnges made to driver are as follows: - I2C base address is passed as a parameter to many functions to avoid multiple #ifdef - I2C init for Exynos5 is made as different function. - Channel initialisation is moved to a commom funation as it is required by both the i2c_init. - Separate functions written to get I2C base address, peripheral id for pinmux support. - Hardcoding for I2CCON_ACKGEN removed. - Replaced printf with debug. - Checkpatch issues resolved.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- drivers/i2c/s3c24x0_i2c.c | 250 ++++++++++++++++++++++++++++++++------------- drivers/i2c/s3c24x0_i2c.h | 10 ++ 2 files changed, 188 insertions(+), 72 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index ba6f39b..61b54a9 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,10 +27,18 @@ */
#include <common.h> +#ifdef CONFIG_EXYNOS5 +#include <asm/arch/clk.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#else #include <asm/arch/s3c24x0_cpu.h> +#endif
#include <asm/io.h> #include <i2c.h> +#include "s3c24x0_i2c.h"
#ifdef CONFIG_HARD_I2C
@@ -45,6 +53,7 @@
#define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ #define I2C_MODE_MR 0x80 /* Master Receive Mode */ @@ -53,6 +62,41 @@
#define I2C_TIMEOUT 1 /* 1 second */
+#ifdef CONFIG_EXYNOS5 +static unsigned int g_current_bus; /* Stores Current I2C Bus */ + +/* We should not rely on any particular ordering of these IDs */ +static enum periph_id periph_for_dev[] = { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, +}; + +static enum periph_id i2c_get_periph_id(unsigned dev_index) +{ + if (dev_index < ARRAY_SIZE(periph_for_dev)) + return periph_for_dev[dev_index]; + debug("%s: invalid bus %d", __func__, dev_index); + return PERIPH_ID_NONE; +} + +static struct s3c24x0_i2c *get_base_i2c(int bus_idx) +{ + struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)samsung_get_base_i2c(); + return &i2c[bus_idx]; +} + +static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void) +{ + return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE); +} + +#else static int GetI2CSDA(void) { struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); @@ -77,16 +121,17 @@ static void SetI2CSCL(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410 - writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat); + writel((readl(&gpio->gpedat) & ~0x4000) | + (x & 1) << 14, &gpio->gpedat); #endif #ifdef CONFIG_S3C2400 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } +#endif
-static int WaitForXfer(void) +static int WaitForXfer(struct s3c24x0_i2c *i2c) { - struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); int i;
i = I2C_TIMEOUT * 10000; @@ -98,25 +143,84 @@ static int WaitForXfer(void) return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; }
-static int IsACK(void) +static int IsACK(struct s3c24x0_i2c *i2c) { - struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - return !(readl(&i2c->iicstat) & I2CSTAT_NACK); }
-static void ReadWriteByte(void) +static void ReadWriteByte(struct s3c24x0_i2c *i2c) { - struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); }
+static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) +{ + ulong freq, pres = 16, div; +#ifdef CONFIG_EXYNOS5 + freq = get_i2c_clk(); +#else + freq = get_PCLK(); +#endif + /* calculate prescaler and divisor values */ + if ((freq / pres / (16 + 1)) > speed) + /* set prescaler to 512 */ + pres = 512; + + div = 0; + while ((freq / pres / (div + 1)) > speed) + div++; + + /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); + + /* init to SLAVE REVEIVE and set slaveaddr */ + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); + /* program Master Transmit (and implicit STOP) */ + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); +} + +static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned int bus) +{ + int periph_id = i2c_get_periph_id(bus); + + exynos_pinmux_config(periph_id, 0); + + i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +} + +#ifdef CONFIG_EXYNOS5 +void i2c_init(int speed, int slaveadd) +{ + struct s3c24x0_i2c *i2c; + struct exynos5_gpio_part1 *gpio; + int i; + + /* By default i2c channel 0 is the current bus */ + g_current_bus = I2C0; + + i2c = get_base_i2c(g_current_bus); + + i2c_bus_init(i2c, g_current_bus); + + /* wait for some time to give previous transfer a chance to finish */ + i = I2C_TIMEOUT * 1000; + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { + udelay(1000); + i--; + } + + gpio = exynos_get_base_gpio1(); + writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con); + + i2c_ch_init(i2c, speed, slaveadd); +} + +#else void i2c_init(int speed, int slaveadd) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); - ulong freq, pres = 16, div; int i;
/* wait for some time to give previous transfer a chance to finish */ @@ -171,27 +275,9 @@ void i2c_init(int speed, int slaveadd) #endif }
- /* calculate prescaler and divisor values */ - freq = get_PCLK(); - if ((freq / pres / (16 + 1)) > speed) - /* set prescaler to 512 */ - pres = 512; - - div = 0; - while ((freq / pres / (div + 1)) > speed) - div++; - - /* set prescaler, divisor according to freq, also set - * ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); - - /* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->iicstat); - writel(slaveadd, &i2c->iicadd); - /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); - + i2c_ch_init(i2c, speed, slaveadd); } +#endif
/* * cmd_type is 0 for write, 1 for read. @@ -200,19 +286,19 @@ void i2c_init(int speed, int slaveadd) * by the char, we could make it larger if needed. If it is * 0 we skip the address write cycle. */ -static -int i2c_transfer(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], unsigned short data_len) +static int i2c_transfer(struct s3c24x0_i2c *i2c, + unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len) { - struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); int i, result;
if (data == 0 || data_len == 0) { /*Don't support data transfer of no length or to address 0 */ - printf("i2c_transfer: bad call\n"); + debug("i2c_transfer: bad call\n"); return I2C_NOK; }
@@ -226,7 +312,7 @@ int i2c_transfer(unsigned char cmd_type, if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT;
- writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon); + writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); result = I2C_OK;
switch (cmd_type) { @@ -238,16 +324,16 @@ int i2c_transfer(unsigned char cmd_type, &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) { - result = WaitForXfer(); + result = WaitForXfer(i2c); writel(addr[i], &i2c->iicds); - ReadWriteByte(); + ReadWriteByte(i2c); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { - result = WaitForXfer(); + result = WaitForXfer(i2c); writel(data[i], &i2c->iicds); - ReadWriteByte(); + ReadWriteByte(i2c); i++; } } else { @@ -257,19 +343,19 @@ int i2c_transfer(unsigned char cmd_type, &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) { - result = WaitForXfer(); + result = WaitForXfer(i2c); writel(data[i], &i2c->iicds); - ReadWriteByte(); + ReadWriteByte(i2c); i++; } }
if (result == I2C_OK) - result = WaitForXfer(); + result = WaitForXfer(i2c);
/* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); - ReadWriteByte(); + ReadWriteByte(i2c); break;
case I2C_READ: @@ -279,13 +365,13 @@ int i2c_transfer(unsigned char cmd_type, /* send START */ writel(readl(&i2c->iicstat) | I2C_START_STOP, &i2c->iicstat); - result = WaitForXfer(); - if (IsACK()) { + result = WaitForXfer(i2c); + if (IsACK(i2c)) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { writel(addr[i], &i2c->iicds); - ReadWriteByte(); - result = WaitForXfer(); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); i++; }
@@ -293,16 +379,17 @@ int i2c_transfer(unsigned char cmd_type, /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, &i2c->iicstat); - ReadWriteByte(); - result = WaitForXfer(); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) writel(readl(&i2c->iiccon) - & ~0x80, &i2c->iiccon); - ReadWriteByte(); - result = WaitForXfer(); + & ~I2CCON_ACKGEN, + &i2c->iiccon); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); data[i] = readl(&i2c->iicds); i++; } @@ -316,17 +403,18 @@ int i2c_transfer(unsigned char cmd_type, /* send START */ writel(readl(&i2c->iicstat) | I2C_START_STOP, &i2c->iicstat); - result = WaitForXfer(); + result = WaitForXfer(i2c);
- if (IsACK()) { + if (IsACK(i2c)) { i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) writel(readl(&i2c->iiccon) & - ~0x80, &i2c->iiccon); - ReadWriteByte(); - result = WaitForXfer(); + ~I2CCON_ACKGEN, + &i2c->iiccon); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); data[i] = readl(&i2c->iicds); i++; } @@ -337,22 +425,28 @@ int i2c_transfer(unsigned char cmd_type,
/* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); - ReadWriteByte(); + ReadWriteByte(i2c); break;
default: - printf("i2c_transfer: bad call\n"); + debug("i2c_transfer: bad call\n"); result = I2C_NOK; break; }
- return (result); + return result; }
int i2c_probe(uchar chip) { + struct s3c24x0_i2c *i2c; uchar buf[1];
+#ifdef CONFIG_EXYNOS5 + i2c = get_base_i2c(g_current_bus); +#else + i2c = s3c24x0_get_base_i2c(); +#endif buf[0] = 0;
/* @@ -360,16 +454,17 @@ int i2c_probe(uchar chip) * address was <ACK>ed (i.e. there was a chip at that address which * drove the data line low). */ - return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; + return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; }
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { + struct s3c24x0_i2c *i2c; uchar xaddr[4]; int ret;
if (alen > 4) { - printf("I2C read: addr len %d not supported\n", alen); + debug("I2C read: addr len %d not supported\n", alen); return 1; }
@@ -396,10 +491,15 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - if ((ret = - i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len)) != 0) { - printf("I2c read: failed %d\n", ret); +#ifdef CONFIG_EXYNOS5 + i2c = get_base_i2c(g_current_bus); +#else + i2c = s3c24x0_get_base_i2c(); +#endif + ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, + buffer, len); + if (ret != 0) { + debug("I2c read: failed %d\n", ret); return 1; } return 0; @@ -407,10 +507,11 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { + struct s3c24x0_i2c *i2c; uchar xaddr[4];
if (alen > 4) { - printf("I2C write: addr len %d not supported\n", alen); + debug("I2C write: addr len %d not supported\n", alen); return 1; }
@@ -436,8 +537,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif +#ifdef CONFIG_EXYNOS5 + i2c = get_base_i2c(g_current_bus); +#else + i2c = s3c24x0_get_base_i2c(); +#endif return (i2c_transfer - (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, + (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, len) != 0); } #endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index d357a0a..3c144c0 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -23,6 +23,16 @@ #ifndef _S3C24X0_I2C_H #define _S3C24X0_I2C_H
+/* I2C channels exynos5 has 8 i2c channel */ +#define I2C0 0 +#define I2C1 1 +#define I2C2 2 +#define I2C3 3 +#define I2C4 4 +#define I2C5 5 +#define I2C6 6 +#define I2C7 7 + struct s3c24x0_i2c { u32 iiccon; u32 iicstat;
Hi,
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This patch modifies the S3C I2C driver to suppport EXYNOS5. The cahnges made to driver are as follows: - I2C base address is passed as a parameter to many functions to avoid multiple #ifdef - I2C init for Exynos5 is made as different function. - Channel initialisation is moved to a commom funation as it is required by both the i2c_init. - Separate functions written to get I2C base address, peripheral id for pinmux support. - Hardcoding for I2CCON_ACKGEN removed. - Replaced printf with debug. - Checkpatch issues resolved.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Just a nit and a question, but:
Acked-by: Simon Glass sjg@chromium.org
drivers/i2c/s3c24x0_i2c.c | 250 ++++++++++++++++++++++++++++++++------------- drivers/i2c/s3c24x0_i2c.h | 10 ++ 2 files changed, 188 insertions(+), 72 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index ba6f39b..61b54a9 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,10 +27,18 @@ */
#include <common.h> +#ifdef CONFIG_EXYNOS5 +#include <asm/arch/clk.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#else #include <asm/arch/s3c24x0_cpu.h> +#endif
#include <asm/io.h> #include <i2c.h> +#include "s3c24x0_i2c.h"
#ifdef CONFIG_HARD_I2C
@@ -45,6 +53,7 @@
#define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ #define I2C_MODE_MR 0x80 /* Master Receive Mode */ @@ -53,6 +62,41 @@
#define I2C_TIMEOUT 1 /* 1 second */
+#ifdef CONFIG_EXYNOS5 +static unsigned int g_current_bus; /* Stores Current I2C Bus */
+/* We should not rely on any particular ordering of these IDs */ +static enum periph_id periph_for_dev[] = {
PERIPH_ID_I2C0,PERIPH_ID_I2C1,PERIPH_ID_I2C2,PERIPH_ID_I2C3,PERIPH_ID_I2C4,PERIPH_ID_I2C5,PERIPH_ID_I2C6,PERIPH_ID_I2C7,+};
+static enum periph_id i2c_get_periph_id(unsigned dev_index) +{
if (dev_index < ARRAY_SIZE(periph_for_dev))return periph_for_dev[dev_index];debug("%s: invalid bus %d", __func__, dev_index);return PERIPH_ID_NONE;+}
+static struct s3c24x0_i2c *get_base_i2c(int bus_idx) +{
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c*)samsung_get_base_i2c();
blank line here
return &i2c[bus_idx];+}
+static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void) +{
return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE);
OK for now - I assume you will pick up the GPIO patches later and move this there.
+}
+#else static int GetI2CSDA(void) { struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); @@ -77,16 +121,17 @@ static void SetI2CSCL(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14,&gpio->gpedat);
writel((readl(&gpio->gpedat) & ~0x4000) |(x & 1) << 14, &gpio->gpedat);
unrelated change?
#endif #ifdef CONFIG_S3C2400 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } +#endif
-static int WaitForXfer(void) +static int WaitForXfer(struct s3c24x0_i2c *i2c) {
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); int i; i = I2C_TIMEOUT * 10000;@@ -98,25 +143,84 @@ static int WaitForXfer(void) return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; }
-static int IsACK(void) +static int IsACK(struct s3c24x0_i2c *i2c) {
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();return !(readl(&i2c->iicstat) & I2CSTAT_NACK);}
-static void ReadWriteByte(void) +static void ReadWriteByte(struct s3c24x0_i2c *i2c) {
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);}
+static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) +{
ulong freq, pres = 16, div;+#ifdef CONFIG_EXYNOS5
freq = get_i2c_clk();+#else
freq = get_PCLK();+#endif
/* calculate prescaler and divisor values */if ((freq / pres / (16 + 1)) > speed)/* set prescaler to 512 */pres = 512;div = 0;while ((freq / pres / (div + 1)) > speed)div++;/* set prescaler, divisor according to freq, also set ACKGEN, IRQ*/
writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0),&i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */writel(0, &i2c->iicstat);writel(slaveadd, &i2c->iicadd);/* program Master Transmit (and implicit STOP) */writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);+}
+static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned int bus) +{
int periph_id = i2c_get_periph_id(bus);exynos_pinmux_config(periph_id, 0);i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);+}
+#ifdef CONFIG_EXYNOS5 +void i2c_init(int speed, int slaveadd) +{
struct s3c24x0_i2c *i2c;struct exynos5_gpio_part1 *gpio;int i;/* By default i2c channel 0 is the current bus */g_current_bus = I2C0;i2c = get_base_i2c(g_current_bus);i2c_bus_init(i2c, g_current_bus);/* wait for some time to give previous transfer a chance to finish*/
i = I2C_TIMEOUT * 1000;while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {udelay(1000);i--;}gpio = exynos_get_base_gpio1();writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con);i2c_ch_init(i2c, speed, slaveadd);+}
+#else void i2c_init(int speed, int slaveadd) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
ulong freq, pres = 16, div; int i; /* wait for some time to give previous transfer a chance to finish*/ @@ -171,27 +275,9 @@ void i2c_init(int speed, int slaveadd) #endif }
/* calculate prescaler and divisor values */freq = get_PCLK();if ((freq / pres / (16 + 1)) > speed)/* set prescaler to 512 */pres = 512;div = 0;while ((freq / pres / (div + 1)) > speed)div++;/* set prescaler, divisor according to freq, also set* ACKGEN, IRQ */writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0),&i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */writel(0, &i2c->iicstat);writel(slaveadd, &i2c->iicadd);/* program Master Transmit (and implicit STOP) */writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
i2c_ch_init(i2c, speed, slaveadd);} +#endif
/*
- cmd_type is 0 for write, 1 for read.
@@ -200,19 +286,19 @@ void i2c_init(int speed, int slaveadd)
- by the char, we could make it larger if needed. If it is
- 0 we skip the address write cycle.
*/ -static -int i2c_transfer(unsigned char cmd_type,
unsigned char chip,unsigned char addr[],unsigned char addr_len,unsigned char data[], unsigned short data_len)+static int i2c_transfer(struct s3c24x0_i2c *i2c,
unsigned char cmd_type,unsigned char chip,unsigned char addr[],unsigned char addr_len,unsigned char data[],unsigned short data_len){
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); int i, result; if (data == 0 || data_len == 0) { /*Don't support data transfer of no length or to address 0*/
printf("i2c_transfer: bad call\n");
debug("i2c_transfer: bad call\n"); return I2C_NOK; }@@ -226,7 +312,7 @@ int i2c_transfer(unsigned char cmd_type, if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT;
writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); result = I2C_OK; switch (cmd_type) {@@ -238,16 +324,16 @@ int i2c_transfer(unsigned char cmd_type, &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) {
result = WaitForXfer();
result = WaitForXfer(i2c); writel(addr[i], &i2c->iicds);
ReadWriteByte();
ReadWriteByte(i2c); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) {
result = WaitForXfer();
result = WaitForXfer(i2c); writel(data[i], &i2c->iicds);
ReadWriteByte();
ReadWriteByte(i2c); i++; } } else {@@ -257,19 +343,19 @@ int i2c_transfer(unsigned char cmd_type, &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) {
result = WaitForXfer();
result = WaitForXfer(i2c); writel(data[i], &i2c->iicds);
ReadWriteByte();
ReadWriteByte(i2c); i++; } } if (result == I2C_OK)
result = WaitForXfer();
result = WaitForXfer(i2c); /* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte();
ReadWriteByte(i2c); break; case I2C_READ:@@ -279,13 +365,13 @@ int i2c_transfer(unsigned char cmd_type, /* send START */ writel(readl(&i2c->iicstat) | I2C_START_STOP, &i2c->iicstat);
result = WaitForXfer();if (IsACK()) {
result = WaitForXfer(i2c);if (IsACK(i2c)) { i = 0; while ((i < addr_len) && (result ==I2C_OK)) { writel(addr[i], &i2c->iicds);
ReadWriteByte();result = WaitForXfer();
ReadWriteByte(i2c);result = WaitForXfer(i2c); i++; }@@ -293,16 +379,17 @@ int i2c_transfer(unsigned char cmd_type, /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, &i2c->iicstat);
ReadWriteByte();result = WaitForXfer();
ReadWriteByte(i2c);result = WaitForXfer(i2c); i = 0; while ((i < data_len) && (result ==I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) writel(readl(&i2c->iiccon)
& ~0x80,&i2c->iiccon);
ReadWriteByte();result = WaitForXfer();
& ~I2CCON_ACKGEN,&i2c->iiccon);ReadWriteByte(i2c);result = WaitForXfer(i2c); data[i] = readl(&i2c->iicds); i++; }@@ -316,17 +403,18 @@ int i2c_transfer(unsigned char cmd_type, /* send START */ writel(readl(&i2c->iicstat) | I2C_START_STOP, &i2c->iicstat);
result = WaitForXfer();
result = WaitForXfer(i2c);
if (IsACK()) {
if (IsACK(i2c)) { i = 0; while ((i < data_len) && (result ==I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) writel(readl(&i2c->iiccon) &
~0x80,&i2c->iiccon);
ReadWriteByte();result = WaitForXfer();
~I2CCON_ACKGEN,&i2c->iiccon);ReadWriteByte(i2c);result = WaitForXfer(i2c); data[i] = readl(&i2c->iicds); i++; }@@ -337,22 +425,28 @@ int i2c_transfer(unsigned char cmd_type,
/* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte();
ReadWriteByte(i2c); break; default:
printf("i2c_transfer: bad call\n");
debug("i2c_transfer: bad call\n"); result = I2C_NOK; break; }
return (result);
return result;}
int i2c_probe(uchar chip) {
struct s3c24x0_i2c *i2c; uchar buf[1];+#ifdef CONFIG_EXYNOS5
i2c = get_base_i2c(g_current_bus);+#else
i2c = s3c24x0_get_base_i2c();+#endif buf[0] = 0;
/*@@ -360,16 +454,17 @@ int i2c_probe(uchar chip) * address was <ACK>ed (i.e. there was a chip at that address which * drove the data line low). */
return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) !=I2C_OK; }
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) {
struct s3c24x0_i2c *i2c; uchar xaddr[4]; int ret; if (alen > 4) {
printf("I2C read: addr len %d not supported\n", alen);
debug("I2C read: addr len %d not supported\n", alen); return 1; }@@ -396,10 +491,15 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif
if ((ret =i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen,buffer, len)) != 0) {printf("I2c read: failed %d\n", ret);+#ifdef CONFIG_EXYNOS5
i2c = get_base_i2c(g_current_bus);+#else
i2c = s3c24x0_get_base_i2c();+#endif
ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen],alen,
buffer, len);if (ret != 0) {debug("I2c read: failed %d\n", ret); return 1; } return 0;@@ -407,10 +507,11 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) {
struct s3c24x0_i2c *i2c; uchar xaddr[4]; if (alen > 4) {
printf("I2C write: addr len %d not supported\n", alen);
debug("I2C write: addr len %d not supported\n", alen); return 1; }@@ -436,8 +537,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif +#ifdef CONFIG_EXYNOS5
i2c = get_base_i2c(g_current_bus);+#else
i2c = s3c24x0_get_base_i2c();+#endif return (i2c_transfer
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, len) != 0);} #endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index d357a0a..3c144c0 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -23,6 +23,16 @@ #ifndef _S3C24X0_I2C_H #define _S3C24X0_I2C_H
+/* I2C channels exynos5 has 8 i2c channel */ +#define I2C0 0 +#define I2C1 1 +#define I2C2 2 +#define I2C3 3 +#define I2C4 4 +#define I2C5 5 +#define I2C6 6 +#define I2C7 7
Do you actually need these? Perhaps just use '0' in the code for bus 0.
struct s3c24x0_i2c { u32 iiccon; u32 iicstat; -- 1.7.4.4
Regards,
Simon
Hi Simon,
Thank you for comments.
On Fri, Jun 1, 2012 at 6:47 AM, Simon Glass sjg@chromium.org wrote:
Hi,
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This patch modifies the S3C I2C driver to suppport EXYNOS5. The cahnges made to driver are as follows: - I2C base address is passed as a parameter to many functions to avoid multiple #ifdef - I2C init for Exynos5 is made as different function. - Channel initialisation is moved to a commom funation as it is required by both the i2c_init. - Separate functions written to get I2C base address, peripheral id for pinmux support. - Hardcoding for I2CCON_ACKGEN removed. - Replaced printf with debug. - Checkpatch issues resolved.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Just a nit and a question, but:
Acked-by: Simon Glass sjg@chromium.org
drivers/i2c/s3c24x0_i2c.c | 250 ++++++++++++++++++++++++++++++++------------- drivers/i2c/s3c24x0_i2c.h | 10 ++ 2 files changed, 188 insertions(+), 72 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index ba6f39b..61b54a9 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,10 +27,18 @@ */
#include <common.h> +#ifdef CONFIG_EXYNOS5 +#include <asm/arch/clk.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#else #include <asm/arch/s3c24x0_cpu.h> +#endif
#include <asm/io.h> #include <i2c.h> +#include "s3c24x0_i2c.h"
#ifdef CONFIG_HARD_I2C
@@ -45,6 +53,7 @@
#define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ #define I2C_MODE_MR 0x80 /* Master Receive Mode */ @@ -53,6 +62,41 @@
#define I2C_TIMEOUT 1 /* 1 second */
+#ifdef CONFIG_EXYNOS5 +static unsigned int g_current_bus; /* Stores Current I2C Bus */
+/* We should not rely on any particular ordering of these IDs */ +static enum periph_id periph_for_dev[] = {
- PERIPH_ID_I2C0,
- PERIPH_ID_I2C1,
- PERIPH_ID_I2C2,
- PERIPH_ID_I2C3,
- PERIPH_ID_I2C4,
- PERIPH_ID_I2C5,
- PERIPH_ID_I2C6,
- PERIPH_ID_I2C7,
+};
+static enum periph_id i2c_get_periph_id(unsigned dev_index) +{
- if (dev_index < ARRAY_SIZE(periph_for_dev))
- return periph_for_dev[dev_index];
- debug("%s: invalid bus %d", __func__, dev_index);
- return PERIPH_ID_NONE;
+}
+static struct s3c24x0_i2c *get_base_i2c(int bus_idx) +{
- struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c
*)samsung_get_base_i2c();
blank line here
-- will correct this.
- return &i2c[bus_idx];
+}
+static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void) +{
- return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE);
OK for now - I assume you will pick up the GPIO patches later and move this there.
-- yes
+}
+#else static int GetI2CSDA(void) { struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); @@ -77,16 +121,17 @@ static void SetI2CSCL(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14,
&gpio->gpedat);
- writel((readl(&gpio->gpedat) & ~0x4000) |
- (x & 1) << 14, &gpio->gpedat);
unrelated change?
-- it is correction of a checkpatch error
#endif #ifdef CONFIG_S3C2400 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } +#endif
-static int WaitForXfer(void) +static int WaitForXfer(struct s3c24x0_i2c *i2c) {
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
i = I2C_TIMEOUT * 10000; @@ -98,25 +143,84 @@ static int WaitForXfer(void) return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; }
-static int IsACK(void) +static int IsACK(struct s3c24x0_i2c *i2c) {
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
return !(readl(&i2c->iicstat) & I2CSTAT_NACK); }
-static void ReadWriteByte(void) +static void ReadWriteByte(struct s3c24x0_i2c *i2c) {
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); }
+static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) +{
- ulong freq, pres = 16, div;
+#ifdef CONFIG_EXYNOS5
- freq = get_i2c_clk();
+#else
- freq = get_PCLK();
+#endif
- /* calculate prescaler and divisor values */
- if ((freq / pres / (16 + 1)) > speed)
- /* set prescaler to 512 */
- pres = 512;
- div = 0;
- while ((freq / pres / (div + 1)) > speed)
- div++;
- /* set prescaler, divisor according to freq, also set ACKGEN, IRQ
*/
- writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0),
&i2c->iiccon);
- /* init to SLAVE REVEIVE and set slaveaddr */
- writel(0, &i2c->iicstat);
- writel(slaveadd, &i2c->iicadd);
- /* program Master Transmit (and implicit STOP) */
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
+}
+static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned int bus) +{
- int periph_id = i2c_get_periph_id(bus);
- exynos_pinmux_config(periph_id, 0);
- i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+}
+#ifdef CONFIG_EXYNOS5 +void i2c_init(int speed, int slaveadd) +{
- struct s3c24x0_i2c *i2c;
- struct exynos5_gpio_part1 *gpio;
- int i;
- /* By default i2c channel 0 is the current bus */
- g_current_bus = I2C0;
- i2c = get_base_i2c(g_current_bus);
- i2c_bus_init(i2c, g_current_bus);
- /* wait for some time to give previous transfer a chance to finish
*/
- i = I2C_TIMEOUT * 1000;
- while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
- udelay(1000);
- i--;
- }
- gpio = exynos_get_base_gpio1();
- writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con);
- i2c_ch_init(i2c, speed, slaveadd);
+}
+#else void i2c_init(int speed, int slaveadd) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
- ulong freq, pres = 16, div;
int i;
/* wait for some time to give previous transfer a chance to finish */ @@ -171,27 +275,9 @@ void i2c_init(int speed, int slaveadd) #endif }
- /* calculate prescaler and divisor values */
- freq = get_PCLK();
- if ((freq / pres / (16 + 1)) > speed)
- /* set prescaler to 512 */
- pres = 512;
- div = 0;
- while ((freq / pres / (div + 1)) > speed)
- div++;
- /* set prescaler, divisor according to freq, also set
- * ACKGEN, IRQ */
- writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0),
&i2c->iiccon);
- /* init to SLAVE REVEIVE and set slaveaddr */
- writel(0, &i2c->iicstat);
- writel(slaveadd, &i2c->iicadd);
- /* program Master Transmit (and implicit STOP) */
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
- i2c_ch_init(i2c, speed, slaveadd);
} +#endif
/* * cmd_type is 0 for write, 1 for read. @@ -200,19 +286,19 @@ void i2c_init(int speed, int slaveadd) * by the char, we could make it larger if needed. If it is * 0 we skip the address write cycle. */ -static -int i2c_transfer(unsigned char cmd_type,
- unsigned char chip,
- unsigned char addr[],
- unsigned char addr_len,
- unsigned char data[], unsigned short data_len)
+static int i2c_transfer(struct s3c24x0_i2c *i2c,
- unsigned char cmd_type,
- unsigned char chip,
- unsigned char addr[],
- unsigned char addr_len,
- unsigned char data[],
- unsigned short data_len)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i, result;
if (data == 0 || data_len == 0) { /*Don't support data transfer of no length or to address 0 */
- printf("i2c_transfer: bad call\n");
- debug("i2c_transfer: bad call\n");
return I2C_NOK; }
@@ -226,7 +312,7 @@ int i2c_transfer(unsigned char cmd_type, if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT;
- writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
- writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
result = I2C_OK;
switch (cmd_type) { @@ -238,16 +324,16 @@ int i2c_transfer(unsigned char cmd_type, &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) {
- result = WaitForXfer();
- result = WaitForXfer(i2c);
writel(addr[i], &i2c->iicds);
- ReadWriteByte();
- ReadWriteByte(i2c);
i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) {
- result = WaitForXfer();
- result = WaitForXfer(i2c);
writel(data[i], &i2c->iicds);
- ReadWriteByte();
- ReadWriteByte(i2c);
i++; } } else { @@ -257,19 +343,19 @@ int i2c_transfer(unsigned char cmd_type, &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) {
- result = WaitForXfer();
- result = WaitForXfer(i2c);
writel(data[i], &i2c->iicds);
- ReadWriteByte();
- ReadWriteByte(i2c);
i++; } }
if (result == I2C_OK)
- result = WaitForXfer();
- result = WaitForXfer(i2c);
/* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
- ReadWriteByte();
- ReadWriteByte(i2c);
break;
case I2C_READ: @@ -279,13 +365,13 @@ int i2c_transfer(unsigned char cmd_type, /* send START */ writel(readl(&i2c->iicstat) | I2C_START_STOP, &i2c->iicstat);
- result = WaitForXfer();
- if (IsACK()) {
- result = WaitForXfer(i2c);
- if (IsACK(i2c)) {
i = 0; while ((i < addr_len) && (result == I2C_OK)) { writel(addr[i], &i2c->iicds);
- ReadWriteByte();
- result = WaitForXfer();
- ReadWriteByte(i2c);
- result = WaitForXfer(i2c);
i++; }
@@ -293,16 +379,17 @@ int i2c_transfer(unsigned char cmd_type, /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, &i2c->iicstat);
- ReadWriteByte();
- result = WaitForXfer();
- ReadWriteByte(i2c);
- result = WaitForXfer(i2c);
i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) writel(readl(&i2c->iiccon)
- & ~0x80,
&i2c->iiccon);
- ReadWriteByte();
- result = WaitForXfer();
- & ~I2CCON_ACKGEN,
- &i2c->iiccon);
- ReadWriteByte(i2c);
- result = WaitForXfer(i2c);
data[i] = readl(&i2c->iicds); i++; } @@ -316,17 +403,18 @@ int i2c_transfer(unsigned char cmd_type, /* send START */ writel(readl(&i2c->iicstat) | I2C_START_STOP, &i2c->iicstat);
- result = WaitForXfer();
- result = WaitForXfer(i2c);
- if (IsACK()) {
- if (IsACK(i2c)) {
i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) writel(readl(&i2c->iiccon) &
- ~0x80,
&i2c->iiccon);
- ReadWriteByte();
- result = WaitForXfer();
- ~I2CCON_ACKGEN,
- &i2c->iiccon);
- ReadWriteByte(i2c);
- result = WaitForXfer(i2c);
data[i] = readl(&i2c->iicds); i++; } @@ -337,22 +425,28 @@ int i2c_transfer(unsigned char cmd_type,
/* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
- ReadWriteByte();
- ReadWriteByte(i2c);
break;
default:
- printf("i2c_transfer: bad call\n");
- debug("i2c_transfer: bad call\n");
result = I2C_NOK; break; }
- return (result);
- return result;
}
int i2c_probe(uchar chip) {
- struct s3c24x0_i2c *i2c;
uchar buf[1];
+#ifdef CONFIG_EXYNOS5
- i2c = get_base_i2c(g_current_bus);
+#else
- i2c = s3c24x0_get_base_i2c();
+#endif buf[0] = 0;
/* @@ -360,16 +454,17 @@ int i2c_probe(uchar chip) * address was <ACK>ed (i.e. there was a chip at that address which * drove the data line low). */
- return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
- return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) !=
I2C_OK; }
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) {
- struct s3c24x0_i2c *i2c;
uchar xaddr[4]; int ret;
if (alen > 4) {
- printf("I2C read: addr len %d not supported\n", alen);
- debug("I2C read: addr len %d not supported\n", alen);
return 1; }
@@ -396,10 +491,15 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif
- if ((ret =
- i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen,
- buffer, len)) != 0) {
- printf("I2c read: failed %d\n", ret);
+#ifdef CONFIG_EXYNOS5
- i2c = get_base_i2c(g_current_bus);
+#else
- i2c = s3c24x0_get_base_i2c();
+#endif
- ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen],
alen,
- buffer, len);
- if (ret != 0) {
- debug("I2c read: failed %d\n", ret);
return 1; } return 0; @@ -407,10 +507,11 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) {
- struct s3c24x0_i2c *i2c;
uchar xaddr[4];
if (alen > 4) {
- printf("I2C write: addr len %d not supported\n", alen);
- debug("I2C write: addr len %d not supported\n", alen);
return 1; }
@@ -436,8 +537,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif +#ifdef CONFIG_EXYNOS5
- i2c = get_base_i2c(g_current_bus);
+#else
- i2c = s3c24x0_get_base_i2c();
+#endif return (i2c_transfer
- (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
- (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
len) != 0); } #endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index d357a0a..3c144c0 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -23,6 +23,16 @@ #ifndef _S3C24X0_I2C_H #define _S3C24X0_I2C_H
+/* I2C channels exynos5 has 8 i2c channel */ +#define I2C0 0 +#define I2C1 1 +#define I2C2 2 +#define I2C3 3 +#define I2C4 4 +#define I2C5 5 +#define I2C6 6 +#define I2C7 7
Do you actually need these? Perhaps just use '0' in the code for bus 0.
-- You are right will correct this.
struct s3c24x0_i2c { u32 iiccon; u32 iicstat; -- 1.7.4.4
Regards,
Simon
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Regards, Rajeshwari Shinde
This adds multiple i2c channel support for I2C.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- drivers/i2c/s3c24x0_i2c.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 61b54a9..39875cd 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -189,6 +189,33 @@ static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned int bus) i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); }
+/* + * MULTI BUS I2C support + */ + +#ifdef CONFIG_I2C_MULTI_BUS +int i2c_set_bus_num(unsigned int bus) +{ + struct s3c24x0_i2c *i2c; + + if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { + debug("Bad bus: %d\n", bus); + return -1; + } + + g_current_bus = bus; + i2c = get_base_i2c(g_current_bus); + i2c_bus_init(i2c, g_current_bus); + + return 0; +} + +unsigned int i2c_get_bus_num(void) +{ + return g_current_bus; +} +#endif + #ifdef CONFIG_EXYNOS5 void i2c_init(int speed, int slaveadd) {
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This adds multiple i2c channel support for I2C.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
drivers/i2c/s3c24x0_i2c.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 61b54a9..39875cd 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -189,6 +189,33 @@ static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned int bus) i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); }
+/*
- MULTI BUS I2C support
- */
+#ifdef CONFIG_I2C_MULTI_BUS +int i2c_set_bus_num(unsigned int bus) +{
struct s3c24x0_i2c *i2c;if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {debug("Bad bus: %d\n", bus);return -1;}g_current_bus = bus;i2c = get_base_i2c(g_current_bus);i2c_bus_init(i2c, g_current_bus);return 0;+}
+unsigned int i2c_get_bus_num(void) +{
return g_current_bus;+} +#endif
#ifdef CONFIG_EXYNOS5 void i2c_init(int speed, int slaveadd) { -- 1.7.4.4
This enables I2C support on smdk5250.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- include/configs/smdk5250.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 9659f9e..1fca652 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -190,6 +190,14 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ +#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_MAX_I2C_NUM 8 + /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X
Hi,
On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This enables I2C support on smdk5250.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
BTW we have additional patches in our tree which tidy up the i2c_transfer() loop, and introduce fdt support. For later, perhaps.
include/configs/smdk5250.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 9659f9e..1fca652 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -190,6 +190,14 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ +#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_MAX_I2C_NUM 8
/* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X
1.7.4.4
Regards,
Simon
participants (3)
-
Rajeshwari Birje -
Rajeshwari Shinde -
Simon Glass