[PATCH v3 00/20] imx8qxp: siemens board: updates / sync with mainline
Updating the imx8qxp based siemens board. The current state of the siemens imx8qxp board is in an old not really working state.
This series brings mainline back working on the siemens deneb board, the guedi board is dropped as not longer used.
make all runs fine without having all the needed firmware images on board, and so CI @azure.
If you want to have a working image you need to copy the following images to your build directory $BDIR:
ATF : bl31-imx8dx.bin -> $BDIR/bl31.bin AHAB: mx8qxc0-ahab-container.img -> $BDIR/mx8qxc0-ahab-container.img SCFW: deneb-scfw-tcm.bin -> $BDIR/mx8qx-mek-scfw-tcm.bin
and call make flash.bin
There are also updates for ethernet and USB support, but not ready to push upstream currently, hopefully following soon.
Azure build: https://dev.azure.com/hs0298/hs/_build/results?buildId=137&view=results
patchseries needs patch: https://patchwork.ozlabs.org/project/uboot/patch/20241104180203.110395-1-hs@...
series is based on mainline commit: 56accc56b9a ("bios_emulator: fix first argument of pci_{read,write}_config_* function calls")
Ah yes, not to forget, we work at siemens also on a CI setup to have a mainline nightly build and test on hardware. We already have such a CI for internall U-Boot versions up and running, but we do not want again loose sync with mainline.
Changes in v3: - add Reviewed-by tag from Alexander - add comments from Igor fix spelling issues depends on ARCH_IMX8 instead of IMX8 Kconfig symbol - comment from Francesco and Stefan rename Kconfig symbol from WDT_SCU_PMIC to WDT_SIEMENS_PMIC rename scu_pmic_wdt.c to siemens_pmic_wdt.c - use renamed Kconfig symbol CONFIG_WDT_SIEMENS_PMIC
Changes in v2: remove patch "siemens: capricorn: add missing ARCH_MISC_INIT" as we do not need this config option anymore. remove patch "siemens: imx8-capricorn-u-boot.dtsi: add fec2" as fec2 is not used in SPL! - work on comments from Stefan: - rename driver file from scu_wdt.c to scu_pmic_wdt.c - rename Kconfig symbol from CONFIG_WDT_IMX_SCU to CONFIG_WDT_SCU_PMIC - reworked Kconfig help text - add comment that TIMER_FUNC_CTRL_PMIC_WDOG is a siemens specific SCU API extension in their SCFW. - reworked commit message add Reviewed-by from Alexander - add "bootph-all" in A35_0 node to u-boot.dtsi not in dts for the board! - add comment from Walter fix typo: than -> then - add Reviewed-by from Alexander - add comments from Fabio fix typo: silicium -> silicon - add Reviewed-by from Alexander - use renamed Kconfig symbol CONFIG_WDT_SCU_PMIC - add comments rom Fabio and Enrico do not remove DMA for console remove u-boot specific property addition, instead add it in arch/arm/dts/imx8qxp-u-boot.dtsi - add comments from Fabio rename subject line and rework commit message, alse remove unneeded comment in checkboard() - add comment from Fabio add From line, as patch is from Alessandro fix typo in commit description: drace -> draco - remove CONFIG_XPL_BUILD in board_init as board_init is not called from SPL. add From tag reworked the commit message a little bit Add From tag - add Reviewed-by from Alexander
Alessandro Zini (1): siemens: capricorn: add HW version information to boot log
Enrico Leto (6): siemens: capricorn: move to cxg3 reference project with deneb board siemens: capricorn: get ram size from system controller siemens: capricorn: get module name from eeprom siemens: add ddr full memory test siemens: add ddr signal integrity test siemens: capricorn: update maintainers
Heiko Schocher (13): wdt: imx8qxp: add option to control external PMIC wdt via IMX8 SCU net: fec_mxc: fix probing for imx8qxp tools: imx8image: Improve error message imx: imx_cntr_image.sh: prevent warning for missing spl imx8qxp: Fix build when using SPL siemens: imx8qxp-capricorn-u-boot.dtsi: fix boot siemens: capricorn: use DCD_SKIP entry siemens: imximage.cfg: correct comment siemens: imximage.cfg: sync image names siemens: configs/capricorn_cxg3_defconfig: updates siemens: capricorn: sync spl code with 8qxp-mek siemens: imx8-capricorn.dtsi: add wdt device siemens: capricorn: small board updates
arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8-capricorn-cxg3.dts | 129 +++++++ ...u-boot.dtsi => imx8-capricorn-u-boot.dtsi} | 67 ++-- ...qxp-capricorn.dtsi => imx8-capricorn.dtsi} | 109 +----- arch/arm/dts/imx8-deneb.dts | 10 - arch/arm/dts/imx8-giedi.dts | 10 - arch/arm/dts/imx8qxp-u-boot.dtsi | 2 + arch/arm/mach-imx/imx8/Kconfig | 11 +- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- board/siemens/capricorn/Kconfig | 25 +- board/siemens/capricorn/MAINTAINERS | 12 +- board/siemens/capricorn/Makefile | 2 + board/siemens/capricorn/board.c | 70 +++- board/siemens/capricorn/imximage.cfg | 21 +- board/siemens/capricorn/spl.c | 43 +++ board/siemens/capricorn/spl_memory_test.c | 158 ++++++++ board/siemens/capricorn/spl_memory_test.h | 7 + board/siemens/common/Kconfig | 4 + board/siemens/common/board.h | 44 +++ board/siemens/common/ddr_si_test.c | 348 ++++++++++++++++++ board/siemens/draco/board.h | 10 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- ...neb_defconfig => capricorn_cxg3_defconfig} | 20 +- configs/giedi_defconfig | 133 ------- drivers/misc/imx8/scu_api.c | 21 ++ drivers/net/fec_mxc.c | 14 +- drivers/watchdog/Kconfig | 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/siemens_pmic_wdt.c | 59 +++ include/configs/capricorn-common.h | 4 +- include/configs/deneb.h | 16 - include/firmware/imx/sci/rpc.h | 3 + include/firmware/imx/sci/sci.h | 1 + include/netdev.h | 2 +- tools/imx8image.c | 2 +- tools/imx_cntr_image.sh | 4 + 36 files changed, 1001 insertions(+), 375 deletions(-) create mode 100644 arch/arm/dts/imx8-capricorn-cxg3.dts rename arch/arm/dts/{imx8qxp-capricorn-u-boot.dtsi => imx8-capricorn-u-boot.dtsi} (54%) rename arch/arm/dts/{imx8qxp-capricorn.dtsi => imx8-capricorn.dtsi} (64%) delete mode 100644 arch/arm/dts/imx8-deneb.dts delete mode 100644 arch/arm/dts/imx8-giedi.dts create mode 100644 board/siemens/capricorn/spl_memory_test.c create mode 100644 board/siemens/capricorn/spl_memory_test.h create mode 100644 board/siemens/common/board.h create mode 100644 board/siemens/common/ddr_si_test.c rename configs/{deneb_defconfig => capricorn_cxg3_defconfig} (89%) delete mode 100644 configs/giedi_defconfig create mode 100644 drivers/watchdog/siemens_pmic_wdt.c delete mode 100644 include/configs/deneb.h
Driver for a PMIC watchdog timer controlled via Siemens SCU firmware extensions. Only useful on some Siemens i.MX8-based platforms as special SCFW is needed which provides the needed SCU API.
Signed-off-by: Andrej Valek andrej.valek@siemens.com Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
---
Changes in v3: - add Reviewed-by tag from Alexander - add comments from Igor fix spelling issues depends on ARCH_IMX8 instead of IMX8 Kconfig symbol - comment from Francesco and Stefan rename Kconfig symbol from WDT_SCU_PMIC to WDT_SIEMENS_PMIC rename scu_pmic_wdt.c to siemens_pmic_wdt.c
Changes in v2: - work on comments from Stefan: - rename driver file from scu_wdt.c to scu_pmic_wdt.c - rename Kconfig symbol from CONFIG_WDT_IMX_SCU to CONFIG_WDT_SCU_PMIC - reworked Kconfig help text - add comment that TIMER_FUNC_CTRL_PMIC_WDOG is a siemens specific SCU API extension in their SCFW. - reworked commit message
drivers/misc/imx8/scu_api.c | 21 ++++++++++ drivers/watchdog/Kconfig | 7 ++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/siemens_pmic_wdt.c | 59 +++++++++++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 3 ++ include/firmware/imx/sci/sci.h | 1 + 6 files changed, 92 insertions(+) create mode 100644 drivers/watchdog/siemens_pmic_wdt.c
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..edb6923151a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,27 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; }
+int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_PMIC_WDOG; + RPC_U8(&msg, 0U) = (u8)cmd; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", + __func__, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..b39b2546e5c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -351,6 +351,13 @@ config WDT_SBSA In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored.
+config WDT_SIEMENS_PMIC + bool "Enable PMIC Watchdog Timer support for Siemens platforms" + depends on ARCH_IMX8 && WDT + help + Select this to enable the PMIC watchdog driver controlled via + IMX8 SCU API found on Siemens platforms. + config WDT_SL28CPLD bool "sl28cpld watchdog timer support" depends on WDT && SL28CPLD diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..9b6b1a8e8ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o +obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c new file mode 100644 index 00000000000..e7ca00de654 --- /dev/null +++ b/drivers/watchdog/siemens_pmic_wdt.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for a PMIC watchdog timer controlled via Siemens SCU firmware + * extensions. Only useful on some Siemens i.MX8-based platforms as + * special NXP SCFW is needed which provides the needed SCU API. + * + * Copyright (C) 2024 Siemens AG + */ + +#include <dm.h> +#include <wdt.h> +#include <firmware/imx/sci/sci.h> + +/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35 + +static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + /* start external watchdog via Timer API */ + return sc_timer_control_pmic_wdog(-1, CMD_START_WDT); +} + +static int scu_wdt_stop(struct udevice *dev) +{ + /* stop external watchdog via Timer API */ + return sc_timer_control_pmic_wdog(-1, CMD_STOP_WDT); +} + +static int scu_wdt_reset(struct udevice *dev) +{ + return sc_timer_control_pmic_wdog(-1, CMD_PING_WDT); +} + +static int scu_wdt_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + return 0; +} + +static const struct wdt_ops scu_wdt_ops = { + .reset = scu_wdt_reset, + .start = scu_wdt_start, + .stop = scu_wdt_stop, +}; + +static const struct udevice_id scu_wdt_ids[] = { + { .compatible = "siemens,scu-wdt" }, + { } +}; + +U_BOOT_DRIVER(scu_wdt) = { + .name = "scu_wdt", + .id = UCLASS_WDT, + .of_match = scu_wdt_ids, + .probe = scu_wdt_probe, + .ops = &scu_wdt_ops, +}; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..ba5bf9a16fe 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -231,4 +231,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
+/* Siemens specific API extension */ +#define TIMER_FUNC_CTRL_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */ + #endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..b971b62836d 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
/* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd);
/* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
Hi Heiko,
On 21.11.24 06:25, Heiko Schocher wrote:
Driver for a PMIC watchdog timer controlled via Siemens SCU firmware extensions. Only useful on some Siemens i.MX8-based platforms as special SCFW is needed which provides the needed SCU API.
Signed-off-by: Andrej Valek andrej.valek@siemens.com Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
Changes in v3:
- add Reviewed-by tag from Alexander
- add comments from Igor fix spelling issues depends on ARCH_IMX8 instead of IMX8 Kconfig symbol
- comment from Francesco and Stefan rename Kconfig symbol from WDT_SCU_PMIC to WDT_SIEMENS_PMIC rename scu_pmic_wdt.c to siemens_pmic_wdt.c
Changes in v2:
work on comments from Stefan:
- rename driver file from scu_wdt.c to scu_pmic_wdt.c
- rename Kconfig symbol from CONFIG_WDT_IMX_SCU to CONFIG_WDT_SCU_PMIC
- reworked Kconfig help text
- add comment that TIMER_FUNC_CTRL_PMIC_WDOG is a siemens specific SCU API extension in their SCFW.
- reworked commit message
drivers/misc/imx8/scu_api.c | 21 ++++++++++ drivers/watchdog/Kconfig | 7 ++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/siemens_pmic_wdt.c | 59 +++++++++++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 3 ++ include/firmware/imx/sci/sci.h | 1 + 6 files changed, 92 insertions(+) create mode 100644 drivers/watchdog/siemens_pmic_wdt.c
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..edb6923151a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,27 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; }
+int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd)
Is this function also Siemens specific?
+{
- struct udevice *dev = gd->arch.scu_dev;
- struct sc_rpc_msg_s msg;
- int size = sizeof(struct sc_rpc_msg_s);
- int ret;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_PMIC_WDOG;
- RPC_U8(&msg, 0U) = (u8)cmd;
- RPC_SIZE(&msg) = 2U;
- ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
- if (ret)
printf("%s: res:%d\n",__func__, RPC_R8(&msg));
Doesn't this printf statement fit into a single line?
- return ret;
+}
- int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) {
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..b39b2546e5c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -351,6 +351,13 @@ config WDT_SBSA In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored.
+config WDT_SIEMENS_PMIC
- bool "Enable PMIC Watchdog Timer support for Siemens platforms"
- depends on ARCH_IMX8 && WDT
- help
Select this to enable the PMIC watchdog driver controlled viaIMX8 SCU API found on Siemens platforms.- config WDT_SL28CPLD bool "sl28cpld watchdog timer support" depends on WDT && SL28CPLD
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..9b6b1a8e8ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o +obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c new file mode 100644 index 00000000000..e7ca00de654 --- /dev/null +++ b/drivers/watchdog/siemens_pmic_wdt.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Driver for a PMIC watchdog timer controlled via Siemens SCU firmware
- extensions. Only useful on some Siemens i.MX8-based platforms as
- special NXP SCFW is needed which provides the needed SCU API.
- Copyright (C) 2024 Siemens AG
- */
+#include <dm.h> +#include <wdt.h> +#include <firmware/imx/sci/sci.h>
+/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35
+static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{
- /* start external watchdog via Timer API */
- return sc_timer_control_pmic_wdog(-1, CMD_START_WDT);
+}
+static int scu_wdt_stop(struct udevice *dev) +{
- /* stop external watchdog via Timer API */
- return sc_timer_control_pmic_wdog(-1, CMD_STOP_WDT);
+}
+static int scu_wdt_reset(struct udevice *dev) +{
- return sc_timer_control_pmic_wdog(-1, CMD_PING_WDT);
+}
+static int scu_wdt_probe(struct udevice *dev) +{
- debug("%s(dev=%p)\n", __func__, dev);
- return 0;
+}
+static const struct wdt_ops scu_wdt_ops = {
- .reset = scu_wdt_reset,
- .start = scu_wdt_start,
- .stop = scu_wdt_stop,
+};
+static const struct udevice_id scu_wdt_ids[] = {
- { .compatible = "siemens,scu-wdt" },
- { }
+};
+U_BOOT_DRIVER(scu_wdt) = {
- .name = "scu_wdt",
- .id = UCLASS_WDT,
- .of_match = scu_wdt_ids,
- .probe = scu_wdt_probe,
- .ops = &scu_wdt_ops,
+}; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..ba5bf9a16fe 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -231,4 +231,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
+/* Siemens specific API extension */ +#define TIMER_FUNC_CTRL_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */
So if it's Siemens specific, shouldn't this also be reflected in the macro name?
Other than this:
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
- #endif /* SC_RPC_H */
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..b971b62836d 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
/* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd);
/* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
Viele Grüße, Stefan Roese
Hello Stefan,
On 21.11.24 09:12, Stefan Roese wrote:
Hi Heiko,
On 21.11.24 06:25, Heiko Schocher wrote:
Driver for a PMIC watchdog timer controlled via Siemens SCU firmware extensions. Only useful on some Siemens i.MX8-based platforms as special SCFW is needed which provides the needed SCU API.
Signed-off-by: Andrej Valek andrej.valek@siemens.com Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
Changes in v3:
- add Reviewed-by tag from Alexander
- add comments from Igor
fix spelling issues depends on ARCH_IMX8 instead of IMX8 Kconfig symbol
- comment from Francesco and Stefan
rename Kconfig symbol from WDT_SCU_PMIC to WDT_SIEMENS_PMIC rename scu_pmic_wdt.c to siemens_pmic_wdt.c
Changes in v2:
- work on comments from Stefan:
- rename driver file from scu_wdt.c to scu_pmic_wdt.c - rename Kconfig symbol from CONFIG_WDT_IMX_SCU to CONFIG_WDT_SCU_PMIC - reworked Kconfig help text - add comment that TIMER_FUNC_CTRL_PMIC_WDOG is a siemens specific SCU API extension in their SCFW. - reworked commit message
drivers/misc/imx8/scu_api.c | 21 ++++++++++ drivers/watchdog/Kconfig | 7 ++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/siemens_pmic_wdt.c | 59 +++++++++++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 3 ++ include/firmware/imx/sci/sci.h | 1 + 6 files changed, 92 insertions(+) create mode 100644 drivers/watchdog/siemens_pmic_wdt.c
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..edb6923151a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,27 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; } +int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd)
Is this function also Siemens specific?
Yep, renamed it to sc_timer_control_siemens_pmic_wdog()
+{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret;
+ RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_PMIC_WDOG; + RPC_U8(&msg, 0U) = (u8)cmd; + RPC_SIZE(&msg) = 2U;
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", + __func__, RPC_R8(&msg));
Doesn't this printf statement fit into a single line?
Good catch, yes!
+ return ret; +}
int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..b39b2546e5c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -351,6 +351,13 @@ config WDT_SBSA In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. +config WDT_SIEMENS_PMIC + bool "Enable PMIC Watchdog Timer support for Siemens platforms" + depends on ARCH_IMX8 && WDT + help + Select this to enable the PMIC watchdog driver controlled via + IMX8 SCU API found on Siemens platforms.
config WDT_SL28CPLD bool "sl28cpld watchdog timer support" depends on WDT && SL28CPLD diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..9b6b1a8e8ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o +obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c new file mode 100644 index 00000000000..e7ca00de654 --- /dev/null +++ b/drivers/watchdog/siemens_pmic_wdt.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Driver for a PMIC watchdog timer controlled via Siemens SCU firmware
- extensions. Only useful on some Siemens i.MX8-based platforms as
- special NXP SCFW is needed which provides the needed SCU API.
- Copyright (C) 2024 Siemens AG
- */
+#include <dm.h> +#include <wdt.h> +#include <firmware/imx/sci/sci.h>
+/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35
+static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + /* start external watchdog via Timer API */ + return sc_timer_control_pmic_wdog(-1, CMD_START_WDT); +}
+static int scu_wdt_stop(struct udevice *dev) +{ + /* stop external watchdog via Timer API */ + return sc_timer_control_pmic_wdog(-1, CMD_STOP_WDT); +}
+static int scu_wdt_reset(struct udevice *dev) +{ + return sc_timer_control_pmic_wdog(-1, CMD_PING_WDT); +}
+static int scu_wdt_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + return 0; +}
+static const struct wdt_ops scu_wdt_ops = { + .reset = scu_wdt_reset, + .start = scu_wdt_start, + .stop = scu_wdt_stop, +};
+static const struct udevice_id scu_wdt_ids[] = { + { .compatible = "siemens,scu-wdt" }, + { } +};
+U_BOOT_DRIVER(scu_wdt) = { + .name = "scu_wdt", + .id = UCLASS_WDT, + .of_match = scu_wdt_ids, + .probe = scu_wdt_probe, + .ops = &scu_wdt_ops, +}; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..ba5bf9a16fe 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -231,4 +231,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ +/* Siemens specific API extension */ +#define TIMER_FUNC_CTRL_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */
So if it's Siemens specific, shouldn't this also be reflected in the macro name?
Renamed it to TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG
Other than this:
Reviewed-by: Stefan Roese sr@denx.de
Thanks!
bye, Heiko
Thanks, Stefan
#endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..b971b62836d 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); /* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd); /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
Viele Grüße, Stefan Roese
probing on capricorn board (imx8qxp based) brings:
Can't find FEC0 clk rate: -19
Cause is that when probing fec_mxc driver, fec_mii_setspeed() is called which calls fec_get_clk_rate().
fec_mii_setspeed() calls fec_get_clk_rate with NULL pointer for udev and so as in IMX8QXP case CLK_CCF is enabled udev gets searched with:
uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
but we do not have yet a UCLASS_ETH ! as we just probing it!
Prevent this by passing udev to fec_get_clk_rate()
Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
board/boundary/nitrogen6x/nitrogen6x.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- drivers/net/fec_mxc.c | 14 +++++++------- include/netdev.h | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index b85fd806cba..1adee9a461f 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -281,7 +281,7 @@ int board_eth_init(struct bd_info *bis) setup_iomux_enet();
#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); + bus = fec_get_miibus(NULL, base, -1); if (!bus) return -EINVAL; /* scan phy 4,5,6,7 */ diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index e9269ef5353..b543bf8c1fb 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -385,7 +385,7 @@ static int find_ethernet_phy(void) int phy_addr = -ENOENT;
#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(ENET_BASE_ADDR, -1); + bus = fec_get_miibus(NULL, ENET_BASE_ADDR, -1); if (!bus) return -ENOENT;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d6d5cb52fdd..eca681b16d1 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -160,7 +160,7 @@ static int fec_get_clk_rate(void *udev, int idx) } }
-static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -182,7 +182,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret;
- ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(dev, 0); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -581,7 +581,7 @@ static int fecmxc_init(struct udevice *dev) fec_reg_setup(fec);
if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(dev, fec->bus->priv);
/* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -996,7 +996,7 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); }
-struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id) { struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; @@ -1018,7 +1018,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(dev, eth); return bus; }
@@ -1354,10 +1354,10 @@ static int fecmxc_probe(struct udevice *dev) if (!bus) { dm_mii_bus = false; #ifdef CONFIG_FEC_MXC_MDIO_BASE - bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, + bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE, dev_seq(dev)); #else - bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); + bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev)); #endif } if (!bus) { diff --git a/include/netdev.h b/include/netdev.h index 2a06d9a261b..949245ecdec 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -117,7 +117,7 @@ static inline int pci_eth_init(struct bd_info *bis) return num; }
-struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id); +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id);
#ifdef CONFIG_PHYLIB struct phy_device;
Improve error message "header tag mismatched" Add filename to error message to see, which file is wrong.
Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
---
(no changes since v2)
Changes in v2: add Reviewed-by from Alexander
tools/imx8image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/imx8image.c b/tools/imx8image.c index 96ece28bd6c..b22e8b21c47 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -733,7 +733,7 @@ static int get_container_image_start_pos(image_t *image_stack, uint32_t align) fclose(fd);
if (header.tag != IVT_HEADER_TAG_B0) { - fprintf(stderr, "header tag mismatched \n"); + fprintf(stderr, "header tag mismatched file %s\n", img_sp->filename); exit(EXIT_FAILURE); } else { file_off +=
when building U-Boot on imx8qxp and the board port uses SPL, U-boot build shows
WARNING '.../spl/u-boot-spl.bin' not found, resulting binary is not-functional
This is because U-Boot binary is build first and Makefile calls script imx_cntr_image.sh which checks if files exists... but of course as spl is not yet build the file `spl/u-boot-spl.bin` does not exist yet, so prevent this warning.
Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
tools/imx_cntr_image.sh | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh index 972b95ccbee..07acd385631 100755 --- a/tools/imx_cntr_image.sh +++ b/tools/imx_cntr_image.sh @@ -14,6 +14,10 @@ for f in $blobs; do continue fi
+ if [ $f = "spl/u-boot-spl.bin" ]; then + continue + fi + if [ -f $f ]; then continue fi
imx8qxp based boards which use SPL drop error when calling make all: """ Writing image to './flash.bin' Node '/binman/imx-boot/spl': GetData: size 0x0 Node '/binman/imx-boot': GetPaddedDataForEntry: size 0x0 Node '/binman/imx-boot': GetData: 1 entries, total size 0x0 Node '/binman/imx-boot': GetPaddedDataForEntry: size 0x0 Wrote 0x0 bytes Image 'imx-boot' is missing external blobs and is non-functional: spl
/binman/imx-boot/spl (spl.bin): Missing blob
Some images are invalid """
Guard creation of flash.bin with CONFIG_XPL_BUILD option.
Signed-off-by: Heiko Schocher hs@denx.de Fixes: c9713c155127 ("imx8-u-boot: Fix SPL guard option") ---
(no changes since v1)
arch/arm/dts/imx8qxp-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index 62791c34c77..8058caae9ba 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -120,6 +120,7 @@ }; };
+#ifdef CONFIG_XPL_BUILD imx-boot { filename = "flash.bin"; pad-byte = <0x00>; @@ -130,4 +131,5 @@ type = "blob-ext"; }; }; +#endif };
From: Enrico Leto enrico.leto@siemens.com
We have many HW with capricorn i.MX8X boards. The difference in u-boot is at all by the display of the LEDs.
* put upstream a reference project & board for DT and defconfig * use the capricorn prefix outside the board/siemens/capricorn folder
Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8-capricorn-cxg3.dts | 129 +++++++++++++++++ ...u-boot.dtsi => imx8-capricorn-u-boot.dtsi} | 0 ...qxp-capricorn.dtsi => imx8-capricorn.dtsi} | 106 +------------- arch/arm/dts/imx8-deneb.dts | 10 -- arch/arm/dts/imx8-giedi.dts | 10 -- arch/arm/mach-imx/imx8/Kconfig | 11 +- board/siemens/capricorn/Kconfig | 18 +-- ...neb_defconfig => capricorn_cxg3_defconfig} | 4 +- configs/giedi_defconfig | 133 ------------------ include/configs/deneb.h | 16 --- 11 files changed, 137 insertions(+), 303 deletions(-) create mode 100644 arch/arm/dts/imx8-capricorn-cxg3.dts rename arch/arm/dts/{imx8qxp-capricorn-u-boot.dtsi => imx8-capricorn-u-boot.dtsi} (100%) rename arch/arm/dts/{imx8qxp-capricorn.dtsi => imx8-capricorn.dtsi} (64%) delete mode 100644 arch/arm/dts/imx8-deneb.dts delete mode 100644 arch/arm/dts/imx8-giedi.dts rename configs/{deneb_defconfig => capricorn_cxg3_defconfig} (97%) delete mode 100644 configs/giedi_defconfig delete mode 100644 include/configs/deneb.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aeccfa93fc5..cccc6956727 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -939,8 +939,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb \ - imx8-deneb.dtb \ - imx8-giedi.dtb + imx8-capricorn-cxg3.dtb \
dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts new file mode 100644 index 00000000000..2f8597579f3 --- /dev/null +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8-capricorn.dtsi" + +/ { + model = "Siemens CXG3"; + + leds_default: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + run { + label = "run"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + flt { + label = "flt"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + svc { + label = "svc"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_tx { + label = "com1-tx"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_rx { + label = "com1-rx"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_tx { + label = "com2-tx"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_rx { + label = "com2-rx"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + cloud { + label = "cloud"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wlan { + label = "wlan"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + apps { + label = "apps"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg2 { + label = "dbg2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg3 { + label = "dbg3"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg4 { + label = "dbg4"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio_keys>; + + muxcgrp: imx8qxp-som { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + >; + }; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021 + >; + }; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi similarity index 100% rename from arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi rename to arch/arm/dts/imx8-capricorn-u-boot.dtsi diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi similarity index 64% rename from arch/arm/dts/imx8qxp-capricorn.dtsi rename to arch/arm/dts/imx8-capricorn.dtsi index db5653ea1ff..4918bf8f567 100644 --- a/arch/arm/dts/imx8qxp-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -9,124 +9,20 @@ /dts-v1/;
#include "fsl-imx8qxp.dtsi" -#include "imx8qxp-capricorn-u-boot.dtsi" +#include "imx8-capricorn-u-boot.dtsi"
/ { - model = "Siemens Giedi"; - compatible = "siemens,capricorn", "fsl,imx8qxp"; - chosen { bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; stdout-path = &lpuart2; };
- leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - run { - label = "run"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - flt { - label = "flt"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - svc { - label = "svc"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_tx { - label = "com1-tx"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_rx { - label = "com1-rx"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_tx { - label = "com2-tx"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_rx { - label = "com2-rx"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - cloud { - label = "cloud"; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - wlan { - label = "wlan"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg1 { - label = "dbg1"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg2 { - label = "dbg2"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg3 { - label = "dbg3"; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg4 { - label = "dbg4"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; };
&iomuxc { pinctrl-names = "default";
muxcgrp: imx8qxp-som { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 - SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 - SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 - SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 - SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 - SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 - SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 - SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 - SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 - SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 - SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 - SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 - >; - }; - pinctrl_lpi2c0: lpi2c0grp { fsl,pins = < SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts deleted file mode 100644 index 04c764aa941..00000000000 --- a/arch/arm/dts/imx8-deneb.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Deneb"; -}; diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts deleted file mode 100644 index 0dbfef2ee97..00000000000 --- a/arch/arm/dts/imx8-giedi.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Giedi"; -}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 59d11b3179e..9a43beda6fa 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -54,15 +54,8 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP
-config TARGET_DENEB - bool "Support i.MX8QXP Capricorn Deneb board" - select BINMAN - select BOARD_LATE_INIT - select FACTORYSET - select IMX8QXP - -config TARGET_GIEDI - bool "Support i.MX8QXP Capricorn Giedi board" +config TARGET_CAPRICORN + bool "Support i.MX8QXP Capricorn board" select BINMAN select BOARD_LATE_INIT select FACTORYSET diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index c5a28ff0220..371eca346e0 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -1,19 +1,5 @@ -if TARGET_GIEDI +if TARGET_CAPRICORN
-config SYS_BOARD - default "capricorn" - -config SYS_VENDOR - default "siemens" - -config SYS_CONFIG_NAME - default "giedi" - -config IMX_CONFIG - default "board/siemens/capricorn/imximage.cfg" -endif - -if TARGET_DENEB
config SYS_BOARD default "capricorn" @@ -22,7 +8,7 @@ config SYS_VENDOR default "siemens"
config SYS_CONFIG_NAME - default "deneb" + default "capricorn-common"
config IMX_CONFIG default "board/siemens/capricorn/imximage.cfg" diff --git a/configs/deneb_defconfig b/configs/capricorn_cxg3_defconfig similarity index 97% rename from configs/deneb_defconfig rename to configs/capricorn_cxg3_defconfig index b220dc8590b..ce820e2c54f 100644 --- a/configs/deneb_defconfig +++ b/configs/capricorn_cxg3_defconfig @@ -12,9 +12,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb" +CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3" CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_TARGET_DENEB=y +CONFIG_TARGET_CAPRICORN=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig deleted file mode 100644 index e54d7ef3bc0..00000000000 --- a/configs/giedi_defconfig +++ /dev/null @@ -1,133 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" -CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_TARGET_GIEDI=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x13e000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_SYS_LOAD_ADDR=0x80280000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING=" ##v01.07" -CONFIG_REMAKE_ELF=y -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press "<Esc><Esc>" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_AUTOBOOT_KEYED_CTRLC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2073 -CONFIG_LOG=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set -CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_READ=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth1" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_SPL_CLK=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_MV88E61XX_SWITCH=y -CONFIG_MV88E61XX_CPU_PORT=5 -CONFIG_MV88E61XX_PHY_PORTS=0x7 -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set -CONFIG_SPL_TINY_MEMSET=y diff --git a/include/configs/deneb.h b/include/configs/deneb.h deleted file mode 100644 index f155bb8bf50..00000000000 --- a/include/configs/deneb.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Siemens AG - * - */ - -#ifndef __DENEB_H -#define __DENEB_H - -#include "capricorn-common.h" - -/* DDR3 board total DDR is 2 GB */ -#undef PHYS_SDRAM_1_SIZE -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ - -#endif /* __DENEB_H */
current generated flash.bin image does not longer boot on cxg3 board.
Rename bootph-pre-ram to bootph-all so flash.bin boots again!
Add u-boot specific change (add bootph-all property) in A35_0 node to imx8qxp-capricorn-u-boot.dtsi
Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v2)
Changes in v2: - add "bootph-all" in A35_0 node to u-boot.dtsi not in dts for the board!
arch/arm/dts/imx8-capricorn-u-boot.dtsi | 67 +++++++++++++------------ 1 file changed, 35 insertions(+), 32 deletions(-)
diff --git a/arch/arm/dts/imx8-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi index cba56188f86..ad5309bd969 100644 --- a/arch/arm/dts/imx8-capricorn-u-boot.dtsi +++ b/arch/arm/dts/imx8-capricorn-u-boot.dtsi @@ -6,130 +6,133 @@ #include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} { + bootph-all; +};
- bootph-pre-ram; +&A35_0 { + bootph-all; };
&mu { - bootph-pre-ram; + bootph-all; };
&clk { - bootph-pre-ram; + bootph-all; };
&iomuxc { - bootph-pre-ram; + bootph-all; };
&pd_lsio { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio0 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio1 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio2 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio3 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio4 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio5 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio6 { - bootph-pre-ram; + bootph-all; };
&pd_lsio_gpio7 { - bootph-pre-ram; + bootph-all; };
&pd_dma { - bootph-pre-ram; + bootph-all; };
&pd_dma_lpuart0 { - bootph-pre-ram; + bootph-all; };
&pd_dma_lpuart2 { - bootph-pre-ram; + bootph-all; };
&pd_conn { - bootph-pre-ram; + bootph-all; };
&pd_conn_sdch0 { - bootph-pre-ram; + bootph-all; };
&pd_conn_sdch1 { - bootph-pre-ram; + bootph-all; };
&pd_conn_sdch2 { - bootph-pre-ram; + bootph-all; };
&gpio0 { - bootph-pre-ram; + bootph-all; };
&gpio1 { - bootph-pre-ram; + bootph-all; };
&gpio2 { - bootph-pre-ram; + bootph-all; };
&gpio3 { - bootph-pre-ram; + bootph-all; };
&gpio4 { - bootph-pre-ram; + bootph-all; };
&gpio5 { - bootph-pre-ram; + bootph-all; };
&gpio6 { - bootph-pre-ram; + bootph-all; };
&gpio7 { - bootph-pre-ram; + bootph-all; };
&lpuart0 { - bootph-pre-ram; + bootph-all; };
&lpuart2 { - bootph-pre-ram; + bootph-all; };
&usdhc1 { - bootph-pre-ram; + bootph-all; };
&usdhc2 { - bootph-pre-ram; + bootph-all; };
Hi Heiko!
On Thu, 2024-11-21 at 06:25 +0100, Heiko Schocher wrote:
current generated flash.bin image does not longer boot on cxg3 board.
Rename bootph-pre-ram to bootph-all so flash.bin boots again!
Add u-boot specific change (add bootph-all property) in A35_0 node to imx8qxp-capricorn-u-boot.dtsi
Signed-off-by: Heiko Schocher hs@denx.de
Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
(no changes since v2)
Changes in v2:
- add "bootph-all" in A35_0 node to u-boot.dtsi not
in dts for the board!
arch/arm/dts/imx8-capricorn-u-boot.dtsi | 67 +++++++++++++------------ 1 file changed, 35 insertions(+), 32 deletions(-)
diff --git a/arch/arm/dts/imx8-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi index cba56188f86..ad5309bd969 100644 --- a/arch/arm/dts/imx8-capricorn-u-boot.dtsi +++ b/arch/arm/dts/imx8-capricorn-u-boot.dtsi @@ -6,130 +6,133 @@ #include "imx8qxp-u-boot.dtsi" &{/imx8qx-pm} {
- bootph-all;
+};
- bootph-pre-ram;
+&A35_0 { + bootph-all; }; &mu {
- bootph-pre-ram;
- bootph-all;
}; &clk {
- bootph-pre-ram;
- bootph-all;
}; &iomuxc {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio0 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio1 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio2 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio3 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio4 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio5 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio6 {
- bootph-pre-ram;
- bootph-all;
}; &pd_lsio_gpio7 {
- bootph-pre-ram;
- bootph-all;
}; &pd_dma {
- bootph-pre-ram;
- bootph-all;
}; &pd_dma_lpuart0 {
- bootph-pre-ram;
- bootph-all;
}; &pd_dma_lpuart2 {
- bootph-pre-ram;
- bootph-all;
}; &pd_conn {
- bootph-pre-ram;
- bootph-all;
}; &pd_conn_sdch0 {
- bootph-pre-ram;
- bootph-all;
}; &pd_conn_sdch1 {
- bootph-pre-ram;
- bootph-all;
}; &pd_conn_sdch2 {
- bootph-pre-ram;
- bootph-all;
}; &gpio0 {
- bootph-pre-ram;
- bootph-all;
}; &gpio1 {
- bootph-pre-ram;
- bootph-all;
}; &gpio2 {
- bootph-pre-ram;
- bootph-all;
}; &gpio3 {
- bootph-pre-ram;
- bootph-all;
}; &gpio4 {
- bootph-pre-ram;
- bootph-all;
}; &gpio5 {
- bootph-pre-ram;
- bootph-all;
}; &gpio6 {
- bootph-pre-ram;
- bootph-all;
}; &gpio7 {
- bootph-pre-ram;
- bootph-all;
}; &lpuart0 {
- bootph-pre-ram;
- bootph-all;
}; &lpuart2 {
- bootph-pre-ram;
- bootph-all;
}; &usdhc1 {
- bootph-pre-ram;
- bootph-all;
}; &usdhc2 {
- bootph-pre-ram;
- bootph-all;
};
Boards which use DCD data in SCFW can drop SPL.
We tried in our mainline rework to use this approach too as other imx8qxp boards do in mainline. But we failed ... it was a hard way to understand the reason!
We cannot use DCD image in container as the SCFW from siemens, does the RAM init on boot itself!
Siemens SCFW reads the RAM config from i2c eeprom and dependent on this settings, initializes the RAM.
Adding DCD data to the bootcontainer will result in hang of the SCFW, also DCD data in container image is static which do not fit our needs.
So we must drop DCD data image, and this has the side effect that we need SPL, as the task which loads the images from the container only loads the images to addresses, and if executed bit is set, starts them.
As now RAM is not initialized from it, and there is no option to "wait until SCFW has setup RAM", we can only load SPL into internal RAM at this point, as than SPL and SCFW boot parallel.
The SPL itself then uses the SCU API to communicate with the SCFW and it seems that SCFW only responds to this API requests when RAM setup is already done by the SCFW, which has a side-effect of a "sync" for the RAM setup is done by SCFW!
We checked if SPL is always save in accessing RAM for loading images to it! For tests, we added in our RAM init part in the SCFW long delays (10 seconds and more) as we thought there is such a sync missing, and we can break the board through delaying RAM setup... but we did not managed to fail booting U-Boot from SPL!
Signed-off-by: Heiko Schocher hs@denx.de
---
(no changes since v2)
Changes in v2: - add comment from Walter fix typo: than -> then
board/siemens/capricorn/imximage.cfg | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index 4350e2967cc..e45f2c9589e 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -9,6 +9,10 @@
/* Boot from SD, sector size 0x400 */ BOOT_FROM sd + +/* skip DCD data, as firmware initializes the RAM */ +DCD_SKIP true + /* SoC type IMX8QX */ SOC_TYPE IMX8QX /* Append seco container image */
fix wrong comment.
Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
---
(no changes since v2)
Changes in v2: - add Reviewed-by from Alexander
board/siemens/capricorn/imximage.cfg | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index e45f2c9589e..f73c5a7a9b0 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -21,5 +21,6 @@ APPEND ahab-container.img CONTAINER /* Add scfw image with exec attribute */ IMAGE SCU capricorn-scfw-tcm.bin -/* Add ATF image with exec attribute */ + +/* Add SPL image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin 0x00100000
sync the image names in imximage.cfg with the ones used in arch/arm/dts/imx8qxp-u-boot.dtsi
Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
board/siemens/capricorn/imximage.cfg | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index f73c5a7a9b0..7fd3fb8b72e 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -15,12 +15,18 @@ DCD_SKIP true
/* SoC type IMX8QX */ SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND ahab-container.img +/* + * Append seco container image, + * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi + */ +APPEND mx8qxc0-ahab-container.img /* Create the 2nd container */ CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU capricorn-scfw-tcm.bin +/* + * Add scfw image with exec attribute + * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi + */ +IMAGE SCU mx8qx-mek-scfw-tcm.bin
/* Add SPL image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin 0x00100000
make savedefconfig and add SCU_WDT and fix environment offsets, as since silicon c0 the boot container takes place at offset 0 and so the u-boot-env must be moved outside of the boot container area.
Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
---
Changes in v3: - use renamed Kconfig symbol CONFIG_WDT_SIEMENS_PMIC
Changes in v2: - add comments from Fabio fix typo: silicium -> silicon - add Reviewed-by from Alexander - use renamed Kconfig symbol CONFIG_WDT_SCU_PMIC
configs/capricorn_cxg3_defconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/configs/capricorn_cxg3_defconfig b/configs/capricorn_cxg3_defconfig index ce820e2c54f..dc40880b1f7 100644 --- a/configs/capricorn_cxg3_defconfig +++ b/configs/capricorn_cxg3_defconfig @@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3" CONFIG_SPL_TEXT_BASE=0x100000 @@ -25,7 +25,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 +CONFIG_ENV_OFFSET_REDUND=0x202000 CONFIG_IDENT_STRING=" ##v01.06" CONFIG_REMAKE_ELF=y # CONFIG_EFI_LOADER is not set @@ -55,9 +55,10 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x4000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y @@ -112,10 +113,13 @@ CONFIG_PHYLIB=y CONFIG_MV88E61XX_SWITCH=y CONFIG_MV88E61XX_CPU_PORT=5 CONFIG_MV88E61XX_PHY_PORTS=0x7 +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC_SHARE_MDIO=y CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8=y @@ -129,5 +133,7 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set +# CONFIG_WATCHDOG is not set +CONFIG_WDT=y +CONFIG_WDT_SIEMENS_PMIC=y CONFIG_SPL_TINY_MEMSET=y
sync spl code with 8qxp-mek board.
Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
board/siemens/capricorn/spl.c | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c index 696b5ebd340..7ee2895b6d4 100644 --- a/board/siemens/capricorn/spl.c +++ b/board/siemens/capricorn/spl.c @@ -15,12 +15,30 @@ #include <dm/uclass-internal.h> #include <dm/device-internal.h>
+#include <firmware/imx/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> + DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19) +static iomux_cfg_t usdhc2_sd_pwr[] = { + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + void spl_board_init(void) { struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) { @@ -34,8 +52,28 @@ void spl_board_init(void)
timer_init();
+ imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr)); + gpio_direction_output(USDHC2_SD_PWR, 0); + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + imx8_power_off_pd_devices(NULL, 0); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; } +#endif
void board_init_f(ulong dummy) {
add wdt device
Signed-off-by: Heiko Schocher hs@denx.de
---
(no changes since v2)
Changes in v2: - add comments rom Fabio and Enrico do not remove DMA for console remove u-boot specific property addition, instead add it in arch/arm/dts/imx8qxp-u-boot.dtsi
arch/arm/dts/imx8-capricorn.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/imx8-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi index 4918bf8f567..3734a9d21f1 100644 --- a/arch/arm/dts/imx8-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -17,6 +17,11 @@ stdout-path = &lpuart2; };
+ /* create device for u-boot wdt command */ + scu-wdt { + compatible = "siemens,scu-wdt"; + }; + };
&iomuxc {
with newest SCFW build_info() works now, so call it from checkboard() now.
As we only use uart2 as console, do not init uart0.
Signed-off-by: Heiko Schocher hs@denx.de
---
(no changes since v2)
Changes in v2: - add comments from Fabio rename subject line and rework commit message, alse remove unneeded comment in checkboard()
board/siemens/capricorn/board.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index ad474d9baa0..bf04f12c75b 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -63,8 +63,7 @@ int board_early_init_f(void) sc_pm_clock_rate_t rate = SC_80MHZ; int ret;
- ret = sc_pm_setup_uart(SC_R_UART_0, rate); - ret |= sc_pm_setup_uart(SC_R_UART_2, rate); + ret = sc_pm_setup_uart(SC_R_UART_2, rate); if (ret) return ret;
@@ -271,11 +270,7 @@ int checkboard(void) { puts("Board: Capricorn\n");
- /* - * Running build_info() doesn't work with current SCFW blob. - * Uncomment below call when new blob is available. - */ - /*build_info();*/ + build_info();
print_bootinfo(); return 0;
Hi Heiko!
On Thu, 2024-11-21 at 06:25 +0100, Heiko Schocher wrote:
with newest SCFW build_info() works now, so call it from checkboard() now.
As we only use uart2 as console, do not init uart0.
Signed-off-by: Heiko Schocher hs@denx.de
Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
(no changes since v2)
Changes in v2:
- add comments from Fabio
rename subject line and rework commit message, alse remove unneeded comment in checkboard()
board/siemens/capricorn/board.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index ad474d9baa0..bf04f12c75b 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -63,8 +63,7 @@ int board_early_init_f(void) sc_pm_clock_rate_t rate = SC_80MHZ; int ret;
- ret = sc_pm_setup_uart(SC_R_UART_0, rate);
- ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
- ret = sc_pm_setup_uart(SC_R_UART_2, rate);
if (ret) return ret; @@ -271,11 +270,7 @@ int checkboard(void) { puts("Board: Capricorn\n");
- /*
* Running build_info() doesn't work with current SCFW blob.* Uncomment below call when new blob is available.*/- /*build_info();*/
- build_info();
print_bootinfo(); return 0;
From: Alessandro Zini alessandro.zini@siemens.com
Add the HW version read directly from EEPROM.
EEPROM chip data structure is now in a .h file common to draco and capricorn.
Therefore move out the definitions in draco board to siemens common place.
From: Alessandro Zini alessandro.zini@siemens.com Signed-off-by: Alessandro Zini alessandro.zini@siemens.com Signed-off-by: Heiko Schocher hs@denx.de
---
(no changes since v2)
Changes in v2: - add comment from Fabio add From line, as patch is from Alessandro fix typo in commit description: drace -> draco - remove CONFIG_XPL_BUILD in board_init as board_init is not called from SPL.
board/siemens/capricorn/board.c | 21 ++++++++++++++++ board/siemens/common/board.h | 44 +++++++++++++++++++++++++++++++++ board/siemens/draco/board.h | 10 ++------ 3 files changed, 67 insertions(+), 8 deletions(-) create mode 100644 board/siemens/common/board.h
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index bf04f12c75b..decac63db3b 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -26,6 +26,7 @@ #include <asm/arch-imx8/clock.h> #endif #include <linux/delay.h> +#include "../common/board.h" #include "../common/eeprom.h" #include "../common/factoryset.h"
@@ -278,6 +279,26 @@ int checkboard(void)
int board_init(void) { + struct chip_data eeprom_data = {}; + int ret; + + ret = siemens_ee_setup(); + if (ret) { + printf("'siemens_ee_setup' failed, ret: %d\n", ret); + goto skip; + } + + ret = siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP, + (uchar *)&eeprom_data, + sizeof(eeprom_data)); + if (ret) { + printf("'siemens_ee_read_data' failed, ret: %d\n", ret); + goto skip; + } + + printf("HW Version: %s\n", eeprom_data.shwver); +skip: + setup_fec(); return 0; } diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h new file mode 100644 index 00000000000..db34bc78711 --- /dev/null +++ b/board/siemens/common/board.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common board functions for siemens based boards + * (C) Copyright 2022 Siemens Schweiz AG + */ + +#ifndef __COMMON_BOARD_H +#define __COMMON_BOARD_H + +/* + * Chip data + * Offset in EEPROM: 0x120 - 0x14F + * + * ----------------------------------------------------------------------------------- + * | Address range | Content | + * ----------------------------------------------------------------------------------- + * | 0x120 - 0x123 | Magic Number - 0x43484950 (4 byte) | + * ----------------------------------------------------------------------------------- + * | 0x124 - 0x133 | Device Nomenclature (15 + 1 byte) | + * ----------------------------------------------------------------------------------- + * | 0x134 - 0x13A | HW Version of the form "v00.00" (6 + 1 byte) | + * | | - First 2 digits: Layout revision (starting from 1) | + * | | - Last 2 digits: Assembly variant revision (starting from 1) | + * ----------------------------------------------------------------------------------- + * | 0x13B - 0x13F | Flash Size in Gibit (4 + 1 byte) | + * ----------------------------------------------------------------------------------- + * | 0x140 - 0x144 | Ram Size in Gibit (4 + 1 byte) | + * ----------------------------------------------------------------------------------- + * | 0x145 - 0x14F | Sequence number, equals DMC-code (10 + 1 byte) [OBSOLETE] | + * ----------------------------------------------------------------------------------- + */ + +#define MAGIC_CHIP 0x50494843 +#define EEPROM_CHIP_OFFSET 0x120 + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; + char flash_size[5]; + char ram_size[5]; +}; + +#endif /* __COMMON_BOARD_H */ diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h index 935f340a8f2..77f35a6ab7b 100644 --- a/board/siemens/draco/board.h +++ b/board/siemens/draco/board.h @@ -11,6 +11,8 @@ #ifndef _BOARD_DRACO_H_ #define _BOARD_DRACO_H_
+#include "../common/board.h" + #define PARGS(x) #x , /* Parameter Name */ \ settings.ddr3.x, /* EEPROM Value */ \ ddr3_default.x, /* Default Value */ \ @@ -18,8 +20,6 @@
#define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
-#define MAGIC_CHIP 0x50494843 - /* Automatic generated definition */ /* Wed, 16 Apr 2014 16:50:41 +0200 */ /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ @@ -43,12 +43,6 @@ struct ddr3_data { char manu_marking[32]; /* "default \0" */ };
-struct chip_data { - unsigned int magic; - char sdevname[16]; - char shwver[7]; -}; - struct draco_baseboard_id { struct ddr3_data ddr3; struct chip_data chip;
From: Enrico Leto enrico.leto@siemens.com
Get the memory region information from system controller to reduce the number of platform specific headers. We were aligned on NXP mek board implementation. This need at least 1 header per memory configuration.
Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
board/siemens/capricorn/board.c | 34 ++++++++++++++++++++++++++++++ include/configs/capricorn-common.h | 4 +++- 2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index decac63db3b..484e2707183 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -73,6 +73,40 @@ int board_early_init_f(void) return 0; }
+#ifndef CONFIG_XPL_BUILD +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + sc_faddr_t addr_start, addr_end; + sc_faddr_t sdram_1_size, sdram_2_size; + sc_err_t sc_err; + + sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end); + if (sc_err == SC_ERR_NONE) { + if (addr_end < 0x100000000) { + /* only lower RAM available */ + sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1; + sdram_2_size = 0; + } else { + /* lower RAM (2 GB) und upper RAM available */ + sdram_1_size = SZ_2G; + sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2; + } + } else { + /* Get default in case it would fail */ + sdram_1_size = PHYS_SDRAM_1_SIZE; + sdram_2_size = PHYS_SDRAM_2_SIZE; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = sdram_1_size; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = sdram_2_size; +} +#endif /* ! CONFIG_XPL_BUILD */ + #define ENET_PHY_RESET IMX_GPIO_NR(0, 3) #define ENET_TEST_1 IMX_GPIO_NR(0, 8) #define ENET_TEST_2 IMX_GPIO_NR(0, 9) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1f61b2b6af6..4d95f3fd79b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -95,7 +95,9 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -/* DDR3 board total DDR is 1 GB */ +/* Set default values to the smallest DDR we have in capricorn modules + * Use it in case the system controller would return an error + */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
From: Enrico Leto enrico.leto@siemens.com
The eeprom contains the information on which module we are running, so read it from the eeprom and print it on the console.
Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
board/siemens/capricorn/board.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 484e2707183..390a7b0d841 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -314,6 +314,7 @@ int checkboard(void) int board_init(void) { struct chip_data eeprom_data = {}; + char module_name[16]; int ret;
ret = siemens_ee_setup(); @@ -322,6 +323,11 @@ int board_init(void) goto skip; }
+ /* Get module name from EEPROM */ + siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, module_name, + sizeof(module_name)); + printf("CPU module: %s\n", module_name); + ret = siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP, (uchar *)&eeprom_data, sizeof(eeprom_data));
From: Enrico Leto enrico.leto@siemens.com
Add siemens specific memory test. Enable it through Kconfig option SPL_CMT. The test is required from our HW team. It runs over temperature during many days: * must run indefinitively through the *whole* DDR area, so we cannot use linux memtest for example. * must write/read/check all values
Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de
---
(no changes since v2)
Changes in v2: add From tag reworked the commit message a little bit
board/siemens/capricorn/Kconfig | 7 + board/siemens/capricorn/Makefile | 1 + board/siemens/capricorn/spl.c | 5 + board/siemens/capricorn/spl_memory_test.c | 158 ++++++++++++++++++++++ board/siemens/capricorn/spl_memory_test.h | 7 + 5 files changed, 178 insertions(+) create mode 100644 board/siemens/capricorn/spl_memory_test.c create mode 100644 board/siemens/capricorn/spl_memory_test.h
diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index 371eca346e0..03a433df2aa 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -14,3 +14,10 @@ config IMX_CONFIG default "board/siemens/capricorn/imximage.cfg"
endif + + +config SPL_CMT + bool "Enable Siemens SPL RAM test" + depends on SPL + help + Enable SIemens SPL RAM test. diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index e8a24c448b9..b8350d96d04 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -8,6 +8,7 @@ obj-y += ../common/eeprom.o
ifdef CONFIG_XPL_BUILD obj-y += spl.o +obj-$(CONFIG_SPL_CMT) += spl_memory_test.o else obj-y += ../common/factoryset.o endif diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c index 7ee2895b6d4..5865cde80b4 100644 --- a/board/siemens/capricorn/spl.c +++ b/board/siemens/capricorn/spl.c @@ -20,6 +20,7 @@ #include <asm/arch/iomux.h> #include <asm/gpio.h> #include <asm/arch/sys_proto.h> +#include "spl_memory_test.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -58,6 +59,10 @@ void spl_board_init(void) preloader_console_init();
puts("Normal Boot\n"); + +#if IS_ENABLED(CONFIG_SPL_CMT) + spl_siemens_memory_full_test(); +#endif }
void spl_board_prepare_for_boot(void) diff --git a/board/siemens/capricorn/spl_memory_test.c b/board/siemens/capricorn/spl_memory_test.c new file mode 100644 index 00000000000..84c97e7853c --- /dev/null +++ b/board/siemens/capricorn/spl_memory_test.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Siemens AG 2020 + * + * SPL Full Memory Test + * - memory test through the full DDR area + * - refresh over temperature torture (write all, read all) + * + * Remark: + * This test has ran properly with the definition of the RAM sizes in board + * headers. Since these headers are removed it's necessary to set the correct + * values to PHYS_SDRAM_1_SIZE & PHYS_SDRAM_2_SIZE before to recompile. + * + * An alternative is to refactor the code to get the size info from system + * controller + */ + +#include <init.h> +#include <log.h> + +/* ----- Defines ----- */ +#define CHECK_LOWER_UPPER + +#define LEVEL2_PRINT 0x0FFFFFFF + +/* use 0x7FFF0000 for shorter loop test */ +#define BASE_OFFSET 0x00000000 + +/* ----- Types ----- */ +struct ct_t { + unsigned long *start; + unsigned long *end; +}; + +/* ----- Variables ----- */ +static struct ct_t ct; +static unsigned long error_counter; + +static void print_parameters(void) +{ + printf("\nstart addr: %p\n", ct.start); + printf("end addr : %p\n", ct.end); +} + +static void run_test(void) +{ + /* moved full test in one void */ + unsigned long *address; /* 512 */ + unsigned long ebyte1; + unsigned long ebyte2; + unsigned int i; + unsigned long rpattern; + + for (i = 0; i <= 255; i++) { + memset(&ebyte1, i, sizeof(ebyte1)); + ebyte2 = ~ebyte1; + printf("LWord: %016lx #LWord: %016lx\n", ebyte1, ebyte2); + + /* write all bytes -> duration ~ 150 s */ + for (address = ct.start; address <= ct.end; address++) { +#ifdef LEVEL2_PRINT + if (((unsigned long)address & LEVEL2_PRINT) == 0) + printf("write to %p - %p\n", address, + (void *)((unsigned long)address + + LEVEL2_PRINT)); +#endif + *address = ebyte1; + address++; + *address = ebyte2; + } + + /* check all bytes */ + for (address = ct.start; address <= ct.end; address++) { +#ifdef LEVEL2_PRINT + if (((unsigned long)address & LEVEL2_PRINT) == 0) + printf("check from %p - %p\n", address, + (void *)((unsigned long)address + + LEVEL2_PRINT)); +#endif + + rpattern = *address; + if (rpattern != ebyte1) { + error_counter++; + printf("Error! Read: %016lX Wrote: %016lX Address: %p\n", + rpattern, ebyte1, address); + } + + address++; + rpattern = *address; + if (rpattern != ebyte2) { + error_counter++; + printf("Error! Read: %016lX Wrote: %016lX Address: %p\n", + rpattern, ebyte2, address); + } + } + } +} + +#ifdef CHECK_LOWER_UPPER +void test_lower_upper(void) +{ + /* + * write different values at the same address of both memory areas + * and check them + */ +#define TEST_ADDRESS 0x12345670UL +#define LOWER_ADDRESS (PHYS_SDRAM_1 + TEST_ADDRESS) +#define UPPER_ADDRESS (PHYS_SDRAM_2 + TEST_ADDRESS) +#define LOWER_VALUE 0x0011223344556677 +#define UPPER_VALUE 0x89ab89abffeeddcc + + *(unsigned long *)LOWER_ADDRESS = LOWER_VALUE; + *(unsigned long *)UPPER_ADDRESS = UPPER_VALUE; + + puts("\nlower-upper memory area test\n"); + printf("write %016lx to lower address %010lx\n", LOWER_VALUE, + LOWER_ADDRESS); + printf("write %016lx to upper address %010lx\n", UPPER_VALUE, + UPPER_ADDRESS); + printf("read %016lx from lower address %010lx\n", + *(unsigned long *)LOWER_ADDRESS, LOWER_ADDRESS); + printf("read %016lx from upper address %010lx\n", + *(unsigned long *)UPPER_ADDRESS, UPPER_ADDRESS); +} +#endif + +void spl_siemens_memory_full_test(void) +{ + unsigned long loopc = 0; + + puts("\nSPL: memory cell test\n"); + +#ifdef CHECK_LOWER_UPPER + if (PHYS_SDRAM_2_SIZE != 0) + test_lower_upper(); +#endif + + while (true) { + /* imx8x has 2 memory areas up to 2 GB */ + + /* 1st memory area @ 0x80000000 */ + ct.start = (unsigned long *)(PHYS_SDRAM_1 + BASE_OFFSET); + ct.end = (unsigned long *)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - 1); + print_parameters(); + run_test(); + + /* 2nd memory area @ 0x880000000 */ + if (PHYS_SDRAM_2_SIZE != 0) { + ct.start = (unsigned long *)(PHYS_SDRAM_2 + BASE_OFFSET); + ct.end = (unsigned long *)(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE - 1); + print_parameters(); + run_test(); + } + + loopc++; + printf("loop: %ld, errors: %ld\n\n", loopc, error_counter); + }; +} diff --git a/board/siemens/capricorn/spl_memory_test.h b/board/siemens/capricorn/spl_memory_test.h new file mode 100644 index 00000000000..28df284b6d5 --- /dev/null +++ b/board/siemens/capricorn/spl_memory_test.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright Siemens AG 2020 + * + */ + +void spl_siemens_memory_full_test(void);
From: Enrico Leto enrico.leto@siemens.com
The signal integrity test generates pattern on DDR lines for certification. The signals must be as fast as possible and unidirectional.
The test is required from our HW team. The available u-boot memory test doesn't full fill the our requirements.
The test is planed to be used in all new siemens boards.
Signed-off-by: Enrico Leto enrico.leto@siemens.com
Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v2)
Changes in v2: Add From tag
board/siemens/capricorn/Kconfig | 2 + board/siemens/capricorn/Makefile | 1 + board/siemens/common/Kconfig | 4 + board/siemens/common/ddr_si_test.c | 348 +++++++++++++++++++++++++++++ 4 files changed, 355 insertions(+) create mode 100644 board/siemens/common/ddr_si_test.c
diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index 03a433df2aa..fe230971e97 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -21,3 +21,5 @@ config SPL_CMT depends on SPL help Enable SIemens SPL RAM test. + +source "board/siemens/common/Kconfig" diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index b8350d96d04..a03d54ef3b3 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -11,4 +11,5 @@ obj-y += spl.o obj-$(CONFIG_SPL_CMT) += spl_memory_test.o else obj-y += ../common/factoryset.o +obj-$(CONFIG_DDR_SI_TEST) += ../common/ddr_si_test.o endif diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig index 131439fcfea..4ae12b1c973 100644 --- a/board/siemens/common/Kconfig +++ b/board/siemens/common/Kconfig @@ -1,2 +1,6 @@ config FACTORYSET bool + +config DDR_SI_TEST + bool "DDR signal integrity test implementations" + default y diff --git a/board/siemens/common/ddr_si_test.c b/board/siemens/common/ddr_si_test.c new file mode 100644 index 00000000000..c1f523eb3f4 --- /dev/null +++ b/board/siemens/common/ddr_si_test.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Siemens AG 2023 + * + * DDR signal integrity test + * Check signals on DDR lines + * - signals must be as fast as possible and generate long burst + * - signals must be unidirectional (to DDR or from DDR only) + * + * Set pattern: define 2^n 32-bit patterns (up to 4) + * Addresses: must be multiple of 16 to avoid checks in loops + * Test functions + * - write: write pattern to memory area for iteration times + * - read: write pattern once to memory area, read for iteration times + */ + +#include <command.h> +#include <exports.h> +#include <time.h> +#if CONFIG_IS_ENABLED(AM33XX) +#include <asm/arch-am33xx/hardware_am33xx.h> +#include <asm/arch-am33xx/cpu.h> +#include <asm/io.h> +#endif + +/* enable some print for debugging */ +#ifdef PR_DEBUG + #define PDEBUG(fmt, args...) printf(fmt, ## args) +#else + #define PDEBUG(fmt, args...) +#endif + +/* define 4 32-bit patterns */ +#define MAX_PTN_SIZE (128) +#define PTN_ARRAY_SIZE (MAX_PTN_SIZE / (8 * sizeof(u32))) + +/* define test direction */ +#define DIR_READ 0 +#define DIR_WRITE 1 + +static union { + u64 l[2]; + u32 s[4]; + } test_pattern; +static int num_ptn32; + +#if CONFIG_IS_ENABLED(AM33XX) +static inline void wdt_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} + +static inline void wdt_enable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xBBBB, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x4444, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} +#else /* ! */ +static inline void wdt_disable(void) {} + +static inline void wdt_enable(void) {} +#endif /* CONFIG_IS_ENABLED(AM33XX) */ + +static int do_ddr_set_ptn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i, n; + + if (argc < 1) + return CMD_RET_USAGE; + + /* number of patterns: 2 exponent */ + n = argc - 1; + if (n > PTN_ARRAY_SIZE || (n & (n - 1))) + return CMD_RET_USAGE; + num_ptn32 = n; + + /* get patterns */ + for (i = 0; i < n; i++) + test_pattern.s[i] = simple_strtoul(argv[i + 1], NULL, 0); + + printf("Test pattern set\n"); + + return CMD_RET_SUCCESS; +} + +static int do_ddr_show_ptn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (!num_ptn32) { + printf("No pattern available\n"); + } else { + u32 *buf = test_pattern.s; + int len = num_ptn32; + int i; + + printf("Pattern: "); + for (i = 0 ; i < len; i++) + printf("0x%08X ", *buf++); + + printf("\n"); + } + + return CMD_RET_SUCCESS; +} + +static void ddr_read32(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register volatile u32 *addr = (u32 *)start_addr; + register u64 count = n_word; + + while (count) { + (void)*addr++; + PDEBUG("Read 0x%08X from 0x%p\n", val, addr - 1); + count--; + } + } +} + +static void ddr_read64(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register volatile u64 *addr = (u64 *)start_addr; + register u64 count = n_word; + + if (num_ptn32 == 4) + count *= 2; + + /* + * 64 & 128 bit pattern. Increase the nummber of read + * commands in the loop to generate longer burst signal + */ + while (count) { + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + /* + * underflow cannot happen since n_word = end - + * start, end & start addresses are checked to be + * multiple of 16 + */ + count -= 8; + } + } +} + +static void ddr_write32(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register u32 *addr = (u32 *)start_addr; + register u32 ptn = *test_pattern.s; + register u64 count = n_word; + + while (count) { + PDEBUG("Write 0x%08X to 0x%p\n", ptn, addr); + *addr++ = ptn; + count--; + } + } +} + +static void ddr_write64(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register u64 *addr = (u64 *)start_addr; + register u64 ptnA = test_pattern.l[0]; + register u64 ptnB = test_pattern.l[1]; + register u64 count = n_word; + + if (num_ptn32 == 2) + ptnB = ptnA; + else + count *= 2; + + /* + * 64 & 128 bit pattern. Increase the nummber of write + * commands in the loop to generate longer burst signal + */ + while (count) { + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + /* + * underflow cannot happen since n_word = end - + * start, end & start addresses are checked to be + * multiple of 16 + */ + count -= 8; + } + } +} + +static int do_ddr_si_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u64 start_addr, end_addr, n_word; + u64 ts_start, ts_end; + unsigned long iteration, wr_iter; + int direction, i; + + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + /* get arguments */ + direction = strcmp(argv[0], "read") ? DIR_WRITE : DIR_READ; + start_addr = simple_strtoul(argv[1], NULL, 0); + end_addr = simple_strtoul(argv[2], NULL, 0); + iteration = simple_strtoul(argv[3], NULL, 10); + + n_word = (end_addr - start_addr) / (num_ptn32 * 4); + printf("\nDDR signal integrity %s test: start\n", argv[0]); + /* checks */ + if (start_addr & 0xF) { + printf("ERROR: start_address should be 16 bytes aligned\n\n"); + return CMD_RET_USAGE; + } + + if (end_addr & 0xF) { + printf("ERROR: end_address should be 16 bytes aligned\n\n"); + return CMD_RET_USAGE; + } + + if (start_addr >= end_addr) { + printf("ERROR: end_address is not bigger than start_address\n\n"); + return CMD_RET_USAGE; + } + + if (!iteration) { + printf("ERROR: no iteration specified\n\n"); + return CMD_RET_USAGE; + } + + if (!num_ptn32) { + printf("ERROR: no test pattern specified\n\n"); + return CMD_RET_USAGE; + } + + /* print parameters */ + printf("start_address = 0x%016llX\n", start_addr); + printf("end_address = 0x%016llX\n", end_addr); + printf("iterations = %lu\n", iteration); + + /* print pattern */ + printf("test pattern 0x"); + for (i = 0; i < num_ptn32; i++) + printf("%08X", test_pattern.s[i]); + + printf("\n"); + + wdt_disable(); + + /* writing */ + printf("Writing..\n"); + ts_start = get_timer_us(0); + + if (direction == DIR_READ) + wr_iter = 1; + else + wr_iter = iteration; + + if (num_ptn32 == 1) + ddr_write32(start_addr, n_word, wr_iter); + else + ddr_write64(start_addr, n_word, wr_iter); + + ts_end = get_timer_us(0); + + /* reading */ + if (direction == DIR_READ) { + printf("Reading..\n"); + /* we need read time, just overwrite */ + ts_start = get_timer_us(0); + + if (num_ptn32 == 1) + ddr_read32(start_addr, n_word, iteration); + else + ddr_read64(start_addr, n_word, iteration); + + ts_end = get_timer_us(0); + } + + wdt_enable(); + + /* print stats */ + printf("DONE."); + printf(" Bytes=%llu ", n_word * num_ptn32 * 4 * iteration); + printf(" Time=%llu us ", ts_end - ts_start); + printf("\nDDR signal integrity %s test: end\n", argv[0]); + + return CMD_RET_SUCCESS; +} + +static char ddr_si_help_text[] = + "- DDR signal integrity test\n\n" + "ddr_si setptn <pattern> [<pattern>] : set [1,2,4] 32-bit patterns\n" + "ddr_si showptn : show patterns\n" + "ddr_si read <start> <end> <iterations> : run test for reading\n" + "ddr_si write <start> <end> <iterations> : run test for writing\n" + "\nWith\n" + "\t<pattern>: 32-bit pattern in hex format\n" + "\t<start>: test start address in hex format\n" + "\t<end>: test end address in hex format\n" + "\t<iterations>: number of iterations\n"; + +U_BOOT_CMD_WITH_SUBCMDS(ddr_si, "DDR si test", ddr_si_help_text, + U_BOOT_SUBCMD_MKENT(setptn, 5, 0, do_ddr_set_ptn), + U_BOOT_SUBCMD_MKENT(showptn, 1, 0, do_ddr_show_ptn), + U_BOOT_SUBCMD_MKENT(read, 4, 0, do_ddr_si_test), + U_BOOT_SUBCMD_MKENT(write, 4, 0, do_ddr_si_test));
From: Enrico Leto enrico.leto@siemens.com
update MAINTAINERS file, add some more board maintainers.
Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Alexander Sverdlin alexander.sverdlin@siemens.com
---
(no changes since v2)
Changes in v2: - add Reviewed-by from Alexander
board/siemens/capricorn/MAINTAINERS | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index b4c52032cc9..5f467aa9b6e 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,10 +1,12 @@ CAPRICORN BOARD +M: Alexander Sverdlin alexander.sverdlin@siemens.com M: Anatolij Gustschin agust@denx.de +M: Heiko Schocher hs@denx.de +M: Walter Schweizer walter.schweizer@siemens.com S: Maintained +F: arch/arm/dts/imx8-capricorn-cxg3.dts +F: arch/arm/dts/imx8-capricorn-u-boot.dtsi +F: arch/arm/dts/imx8-capricorn.dtsi F: board/siemens/capricorn/ +F: configs/capricorn_cxg3_defconfig F: include/configs/capricorn-common.h -F: include/configs/deneb.h -F: include/configs/giedi.h -F: include/configs/siemens-env-common.h -F: configs/deneb_defconfig -F: configs/giedi_defconfig
participants (3)
-
Heiko Schocher -
Stefan Roese -
Sverdlin, Alexander