[U-Boot] [PATCH 0/5] arm: ls1021a: merge SoC specific code in a separate file

Yuan Yao

4 Dec 2015 4 Dec '15

10:37 a.m.

Yuan Yao(5): arm: ls1021a: merge SoC specific code in a separate file arm: ls102xa: enable all the snoop signal for masters. ls102xa: Enable snoop and DVM message requests.

armv7/fsl-ls102xa: Workaround for DDR erratum A008514 Changed in v2: Update the write value to 63b2_0042h; move erratum a008336 and a008514 to soc specific file Changed in v2: Update the patch commit message.

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Yuan Yao

4 Dec 4 Dec

10:37 a.m.

New subject: [U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao yao.yuan@freescale.com ---

arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/soc.c | 66 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++ board/freescale/ls1021aqds/ls1021aqds.c | 49 +----------------- board/freescale/ls1021atwr/ls1021atwr.c | 42 +--------------- 5 files changed, 83 insertions(+), 87 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2311468..0228300 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o

obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000..0fdd6d4 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,66 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ls102xa_soc.h> + +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + +int arch_soc_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d889ad5..be3358a 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> @@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; }

-unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major;

#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -205,40 +193,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif

-#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - } + arch_soc_init();

#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4918c11..8eaff5f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> @@ -138,17 +139,6 @@ int checkboard(void) return 0; }

-unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -394,8 +384,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major;

#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -407,33 +395,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif

-#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - } + arch_soc_init();

#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) {

-- 2.1.0.27.g96db324

Yuan Yao

10:37 a.m.

New subject: [U-Boot] [PATCH 2/5] arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal for various masters.

Signed-off-by: Yuan Yao yao.yuan@freescale.com ---

arch/arm/cpu/armv7/ls102xa/soc.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++ 2 files changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 0fdd6d4..6036473 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -62,5 +62,13 @@ int arch_soc_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); }

+ /* Enable all the snoop signal for various masters */ + out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | + SCFG_SNPCNFGCR_DCU_RD_WR | + SCFG_SNPCNFGCR_SATA_RD_WR | + SCFG_SNPCNFGCR_USB3_RD_WR | + SCFG_SNPCNFGCR_DBG_RD_WR | + SCFG_SNPCNFGCR_EDMA_SNP); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 1bcdf04..0527576 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -150,6 +150,12 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000

/* Supplemental Configuration Unit */

-- 2.1.0.27.g96db324

Yuan Yao

10:37 a.m.

New subject: [U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

Signed-off-by: Yuan Yao yao.yuan@freescale.com ---

arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 6036473..97ba6d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -40,8 +40,14 @@ int arch_soc_init(void)

/* * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) + * All the slave insterfaces. */ + out_le32(&cci->slave[0].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[1].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[2].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);

-- 2.1.0.27.g96db324

Yuan Yao

10:37 a.m.

New subject: [U-Boot] [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao yao.yuan@freescale.com --- Changed in v2: Update the write value to 63b2_0042h; ---

arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 97ba6d5..79ae883 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -76,5 +76,15 @@ int arch_soc_init(void) SCFG_SNPCNFGCR_DBG_RD_WR | SCFG_SNPCNFGCR_EDMA_SNP);

+ /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20042); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 0527576..c584c9f 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -228,7 +228,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr;

-- 2.1.0.27.g96db324

Yuan Yao

10:37 a.m.

New subject: [U-Boot] [PATCH v2 5/5] move erratum a008336 and a008514 to soc specific file

As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao yao.yuan@freescale.com --- Changed in v2: Update the patch commit message. ---

arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++ drivers/ddr/fsl/fsl_ddr_gen4.c | 34 ------------------------------ 2 files changed, 37 insertions(+), 34 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..738b113 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -14,6 +14,41 @@ DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/* + * This erratum requires setting a value to eddrtqcr1 to + * optimal the DDR performance. + */ +static void erratum_a008336(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#endif +} + +/* + * This erratum requires a register write before being Memory + * controller 3 being enabled. + */ +static void erratum_a008514(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b20002); +#endif +#endif +} #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"

@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void) erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); + erratum_a008514(); + erratum_a008336(); }

#elif defined(CONFIG_LS1043A) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 1de7b72..2e5fe62 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 temp_sdram_cfg; u32 total_gb_size_per_controller; int timeout; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - u32 *eddrtqcr1; -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 u32 temp32, mr6; #endif @@ -66,36 +62,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; -#endif break; #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; -#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; -#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; -#endif break; #endif default: @@ -106,20 +86,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (step == 2) goto step2;

-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) - /* A008336 only applies to general DDR controllers */ - if ((ctrl_num == 0) || (ctrl_num == 1)) -#endif - ddr_out32(eddrtqcr1, 0x63b30002); -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) - /* A008514 only applies to DP-DDR controler */ - if (ctrl_num == 2) -#endif - ddr_out32(eddrtqcr1, 0x63b20002); -#endif if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor);

-- 2.1.0.27.g96db324

York Sun

6:22 p.m.

New subject: [U-Boot] [PATCH v2 5/5] move erratum a008336 and a008514 to soc specific file

On 12/04/2015 01:37 AM, Yuan Yao wrote:

...

As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao yao.yuan@freescale.com

Changed in v2: Update the patch commit message.

arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++ drivers/ddr/fsl/fsl_ddr_gen4.c | 34 ------------------------------ 2 files changed, 37 insertions(+), 34 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..738b113 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -14,6 +14,41 @@ DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/*

This erratum requires setting a value to eddrtqcr1 to

optimal the DDR performance.

*/

+static void erratum_a008336(void) +{

u32 *eddrtqcr1;

+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR

eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;

out_le32(eddrtqcr1, 0x63b30002);

+#endif +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR

eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;

out_le32(eddrtqcr1, 0x63b30002);

+#endif +#endif +}

+/*

This erratum requires a register write before being Memory

controller 3 being enabled.

*/

+static void erratum_a008514(void) +{

u32 *eddrtqcr1;

+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR

I believe this is a typo. It should be CONFIG_SYS_FSL_DCSR_DDR3_ADDR.

...

eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;

out_le32(eddrtqcr1, 0x63b20002);

+#endif +#endif +} #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"

@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void) erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203();

erratum_a008514();

erratum_a008336();

}

#elif defined(CONFIG_LS1043A)

York

Yao Yuan

5 Dec 5 Dec

7:49 a.m.

New subject: [U-Boot] [PATCH v2 5/5] move erratum a008336 and a008514 to soc specific file

On 12/05/2015 01:12 AM, York Sun wrote:

...

On 12/04/2015 01:37 AM, Yuan Yao wrote:

...
As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao yao.yuan@freescale.com

Changed in v2: Update the patch commit message.

arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37

+++++++++++++++++++++++++++++++++

...
drivers/ddr/fsl/fsl_ddr_gen4.c | 34 ------------------------------ 2 files changed, 37 insertions(+), 34 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..738b113 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -14,6 +14,41 @@ DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/*

This erratum requires setting a value to eddrtqcr1 to

optimal the DDR performance.

*/

+static void erratum_a008336(void) +{

u32 *eddrtqcr1;

+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 #ifdef +CONFIG_SYS_FSL_DCSR_DDR_ADDR

eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;

out_le32(eddrtqcr1, 0x63b30002);

+#endif +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR

eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;

out_le32(eddrtqcr1, 0x63b30002);

+#endif +#endif +}

+/*

This erratum requires a register write before being Memory

controller 3 being enabled.

*/

+static void erratum_a008514(void) +{

u32 *eddrtqcr1;

+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 #ifdef +CONFIG_SYS_FSL_DCSR_DDR2_ADDR

I believe this is a typo. It should be CONFIG_SYS_FSL_DCSR_DDR3_ADDR.

Thanks york, Yes, it's a typo. It should be CONFIG_SYS_FSL_DCSR_DDR3_ADDR. Sorry for the mistake. I will update it soon.

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Yao Yuan
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Yuan Yao