[U-Boot] [PATCH] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de --- drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
+ /* to ensure spi_calibration is run when SCLK frequency change */ + plat->max_hz = hz; + /* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) {
On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote:
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
- /* to ensure spi_calibration is run when SCLK frequency change */
- plat->max_hz = hz;
This looks like a hack, doesn't this change just subvert the condition below to enforce the calibration ?
/* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) {
Best regards, Marek Vasut
On Tue, 2015-09-01 at 11:01 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote:
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
- /* to ensure spi_calibration is run when SCLK frequency change */
- plat->max_hz = hz;
This looks like a hack, doesn't this change just subvert the condition below to enforce the calibration ?
Nope. I checked through debugger where plat->max_hz is initialized once with the value from device tree. When you use sf probe to change frequency, the value is not reflected to plat->max_hz. Hence the calibration is not run when frequency change. That lead to the sf probe fail when running at 80MHz or higher. Note the priv->qspi_calibrated_hz is updated after calibration succeed.
Thanks Chin Liang
/* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) {
Best regards, Marek Vasut
On Tue, 2015-09-01 at 04:13 -0500, Chin Liang See wrote:
On Tue, 2015-09-01 at 11:01 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote:
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
- /* to ensure spi_calibration is run when SCLK frequency change */
- plat->max_hz = hz;
This looks like a hack, doesn't this change just subvert the condition below to enforce the calibration ?
Nope. I checked through debugger where plat->max_hz is initialized once with the value from device tree. When you use sf probe to change frequency, the value is not reflected to plat->max_hz. Hence the calibration is not run when frequency change. That lead to the sf probe fail when running at 80MHz or higher. Note the priv->qspi_calibrated_hz is updated after calibration succeed.
Thanks Chin Liang
Here are the useful info
U-Boot 2015.10-rc2-06835-gf7d7156-dirty (Sep 01 2015 - 08:29:14 +0000)
CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: SOCFPGA DWMMC: 0 Using default environment
In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Error: ethernet@ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => sf probe 0 1000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 0000000f .... => sf probe 0 10000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 0000000f .... => sf probe 0 20000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 0000000d .... => sf probe 0 50000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 00000007 .... => sf probe 0 80000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 00000007 .... => sf probe 0 100000000 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB => md ff705010 1 ff705010: 00000007 ....
Thanks Chin Liang
/* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) {
Best regards, Marek Vasut
On Tuesday, September 01, 2015 at 11:13:38 AM, Chin Liang See wrote:
On Tue, 2015-09-01 at 11:01 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote:
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
- /* to ensure spi_calibration is run when SCLK frequency change */
- plat->max_hz = hz;
This looks like a hack, doesn't this change just subvert the condition below to enforce the calibration ?
Nope. I checked through debugger where plat->max_hz is initialized once with the value from device tree. When you use sf probe to change frequency, the value is not reflected to plat->max_hz. Hence the calibration is not run when frequency change. That lead to the sf probe fail when running at 80MHz or higher. Note the priv->qspi_calibrated_hz is updated after calibration succeed.
Isn't the purpose of ->max_hz to reflect the maximum frequency of the bus? I don't think this should thus ever be updated, in particular not by the user. I also think that setting ->max_hz once from DT is the correct behavior.
Best regards, Marek Vasut
On Tue, 2015-09-01 at 11:19 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 11:13:38 AM, Chin Liang See wrote:
On Tue, 2015-09-01 at 11:01 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote:
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
- /* to ensure spi_calibration is run when SCLK frequency change */
- plat->max_hz = hz;
This looks like a hack, doesn't this change just subvert the condition below to enforce the calibration ?
Nope. I checked through debugger where plat->max_hz is initialized once with the value from device tree. When you use sf probe to change frequency, the value is not reflected to plat->max_hz. Hence the calibration is not run when frequency change. That lead to the sf probe fail when running at 80MHz or higher. Note the priv->qspi_calibrated_hz is updated after calibration succeed.
Isn't the purpose of ->max_hz to reflect the maximum frequency of the bus? I don't think this should thus ever be updated, in particular not by the user. I also think that setting ->max_hz once from DT is the correct behavior.
Oh, in this case, there are more bug in the code. I saw there is mismatch of the usage of this variable. As example, the line "priv->qspi_calibrated_hz = plat->max_hz;" is wrong as it would be always static. Besides that, there is no check against the requested speed not to exceed the max_hz. Let me fix this all again.
Thanks Chin Liang
Best regards, Marek Vasut
On Tuesday, September 01, 2015 at 11:30:59 AM, Chin Liang See wrote:
On Tue, 2015-09-01 at 11:19 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 11:13:38 AM, Chin Liang See wrote:
On Tue, 2015-09-01 at 11:01 +0200, marex@denx.de wrote:
On Tuesday, September 01, 2015 at 10:46:47 AM, Chin Liang See wrote:
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_spi_write_speed(bus, hz);
- /* to ensure spi_calibration is run when SCLK frequency change
*/
- plat->max_hz = hz;
This looks like a hack, doesn't this change just subvert the condition below to enforce the calibration ?
Nope. I checked through debugger where plat->max_hz is initialized once with the value from device tree. When you use sf probe to change frequency, the value is not reflected to plat->max_hz. Hence the calibration is not run when frequency change. That lead to the sf probe fail when running at 80MHz or higher. Note the priv->qspi_calibrated_hz is updated after calibration succeed.
Isn't the purpose of ->max_hz to reflect the maximum frequency of the bus? I don't think this should thus ever be updated, in particular not by the user. I also think that setting ->max_hz once from DT is the correct behavior.
Oh, in this case, there are more bug in the code. I saw there is mismatch of the usage of this variable. As example, the line "priv->qspi_calibrated_hz = plat->max_hz;" is wrong as it would be always static. Besides that, there is no check against the requested speed not to exceed the max_hz. Let me fix this all again.
THanks
Best regards, Marek Vasut
participants (2)
-
Chin Liang See -
Marek Vasut