[U-Boot] [PATCH 0/3] mips: bmips: add BCM6362 SoC support

BCM6362 is a dual core BCM63xx SoC.
Álvaro Fernández Rojas (3): dm: cpu: bmips: add BCM6362 support MIPS: add support for Broadcom MIPS BCM6362 SoC family MIPS: add BMIPS Netgear DGND3700v2 board
arch/mips/dts/Makefile | 1 + arch/mips/dts/brcm,bcm6362.dtsi | 186 +++++++++++++++++++++ arch/mips/dts/netgear,dgnd3700v2.dts | 121 ++++++++++++++ arch/mips/mach-bmips/Kconfig | 24 +++ board/netgear/dgnd3700v2/Kconfig | 12 ++ board/netgear/dgnd3700v2/MAINTAINERS | 6 + board/netgear/dgnd3700v2/Makefile | 5 + board/netgear/dgnd3700v2/dgnd3700v2.c | 30 ++++ configs/netgear_dgnd3700v2_ram_defconfig | 46 +++++ drivers/cpu/bmips_cpu.c | 51 ++++++ include/configs/bmips_bcm6362.h | 25 +++ include/configs/netgear_dgnd3700v2.h | 16 ++ include/dt-bindings/clock/bcm6362-clock.h | 33 ++++ .../power-domain/bcm6362-power-domain.h | 25 +++ include/dt-bindings/reset/bcm6362-reset.h | 28 ++++ 15 files changed, 609 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm6362.dtsi create mode 100644 arch/mips/dts/netgear,dgnd3700v2.dts create mode 100644 board/netgear/dgnd3700v2/Kconfig create mode 100644 board/netgear/dgnd3700v2/MAINTAINERS create mode 100644 board/netgear/dgnd3700v2/Makefile create mode 100644 board/netgear/dgnd3700v2/dgnd3700v2.c create mode 100644 configs/netgear_dgnd3700v2_ram_defconfig create mode 100644 include/configs/bmips_bcm6362.h create mode 100644 include/configs/netgear_dgnd3700v2.h create mode 100644 include/dt-bindings/clock/bcm6362-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6362-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6362-reset.h

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- drivers/cpu/bmips_cpu.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index 4ad291a56e..6c612bacdc 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR; #define DMIPSPLLCFG_6358_N2_SHIFT 29 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
+#define REG_BCM6362_MISC_STRAPBUS 0x1814 +#define STRAPBUS_6362_FCVO_SHIFT 1 +#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) + #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0 #define DMIPSPLLCFG_6368_P1_SHIFT 0 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) @@ -194,6 +198,44 @@ static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) return (16 * 1000000 * n1 * n2) / m1; }
+static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int mips_pll_fcvo; + + mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS); + mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK) + >> STRAPBUS_6362_FCVO_SHIFT; + + switch (mips_pll_fcvo) { + case 0x03: + case 0x0b: + case 0x13: + case 0x1b: + return 240000000; + case 0x04: + case 0x0c: + case 0x14: + case 0x1c: + return 160000000; + case 0x05: + case 0x0e: + case 0x16: + case 0x1e: + case 0x1f: + return 400000000; + case 0x06: + return 440000000; + case 0x07: + case 0x17: + return 384000000; + case 0x15: + case 0x1d: + return 200000000; + default: + return 320000000; + } +} + static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv) { unsigned int tmp, p1, p2, ndiv, m1; @@ -289,6 +331,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { .get_cpu_count = bcm6358_get_cpu_count, };
+static const struct bmips_cpu_hw bmips_cpu_bcm6362 = { + .get_cpu_desc = bmips_short_cpu_desc, + .get_cpu_freq = bcm6362_get_cpu_freq, + .get_cpu_count = bcm6358_get_cpu_count, +}; + static const struct bmips_cpu_hw bmips_cpu_bcm6368 = { .get_cpu_desc = bmips_short_cpu_desc, .get_cpu_freq = bcm6368_get_cpu_freq, @@ -395,6 +443,9 @@ static const struct udevice_id bmips_cpu_ids[] = { .compatible = "brcm,bcm6358-cpu", .data = (ulong)&bmips_cpu_bcm6358, }, { + .compatible = "brcm,bcm6362-cpu", + .data = (ulong)&bmips_cpu_bcm6362, + }, { .compatible = "brcm,bcm6368-cpu", .data = (ulong)&bmips_cpu_bcm6368, }, {

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- arch/mips/dts/brcm,bcm6362.dtsi | 186 +++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 ++ include/configs/bmips_bcm6362.h | 25 +++ include/dt-bindings/clock/bcm6362-clock.h | 33 ++++ .../power-domain/bcm6362-power-domain.h | 25 +++ include/dt-bindings/reset/bcm6362-reset.h | 28 ++++ 6 files changed, 309 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm6362.dtsi create mode 100644 include/configs/bmips_bcm6362.h create mode 100644 include/dt-bindings/clock/bcm6362-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6362-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6362-reset.h
diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi new file mode 100644 index 0000000000..921fcd52c3 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm6362-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6362-power-domain.h> +#include <dt-bindings/reset/bcm6362-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6362"; + + aliases { + spi0 = &lsspi; + spi1 = &hsspi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_SPI>; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + + hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x864>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e4a0118368..2cc6a6a8d9 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -12,6 +12,7 @@ config SYS_SOC default "bcm6348" if SOC_BMIPS_BCM6348 default "bcm6358" if SOC_BMIPS_BCM6358 default "bcm6368" if SOC_BMIPS_BCM6368 + default "bcm6362" if SOC_BMIPS_BCM6362 default "bcm63268" if SOC_BMIPS_BCM63268
choice @@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368 help This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
+config SOC_BMIPS_BCM6362 + bool "BMIPS BCM6362 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6362 family including BCM6361 and BCM6362. + config SOC_BMIPS_BCM63268 bool "BMIPS BCM63268 family" select SUPPORTS_BIG_ENDIAN diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h new file mode 100644 index 0000000000..6ff0a33d49 --- /dev/null +++ b/include/configs/bmips_bcm6362.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6362_H +#define __CONFIG_BMIPS_BCM6362_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h new file mode 100644 index 0000000000..4fec0cf687 --- /dev/null +++ b/include/dt-bindings/clock/bcm6362-clock.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6362_H +#define __DT_BINDINGS_CLOCK_BCM6362_H + +#define BCM6362_CLK_GLESS 0 +#define BCM6362_CLK_ADSL_QPROC 1 +#define BCM6362_CLK_ADSL_AFE 2 +#define BCM6362_CLK_ADSL 3 +#define BCM6362_CLK_MIPS 4 +#define BCM6362_CLK_WLAN_OCP 5 +#define BCM6362_CLK_SWPKT_USB 7 +#define BCM6362_CLK_SWPKT_SAR 8 +#define BCM6362_CLK_SAR 9 +#define BCM6362_CLK_ROBOSW 10 +#define BCM6362_CLK_PCM 11 +#define BCM6362_CLK_USBD 12 +#define BCM6362_CLK_USBH 13 +#define BCM6362_CLK_IPSEC 14 +#define BCM6362_CLK_SPI 15 +#define BCM6362_CLK_HSSPI 16 +#define BCM6362_CLK_PCIE 17 +#define BCM6362_CLK_FAP 18 +#define BCM6362_CLK_PHYMIPS 19 +#define BCM6362_CLK_NAND 20 + +#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h new file mode 100644 index 0000000000..eafaae1457 --- /dev/null +++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H + +#define BCM6362_PWR_SAR 0 +#define BCM6362_PWR_IPSEC 1 +#define BCM6362_PWR_MIPS 2 +#define BCM6362_PWR_DECT 3 +#define BCM6362_PWR_USBH 4 +#define BCM6362_PWR_USBD 5 +#define BCM6362_PWR_ROBOSW 6 +#define BCM6362_PWR_PCM 7 +#define BCM6362_PWR_PERIPH 8 +#define BCM6362_PWR_ADSL_PHY 9 +#define BCM6362_PWR_GMII_PADS 10 +#define BCM6362_PWR_FAP 11 +#define BCM6362_PWR_PCIE 12 +#define BCM6362_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */ diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h new file mode 100644 index 0000000000..78c43ca482 --- /dev/null +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6362_H +#define __DT_BINDINGS_RESET_BCM6362_H + +#define BCM6362_RST_SPI 0 +#define BCM6362_RST_IPSEC 1 +#define BCM6362_RST_EPHY 2 +#define BCM6362_RST_SAR 3 +#define BCM6362_RST_ENETSW 4 +#define BCM6362_RST_USBD 5 +#define BCM6362_RST_USBH 6 +#define BCM6362_RST_PCM 7 +#define BCM6362_RST_PCIE_CORE 8 +#define BCM6362_RST_PCIE 9 +#define BCM6362_RST_PCIE_EXT 10 +#define BCM6362_RST_WLAN_SHIM 11 +#define BCM6362_RST_DDR_PHY 12 +#define BCM6362_RST_FAP 13 +#define BCM6362_RST_WLAN_UBUS 14 + +#endif /* __DT_BINDINGS_RESET_BCM6362_H */

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- arch/mips/dts/Makefile | 1 + arch/mips/dts/netgear,dgnd3700v2.dts | 121 +++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++ board/netgear/dgnd3700v2/Kconfig | 12 +++ board/netgear/dgnd3700v2/MAINTAINERS | 6 ++ board/netgear/dgnd3700v2/Makefile | 5 ++ board/netgear/dgnd3700v2/dgnd3700v2.c | 30 ++++++++ configs/netgear_dgnd3700v2_ram_defconfig | 46 ++++++++++++ include/configs/netgear_dgnd3700v2.h | 16 ++++ 9 files changed, 249 insertions(+) create mode 100644 arch/mips/dts/netgear,dgnd3700v2.dts create mode 100644 board/netgear/dgnd3700v2/Kconfig create mode 100644 board/netgear/dgnd3700v2/MAINTAINERS create mode 100644 board/netgear/dgnd3700v2/Makefile create mode 100644 board/netgear/dgnd3700v2/dgnd3700v2.c create mode 100644 configs/netgear_dgnd3700v2_ram_defconfig create mode 100644 include/configs/netgear_dgnd3700v2.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 840dbf170d..e80905cf3a 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts new file mode 100644 index 0000000000..2739f2035a --- /dev/null +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6362.dtsi" + +/ { + model = "Netgear DGND3700v2"; + compatible = "netgear,dgnd3700v2", "brcm,bcm6362"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "DGND3700v2:green:inet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_green { + label = "DGND3700v2:green:dsl"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + power_amber { + label = "DGND3700v2:red:power"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + brcm,serial-mux; + + led@8 { + reg = <8>; + label = "DGND3700v2:green:power"; + }; + + led@9 { + reg = <9>; + active-low; + label = "DGND3700v2:green:wps"; + }; + + led@10 { + reg = <10>; + active-low; + label = "DGND3700v2:green:usb1"; + }; + + led@11 { + reg = <11>; + active-low; + label = "DGND3700v2:green:usb2"; + }; + + led@12 { + reg = <12>; + active-low; + label = "DGND3700v2:amber:inet"; + }; + + led@13 { + reg = <13>; + active-low; + label = "DGND3700v2:green:ethernet"; + }; + + led@14 { + reg = <14>; + active-low; + label = "DGND3700v2:amber:dsl"; + }; + + led@16 { + reg = <16>; + active-low; + label = "DGND3700v2:amber:usb1"; + }; + + led@17 { + reg = <17>; + active-low; + label = "DGND3700v2:amber:usb2"; + }; + + led@18 { + reg = <18>; + active-low; + label = "DGND3700v2:amber:ethernet"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 2cc6a6a8d9..10900bf604 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -200,6 +200,17 @@ config BOARD_NETGEAR_CG3100D ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 (miniPCIe).
+config BOARD_NETGEAR_DGND3700V2 + bool "Netgear DGND3700v2" + depends on SOC_BMIPS_BCM6362 + select BMIPS_SUPPORTS_BOOT_RAM + help + Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and + 32 MB of flash (NAND). + Between its different peripherals there's a BCM53125 switch with 5 + ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a + BCM43228 (miniPCIe). + config BOARD_SAGEM_FAST1704 bool "Sagem F@ST1704" depends on SOC_BMIPS_BCM6338 @@ -247,6 +258,7 @@ source "board/comtrend/vr3032u/Kconfig" source "board/comtrend/wap5813n/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/netgear/cg3100d/Kconfig" +source "board/netgear/dgnd3700v2/Kconfig" source "board/sagem/f@st1704/Kconfig" source "board/sfr/nb4_ser/Kconfig"
diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig new file mode 100644 index 0000000000..11af188785 --- /dev/null +++ b/board/netgear/dgnd3700v2/Kconfig @@ -0,0 +1,12 @@ +if BOARD_NETGEAR_DGND3700V2 + +config SYS_BOARD + default "dgnd3700v2" + +config SYS_VENDOR + default "netgear" + +config SYS_CONFIG_NAME + default "netgear_dgnd3700v2" + +endif diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS new file mode 100644 index 0000000000..aaa51c177e --- /dev/null +++ b/board/netgear/dgnd3700v2/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR DGND3700V2 BOARD +M: Álvaro Fernández Rojas noltari@gmail.com +S: Maintained +F: board/netgear/dgnd3700v2/ +F: include/configs/netgear_dgnd3700v2.h +F: configs/netgear_dgnd3700v2_ram_defconfig diff --git a/board/netgear/dgnd3700v2/Makefile b/board/netgear/dgnd3700v2/Makefile new file mode 100644 index 0000000000..89fd6c89eb --- /dev/null +++ b/board/netgear/dgnd3700v2/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dgnd3700v2.o diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c new file mode 100644 index 0000000000..9e9f70c5b8 --- /dev/null +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#define GPIO_BASE_6362 0x10000080 + +#define GPIO_MODE_6362_REG 0x18 +#define GPIO_MODE_6362_SERIAL_LED_DATA BIT(2) +#define GPIO_MODE_6362_SERIAL_LED_CLK BIT(3) + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE); + u32 val; + + /* Enable Serial LEDs */ + val = readl_be(gpio_regs + GPIO_MODE_6362_REG); + val |= GPIO_MODE_6362_SERIAL_LED_DATA; + val |= GPIO_MODE_6362_SERIAL_LED_CLK; + writel_be(val, gpio_regs + GPIO_MODE_6362_REG); + + return 0; +} +#endif diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig new file mode 100644 index 0000000000..11ee28eab1 --- /dev/null +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -0,0 +1,46 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_BMIPS=y +CONFIG_SOC_BMIPS_BCM6362=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="DGND3700v2 # " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_BCM6345_GPIO=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_POWER_DOMAIN=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y +CONFIG_RESET_BCM6345=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h new file mode 100644 index 0000000000..0b68b4d344 --- /dev/null +++ b/include/configs/netgear_dgnd3700v2.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <configs/bmips_common.h> +#include <configs/bmips_bcm6362.h> + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP

On 26.01.2018 21:30, Álvaro Fernández Rojas wrote:
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com
arch/mips/dts/Makefile | 1 + arch/mips/dts/netgear,dgnd3700v2.dts | 121 +++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++ board/netgear/dgnd3700v2/Kconfig | 12 +++ board/netgear/dgnd3700v2/MAINTAINERS | 6 ++ board/netgear/dgnd3700v2/Makefile | 5 ++ board/netgear/dgnd3700v2/dgnd3700v2.c | 30 ++++++++ configs/netgear_dgnd3700v2_ram_defconfig | 46 ++++++++++++ include/configs/netgear_dgnd3700v2.h | 16 ++++ 9 files changed, 249 insertions(+) create mode 100644 arch/mips/dts/netgear,dgnd3700v2.dts create mode 100644 board/netgear/dgnd3700v2/Kconfig create mode 100644 board/netgear/dgnd3700v2/MAINTAINERS create mode 100644 board/netgear/dgnd3700v2/Makefile create mode 100644 board/netgear/dgnd3700v2/dgnd3700v2.c create mode 100644 configs/netgear_dgnd3700v2_ram_defconfig create mode 100644 include/configs/netgear_dgnd3700v2.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 840dbf170d..e80905cf3a 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts new file mode 100644 index 0000000000..2739f2035a --- /dev/null +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -0,0 +1,121 @@ +/*
- Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/;
+#include "brcm,bcm6362.dtsi"
+/ {
- model = "Netgear DGND3700v2";
- compatible = "netgear,dgnd3700v2", "brcm,bcm6362";
- aliases {
serial0 = &uart0;
- };
- chosen {
stdout-path = "serial0:115200n8";
- };
- gpio-leds {
compatible = "gpio-leds";
inet_green {
label = "DGND3700v2:green:inet";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
dsl_green {
label = "DGND3700v2:green:dsl";
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
power_amber {
label = "DGND3700v2:red:power";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
- };
+};
+&gpio0 {
- status = "okay";
+};
+&gpio1 {
- status = "okay";
+};
+&leds {
- status = "okay";
- brcm,serial-leds;
- brcm,serial-dat-low;
- brcm,serial-shift-inv;
- brcm,serial-mux;
- led@8 {
reg = <8>;
label = "DGND3700v2:green:power";
- };
- led@9 {
reg = <9>;
active-low;
label = "DGND3700v2:green:wps";
- };
- led@10 {
reg = <10>;
active-low;
label = "DGND3700v2:green:usb1";
- };
- led@11 {
reg = <11>;
active-low;
label = "DGND3700v2:green:usb2";
- };
- led@12 {
reg = <12>;
active-low;
label = "DGND3700v2:amber:inet";
- };
- led@13 {
reg = <13>;
active-low;
label = "DGND3700v2:green:ethernet";
- };
- led@14 {
reg = <14>;
active-low;
label = "DGND3700v2:amber:dsl";
- };
- led@16 {
reg = <16>;
active-low;
label = "DGND3700v2:amber:usb1";
- };
- led@17 {
reg = <17>;
active-low;
label = "DGND3700v2:amber:usb2";
- };
- led@18 {
reg = <18>;
active-low;
label = "DGND3700v2:amber:ethernet";
- };
+};
+&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
+}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 2cc6a6a8d9..10900bf604 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -200,6 +200,17 @@ config BOARD_NETGEAR_CG3100D ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 (miniPCIe).
+config BOARD_NETGEAR_DGND3700V2
- bool "Netgear DGND3700v2"
- depends on SOC_BMIPS_BCM6362
- select BMIPS_SUPPORTS_BOOT_RAM
- help
Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and
32 MB of flash (NAND).
Between its different peripherals there's a BCM53125 switch with 5
ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a
BCM43228 (miniPCIe).
config BOARD_SAGEM_FAST1704 bool "Sagem F@ST1704" depends on SOC_BMIPS_BCM6338 @@ -247,6 +258,7 @@ source "board/comtrend/vr3032u/Kconfig" source "board/comtrend/wap5813n/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/netgear/cg3100d/Kconfig" +source "board/netgear/dgnd3700v2/Kconfig" source "board/sagem/f@st1704/Kconfig" source "board/sfr/nb4_ser/Kconfig"
diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig new file mode 100644 index 0000000000..11af188785 --- /dev/null +++ b/board/netgear/dgnd3700v2/Kconfig @@ -0,0 +1,12 @@ +if BOARD_NETGEAR_DGND3700V2
+config SYS_BOARD
- default "dgnd3700v2"
+config SYS_VENDOR
- default "netgear"
+config SYS_CONFIG_NAME
- default "netgear_dgnd3700v2"
+endif diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS new file mode 100644 index 0000000000..aaa51c177e --- /dev/null +++ b/board/netgear/dgnd3700v2/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR DGND3700V2 BOARD +M: Álvaro Fernández Rojas noltari@gmail.com +S: Maintained +F: board/netgear/dgnd3700v2/ +F: include/configs/netgear_dgnd3700v2.h +F: configs/netgear_dgnd3700v2_ram_defconfig diff --git a/board/netgear/dgnd3700v2/Makefile b/board/netgear/dgnd3700v2/Makefile new file mode 100644 index 0000000000..89fd6c89eb --- /dev/null +++ b/board/netgear/dgnd3700v2/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += dgnd3700v2.o diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c new file mode 100644 index 0000000000..9e9f70c5b8 --- /dev/null +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -0,0 +1,30 @@ +/*
- Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h>
+#define GPIO_BASE_6362 0x10000080
+#define GPIO_MODE_6362_REG 0x18 +#define GPIO_MODE_6362_SERIAL_LED_DATA BIT(2) +#define GPIO_MODE_6362_SERIAL_LED_CLK BIT(3)
+#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{
- void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE);
- u32 val;
- /* Enable Serial LEDs */
- val = readl_be(gpio_regs + GPIO_MODE_6362_REG);
- val |= GPIO_MODE_6362_SERIAL_LED_DATA;
- val |= GPIO_MODE_6362_SERIAL_LED_CLK;
- writel_be(val, gpio_regs + GPIO_MODE_6362_REG);
setbits_be32() ?
- return 0;
+} +#endif diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig new file mode 100644 index 0000000000..11ee28eab1 --- /dev/null +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -0,0 +1,46 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_BMIPS=y +CONFIG_SOC_BMIPS_BCM6362=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="DGND3700v2 # " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_BCM6345_GPIO=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_POWER_DOMAIN=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y +CONFIG_RESET_BCM6345=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h new file mode 100644 index 0000000000..0b68b4d344 --- /dev/null +++ b/include/configs/netgear_dgnd3700v2.h @@ -0,0 +1,16 @@ +/*
- Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <configs/bmips_common.h> +#include <configs/bmips_bcm6362.h>
+#define CONFIG_REMAKE_ELF
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP

BCM6362 is a dual core BCM63xx SoC.
v2: Introduce changes suggested by Daniel Schwierzeck: - Use setbits_be32()
Álvaro Fernández Rojas (3): dm: cpu: bmips: add BCM6362 support MIPS: add support for Broadcom MIPS BCM6362 SoC family MIPS: add BMIPS Netgear DGND3700v2 board
arch/mips/dts/Makefile | 1 + arch/mips/dts/brcm,bcm6362.dtsi | 186 +++++++++++++++++++++ arch/mips/dts/netgear,dgnd3700v2.dts | 121 ++++++++++++++ arch/mips/mach-bmips/Kconfig | 24 +++ board/netgear/dgnd3700v2/Kconfig | 12 ++ board/netgear/dgnd3700v2/MAINTAINERS | 6 + board/netgear/dgnd3700v2/Makefile | 5 + board/netgear/dgnd3700v2/dgnd3700v2.c | 28 ++++ configs/netgear_dgnd3700v2_ram_defconfig | 46 +++++ drivers/cpu/bmips_cpu.c | 51 ++++++ include/configs/bmips_bcm6362.h | 25 +++ include/configs/netgear_dgnd3700v2.h | 16 ++ include/dt-bindings/clock/bcm6362-clock.h | 33 ++++ .../power-domain/bcm6362-power-domain.h | 25 +++ include/dt-bindings/reset/bcm6362-reset.h | 28 ++++ 15 files changed, 607 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm6362.dtsi create mode 100644 arch/mips/dts/netgear,dgnd3700v2.dts create mode 100644 board/netgear/dgnd3700v2/Kconfig create mode 100644 board/netgear/dgnd3700v2/MAINTAINERS create mode 100644 board/netgear/dgnd3700v2/Makefile create mode 100644 board/netgear/dgnd3700v2/dgnd3700v2.c create mode 100644 configs/netgear_dgnd3700v2_ram_defconfig create mode 100644 include/configs/bmips_bcm6362.h create mode 100644 include/configs/netgear_dgnd3700v2.h create mode 100644 include/dt-bindings/clock/bcm6362-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6362-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6362-reset.h

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: no changes
drivers/cpu/bmips_cpu.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index 4ad291a56e..6c612bacdc 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR; #define DMIPSPLLCFG_6358_N2_SHIFT 29 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
+#define REG_BCM6362_MISC_STRAPBUS 0x1814 +#define STRAPBUS_6362_FCVO_SHIFT 1 +#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) + #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0 #define DMIPSPLLCFG_6368_P1_SHIFT 0 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) @@ -194,6 +198,44 @@ static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) return (16 * 1000000 * n1 * n2) / m1; }
+static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int mips_pll_fcvo; + + mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS); + mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK) + >> STRAPBUS_6362_FCVO_SHIFT; + + switch (mips_pll_fcvo) { + case 0x03: + case 0x0b: + case 0x13: + case 0x1b: + return 240000000; + case 0x04: + case 0x0c: + case 0x14: + case 0x1c: + return 160000000; + case 0x05: + case 0x0e: + case 0x16: + case 0x1e: + case 0x1f: + return 400000000; + case 0x06: + return 440000000; + case 0x07: + case 0x17: + return 384000000; + case 0x15: + case 0x1d: + return 200000000; + default: + return 320000000; + } +} + static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv) { unsigned int tmp, p1, p2, ndiv, m1; @@ -289,6 +331,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { .get_cpu_count = bcm6358_get_cpu_count, };
+static const struct bmips_cpu_hw bmips_cpu_bcm6362 = { + .get_cpu_desc = bmips_short_cpu_desc, + .get_cpu_freq = bcm6362_get_cpu_freq, + .get_cpu_count = bcm6358_get_cpu_count, +}; + static const struct bmips_cpu_hw bmips_cpu_bcm6368 = { .get_cpu_desc = bmips_short_cpu_desc, .get_cpu_freq = bcm6368_get_cpu_freq, @@ -395,6 +443,9 @@ static const struct udevice_id bmips_cpu_ids[] = { .compatible = "brcm,bcm6358-cpu", .data = (ulong)&bmips_cpu_bcm6358, }, { + .compatible = "brcm,bcm6362-cpu", + .data = (ulong)&bmips_cpu_bcm6362, + }, { .compatible = "brcm,bcm6368-cpu", .data = (ulong)&bmips_cpu_bcm6368, }, {

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: no changes
arch/mips/dts/brcm,bcm6362.dtsi | 186 +++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 ++ include/configs/bmips_bcm6362.h | 25 +++ include/dt-bindings/clock/bcm6362-clock.h | 33 ++++ .../power-domain/bcm6362-power-domain.h | 25 +++ include/dt-bindings/reset/bcm6362-reset.h | 28 ++++ 6 files changed, 309 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm6362.dtsi create mode 100644 include/configs/bmips_bcm6362.h create mode 100644 include/dt-bindings/clock/bcm6362-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6362-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6362-reset.h
diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi new file mode 100644 index 0000000000..921fcd52c3 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm6362-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6362-power-domain.h> +#include <dt-bindings/reset/bcm6362-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6362"; + + aliases { + spi0 = &lsspi; + spi1 = &hsspi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_SPI>; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + + hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x864>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e4a0118368..2cc6a6a8d9 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -12,6 +12,7 @@ config SYS_SOC default "bcm6348" if SOC_BMIPS_BCM6348 default "bcm6358" if SOC_BMIPS_BCM6358 default "bcm6368" if SOC_BMIPS_BCM6368 + default "bcm6362" if SOC_BMIPS_BCM6362 default "bcm63268" if SOC_BMIPS_BCM63268
choice @@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368 help This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
+config SOC_BMIPS_BCM6362 + bool "BMIPS BCM6362 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6362 family including BCM6361 and BCM6362. + config SOC_BMIPS_BCM63268 bool "BMIPS BCM63268 family" select SUPPORTS_BIG_ENDIAN diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h new file mode 100644 index 0000000000..6ff0a33d49 --- /dev/null +++ b/include/configs/bmips_bcm6362.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6362_H +#define __CONFIG_BMIPS_BCM6362_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h new file mode 100644 index 0000000000..4fec0cf687 --- /dev/null +++ b/include/dt-bindings/clock/bcm6362-clock.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6362_H +#define __DT_BINDINGS_CLOCK_BCM6362_H + +#define BCM6362_CLK_GLESS 0 +#define BCM6362_CLK_ADSL_QPROC 1 +#define BCM6362_CLK_ADSL_AFE 2 +#define BCM6362_CLK_ADSL 3 +#define BCM6362_CLK_MIPS 4 +#define BCM6362_CLK_WLAN_OCP 5 +#define BCM6362_CLK_SWPKT_USB 7 +#define BCM6362_CLK_SWPKT_SAR 8 +#define BCM6362_CLK_SAR 9 +#define BCM6362_CLK_ROBOSW 10 +#define BCM6362_CLK_PCM 11 +#define BCM6362_CLK_USBD 12 +#define BCM6362_CLK_USBH 13 +#define BCM6362_CLK_IPSEC 14 +#define BCM6362_CLK_SPI 15 +#define BCM6362_CLK_HSSPI 16 +#define BCM6362_CLK_PCIE 17 +#define BCM6362_CLK_FAP 18 +#define BCM6362_CLK_PHYMIPS 19 +#define BCM6362_CLK_NAND 20 + +#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h new file mode 100644 index 0000000000..eafaae1457 --- /dev/null +++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H + +#define BCM6362_PWR_SAR 0 +#define BCM6362_PWR_IPSEC 1 +#define BCM6362_PWR_MIPS 2 +#define BCM6362_PWR_DECT 3 +#define BCM6362_PWR_USBH 4 +#define BCM6362_PWR_USBD 5 +#define BCM6362_PWR_ROBOSW 6 +#define BCM6362_PWR_PCM 7 +#define BCM6362_PWR_PERIPH 8 +#define BCM6362_PWR_ADSL_PHY 9 +#define BCM6362_PWR_GMII_PADS 10 +#define BCM6362_PWR_FAP 11 +#define BCM6362_PWR_PCIE 12 +#define BCM6362_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */ diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h new file mode 100644 index 0000000000..78c43ca482 --- /dev/null +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6362_H +#define __DT_BINDINGS_RESET_BCM6362_H + +#define BCM6362_RST_SPI 0 +#define BCM6362_RST_IPSEC 1 +#define BCM6362_RST_EPHY 2 +#define BCM6362_RST_SAR 3 +#define BCM6362_RST_ENETSW 4 +#define BCM6362_RST_USBD 5 +#define BCM6362_RST_USBH 6 +#define BCM6362_RST_PCM 7 +#define BCM6362_RST_PCIE_CORE 8 +#define BCM6362_RST_PCIE 9 +#define BCM6362_RST_PCIE_EXT 10 +#define BCM6362_RST_WLAN_SHIM 11 +#define BCM6362_RST_DDR_PHY 12 +#define BCM6362_RST_FAP 13 +#define BCM6362_RST_WLAN_UBUS 14 + +#endif /* __DT_BINDINGS_RESET_BCM6362_H */

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: Introduce changes suggested by Daniel Schwierzeck: - Use setbits_be32()
arch/mips/dts/Makefile | 1 + arch/mips/dts/netgear,dgnd3700v2.dts | 121 +++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++ board/netgear/dgnd3700v2/Kconfig | 12 +++ board/netgear/dgnd3700v2/MAINTAINERS | 6 ++ board/netgear/dgnd3700v2/Makefile | 5 ++ board/netgear/dgnd3700v2/dgnd3700v2.c | 28 +++++++ configs/netgear_dgnd3700v2_ram_defconfig | 46 ++++++++++++ include/configs/netgear_dgnd3700v2.h | 16 ++++ 9 files changed, 247 insertions(+) create mode 100644 arch/mips/dts/netgear,dgnd3700v2.dts create mode 100644 board/netgear/dgnd3700v2/Kconfig create mode 100644 board/netgear/dgnd3700v2/MAINTAINERS create mode 100644 board/netgear/dgnd3700v2/Makefile create mode 100644 board/netgear/dgnd3700v2/dgnd3700v2.c create mode 100644 configs/netgear_dgnd3700v2_ram_defconfig create mode 100644 include/configs/netgear_dgnd3700v2.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 840dbf170d..e80905cf3a 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts new file mode 100644 index 0000000000..2739f2035a --- /dev/null +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6362.dtsi" + +/ { + model = "Netgear DGND3700v2"; + compatible = "netgear,dgnd3700v2", "brcm,bcm6362"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "DGND3700v2:green:inet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_green { + label = "DGND3700v2:green:dsl"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + power_amber { + label = "DGND3700v2:red:power"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + brcm,serial-mux; + + led@8 { + reg = <8>; + label = "DGND3700v2:green:power"; + }; + + led@9 { + reg = <9>; + active-low; + label = "DGND3700v2:green:wps"; + }; + + led@10 { + reg = <10>; + active-low; + label = "DGND3700v2:green:usb1"; + }; + + led@11 { + reg = <11>; + active-low; + label = "DGND3700v2:green:usb2"; + }; + + led@12 { + reg = <12>; + active-low; + label = "DGND3700v2:amber:inet"; + }; + + led@13 { + reg = <13>; + active-low; + label = "DGND3700v2:green:ethernet"; + }; + + led@14 { + reg = <14>; + active-low; + label = "DGND3700v2:amber:dsl"; + }; + + led@16 { + reg = <16>; + active-low; + label = "DGND3700v2:amber:usb1"; + }; + + led@17 { + reg = <17>; + active-low; + label = "DGND3700v2:amber:usb2"; + }; + + led@18 { + reg = <18>; + active-low; + label = "DGND3700v2:amber:ethernet"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 2cc6a6a8d9..10900bf604 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -200,6 +200,17 @@ config BOARD_NETGEAR_CG3100D ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 (miniPCIe).
+config BOARD_NETGEAR_DGND3700V2 + bool "Netgear DGND3700v2" + depends on SOC_BMIPS_BCM6362 + select BMIPS_SUPPORTS_BOOT_RAM + help + Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and + 32 MB of flash (NAND). + Between its different peripherals there's a BCM53125 switch with 5 + ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a + BCM43228 (miniPCIe). + config BOARD_SAGEM_FAST1704 bool "Sagem F@ST1704" depends on SOC_BMIPS_BCM6338 @@ -247,6 +258,7 @@ source "board/comtrend/vr3032u/Kconfig" source "board/comtrend/wap5813n/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/netgear/cg3100d/Kconfig" +source "board/netgear/dgnd3700v2/Kconfig" source "board/sagem/f@st1704/Kconfig" source "board/sfr/nb4_ser/Kconfig"
diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig new file mode 100644 index 0000000000..11af188785 --- /dev/null +++ b/board/netgear/dgnd3700v2/Kconfig @@ -0,0 +1,12 @@ +if BOARD_NETGEAR_DGND3700V2 + +config SYS_BOARD + default "dgnd3700v2" + +config SYS_VENDOR + default "netgear" + +config SYS_CONFIG_NAME + default "netgear_dgnd3700v2" + +endif diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS new file mode 100644 index 0000000000..aaa51c177e --- /dev/null +++ b/board/netgear/dgnd3700v2/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR DGND3700V2 BOARD +M: Álvaro Fernández Rojas noltari@gmail.com +S: Maintained +F: board/netgear/dgnd3700v2/ +F: include/configs/netgear_dgnd3700v2.h +F: configs/netgear_dgnd3700v2_ram_defconfig diff --git a/board/netgear/dgnd3700v2/Makefile b/board/netgear/dgnd3700v2/Makefile new file mode 100644 index 0000000000..89fd6c89eb --- /dev/null +++ b/board/netgear/dgnd3700v2/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dgnd3700v2.o diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c new file mode 100644 index 0000000000..81a74c98f3 --- /dev/null +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#define GPIO_BASE_6362 0x10000080 + +#define GPIO_MODE_6362_REG 0x18 +#define GPIO_MODE_6362_SERIAL_LED_DATA BIT(2) +#define GPIO_MODE_6362_SERIAL_LED_CLK BIT(3) + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE); + + /* Enable Serial LEDs */ + setbits_be32(gpio_regs + GPIO_MODE_6362_REG, + GPIO_MODE_6362_SERIAL_LED_DATA | + GPIO_MODE_6362_SERIAL_LED_CLK); + + return 0; +} +#endif diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig new file mode 100644 index 0000000000..11ee28eab1 --- /dev/null +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -0,0 +1,46 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_BMIPS=y +CONFIG_SOC_BMIPS_BCM6362=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="DGND3700v2 # " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_BCM6345_GPIO=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_POWER_DOMAIN=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y +CONFIG_RESET_BCM6345=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h new file mode 100644 index 0000000000..0b68b4d344 --- /dev/null +++ b/include/configs/netgear_dgnd3700v2.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <configs/bmips_common.h> +#include <configs/bmips_bcm6362.h> + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP

On 26.01.2018 21:30, Álvaro Fernández Rojas wrote:
BCM6362 is a dual core BCM63xx SoC.
Álvaro Fernández Rojas (3): dm: cpu: bmips: add BCM6362 support MIPS: add support for Broadcom MIPS BCM6362 SoC family MIPS: add BMIPS Netgear DGND3700v2 board
arch/mips/dts/Makefile | 1 + arch/mips/dts/brcm,bcm6362.dtsi | 186 +++++++++++++++++++++ arch/mips/dts/netgear,dgnd3700v2.dts | 121 ++++++++++++++ arch/mips/mach-bmips/Kconfig | 24 +++ board/netgear/dgnd3700v2/Kconfig | 12 ++ board/netgear/dgnd3700v2/MAINTAINERS | 6 + board/netgear/dgnd3700v2/Makefile | 5 + board/netgear/dgnd3700v2/dgnd3700v2.c | 30 ++++ configs/netgear_dgnd3700v2_ram_defconfig | 46 +++++ drivers/cpu/bmips_cpu.c | 51 ++++++ include/configs/bmips_bcm6362.h | 25 +++ include/configs/netgear_dgnd3700v2.h | 16 ++ include/dt-bindings/clock/bcm6362-clock.h | 33 ++++ .../power-domain/bcm6362-power-domain.h | 25 +++ include/dt-bindings/reset/bcm6362-reset.h | 28 ++++ 15 files changed, 609 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm6362.dtsi create mode 100644 arch/mips/dts/netgear,dgnd3700v2.dts create mode 100644 board/netgear/dgnd3700v2/Kconfig create mode 100644 board/netgear/dgnd3700v2/MAINTAINERS create mode 100644 board/netgear/dgnd3700v2/Makefile create mode 100644 board/netgear/dgnd3700v2/dgnd3700v2.c create mode 100644 configs/netgear_dgnd3700v2_ram_defconfig create mode 100644 include/configs/bmips_bcm6362.h create mode 100644 include/configs/netgear_dgnd3700v2.h create mode 100644 include/dt-bindings/clock/bcm6362-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6362-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6362-reset.h
applied to u-boot-mips/next, thanks.
participants (2)
-
Daniel Schwierzeck
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Álvaro Fernández Rojas