[PATCHv3 00/13] powerpc: covert p1010, p1020 and p2020 RDB board to DM_ETH
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
This patch set depends on: https://patchwork.ozlabs.org/project/uboot/patch/20200503185227.28731-2-olte...
Hou Zhiqiang (15): net: fsl_mdio: Change to use virtual address net: fsl_mdio: Correct the MII management register block address net: tsec: convert to use DM_MDIO when DM_ETH enabled net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() configs: p1_p2_rdb: Add the default address of vsc7385 firmware dts: powerpc: p1020rdb: Add eTSEC DT nodes powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled configs: P1020RDB: Enable DM_ETH config dts: powerpc: p1010rdb: Add eTSEC DT nodes powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH configs: P1010RDB: Enable DM_ETH config dts: powerpc: p2020rdb: Add eTSEC DT nodes configs: P2020RDB: Enable DM_ETH config
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi | 62 +++++++++++++++++++ arch/powerpc/dts/p1010si-post.dtsi | 25 ++++++++ arch/powerpc/dts/p1020-post.dtsi | 16 +++++ arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 ++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 57 +++++++++++++++++ arch/powerpc/dts/p2020-post.dtsi | 10 +++ arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 59 ++++++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-1.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-2.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-3.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-timer-0.dtsi | 13 ++++ arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++ board/freescale/p1010rdb/p1010rdb.c | 2 + board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 37 ++++++----- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig | 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig | 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig | 3 + configs/P1020RDB-PC_SDCARD_defconfig | 3 + configs/P1020RDB-PC_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig | 3 + configs/P1020RDB-PD_SDCARD_defconfig | 3 + configs/P1020RDB-PD_SPIFLASH_defconfig | 3 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig | 3 + configs/P2020RDB-PC_SDCARD_defconfig | 3 + configs/P2020RDB-PC_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_defconfig | 3 + doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/fsl_mdio.c | 28 +++++++-- drivers/net/tsec.c | 62 ++++++++----------- include/configs/p1_p2_rdb_pc.h | 2 + include/fsl_mdio.h | 4 ++ include/tsec.h | 4 ++ 69 files changed, 744 insertions(+), 59 deletions(-) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Use virtual address to access the MII block registers instead of physical address.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - New patch.
drivers/net/fsl_mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 43040d4c3f..e52daa214d 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev) printf("dev_get_priv(dev %p) = NULL\n", dev); return -1; } - priv->regs = (void *)(uintptr_t)dev_read_addr(dev); + priv->regs = dev_remap_addr(dev); debug("%s priv %p @ regs %p, pdata %p\n", __func__, priv, priv->regs, pdata);
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Use virtual address to access the MII block registers instead of physical address.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- New patch.
drivers/net/fsl_mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 43040d4c3f..e52daa214d 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev) printf("dev_get_priv(dev %p) = NULL\n", dev); return -1; }
priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev); debug("%s priv %p @ regs %p, pdata %p\n", __func__, priv, priv->regs, pdata);-- 2.25.1
Hi Vladimir,
Thanks a lot for your review!
Regards, Zhiqiang
-----Original Message----- From: Vladimir Oltean olteanv@gmail.com Sent: 2020年6月13日 4:29 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 01/15] net: fsl_mdio: Change to use virtual address
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Use virtual address to access the MII block registers instead of physical address.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- New patch.
drivers/net/fsl_mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 43040d4c3f..e52daa214d 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev) printf("dev_get_priv(dev %p) = NULL\n", dev); return -1; }
priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev); debug("%s priv %p @ regs %p, pdata %p\n", __func__, priv, priv->regs, pdata);-- 2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The MII management register block offset is different between gianfar and etsec2 compatible devices, this patch is to fix this issue by adding driver data for different compatible string.
Fixes: Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - New patch.
drivers/net/fsl_mdio.c | 28 ++++++++++++++++++++++------ include/fsl_mdio.h | 4 ++++ 2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index e52daa214d..5b615d50f6 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -11,6 +11,7 @@ #include <fsl_mdio.h> #include <asm/io.h> #include <linux/errno.h> +#include <tsec.h>
#ifdef CONFIG_DM_MDIO struct tsec_mdio_priv { @@ -190,17 +191,30 @@ static const struct mdio_ops tsec_mdio_ops = { .reset = tsec_mdio_reset, };
+static struct fsl_pq_mdio_data etsec2_data = { + .mdio_regs_off = TSEC_MDIO_REGS_OFFSET, +}; + +static struct fsl_pq_mdio_data gianfar_data = { + .mdio_regs_off = 0x0, +}; + +static struct fsl_pq_mdio_data fman_data = { + .mdio_regs_off = 0x0, +}; + static const struct udevice_id tsec_mdio_ids[] = { - { .compatible = "fsl,gianfar-tbi" }, - { .compatible = "fsl,gianfar-mdio" }, - { .compatible = "fsl,etsec2-tbi" }, - { .compatible = "fsl,etsec2-mdio" }, - { .compatible = "fsl,fman-mdio" }, + { .compatible = "fsl,gianfar-tbi", .data = (ulong)&gianfar_data }, + { .compatible = "fsl,gianfar-mdio", .data = (ulong)&gianfar_data }, + { .compatible = "fsl,etsec2-tbi", .data = (ulong)&etsec2_data }, + { .compatible = "fsl,etsec2-mdio", .data = (ulong)&etsec2_data }, + { .compatible = "fsl,fman-mdio", .data = (ulong)&fman_data }, {} };
static int tsec_mdio_probe(struct udevice *dev) { + struct fsl_pq_mdio_data *data; struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL; struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) : NULL; @@ -213,7 +227,9 @@ static int tsec_mdio_probe(struct udevice *dev) printf("dev_get_priv(dev %p) = NULL\n", dev); return -1; } - priv->regs = dev_remap_addr(dev); + + data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev); + priv->regs = dev_remap_addr(dev) + data->mdio_regs_off; debug("%s priv %p @ regs %p, pdata %p\n", __func__, priv, priv->regs, pdata);
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index 8857d50910..cd612c0954 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -55,6 +55,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, int regnum); int memac_mdio_reset(struct mii_dev *bus);
+struct fsl_pq_mdio_data { + u32 mdio_regs_off; +}; + struct fsl_pq_mdio_info { struct tsec_mii_mng __iomem *regs; char *name;
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise.
Signed-off-by: Vladimir Oltean vladimir.oltean@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Draw from the tsec.c part of the Vladimir's patch below and do some slightly tweaking: https://patchwork.ozlabs.org/project/uboot/patch/20200503185227.28731-4-olte...
drivers/net/tsec.c | 46 +++++++++++++--------------------------------- 1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3d75acb6b4..cb3e56d439 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -18,6 +18,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> +#include <miiphy.h> #include <asm/processor.h> #include <asm/io.h>
@@ -681,8 +682,15 @@ static int init_phy(struct tsec_private *priv) if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv);
+#ifdef CONFIG_DM_ETH + if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link"))) + phydev = phy_connect(NULL, 0, priv->dev, priv->interface); + else + phydev = dm_eth_phy_connect(priv->dev); +#else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface); +#endif if (!phydev) return 0;
@@ -787,14 +795,17 @@ int tsec_standard_init(bd_t *bis) return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); } #else /* CONFIG_DM_ETH */ + +#ifndef CONFIG_DM_MDIO +#error "TSEC with DM_ETH also requires DM_MDIO" +#endif + int tsec_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct tsec_private *priv = dev_get_priv(dev); - struct tsec_mii_mng __iomem *ext_phyregs_mii; struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; - struct fsl_pq_mdio_info mdio_info; const char *phy_mode; fdt_addr_t reg; ofnode parent; @@ -803,31 +814,6 @@ int tsec_probe(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, - &phandle_args)) { - printf("phy-handle does not exist under tsec %s\n", dev->name); - return -ENOENT; - } else { - int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); - - priv->phyaddr = reg; - } - - parent = ofnode_get_parent(phandle_args.node); - if (!ofnode_valid(parent)) { - printf("No parent node for PHY?\n"); - return -ENOENT; - } - - reg = ofnode_get_addr_index(parent, 0); - if (reg == FDT_ADDR_T_NONE) { - printf("No 'reg' property of MII for external PHY\n"); - return -ENOENT; - } - - ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0, - MAP_NOCACHE); - ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, &phandle_args); if (ret == 0) { @@ -865,12 +851,6 @@ int tsec_probe(struct udevice *dev) if (priv->interface == PHY_INTERFACE_MODE_SGMII) priv->flags |= TSEC_SGMII;
- mdio_info.regs = ext_phyregs_mii; - mdio_info.name = (char *)dev->name; - ret = fsl_pq_mdio_init(NULL, &mdio_info); - if (ret) - return ret; - /* Reset the MAC */ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise.
Signed-off-by: Vladimir Oltean vladimir.oltean@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- Draw from the tsec.c part of the Vladimir's patch below and do some slightly tweaking: https://patchwork.ozlabs.org/project/uboot/patch/20200503185227.28731-4-olte...
drivers/net/tsec.c | 46 +++++++++++++--------------------------------- 1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3d75acb6b4..cb3e56d439 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -18,6 +18,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> +#include <miiphy.h> #include <asm/processor.h> #include <asm/io.h>
@@ -681,8 +682,15 @@ static int init_phy(struct tsec_private *priv) if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv);
+#ifdef CONFIG_DM_ETH
if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link")))phydev = phy_connect(NULL, 0, priv->dev, priv->interface);elsephydev = dm_eth_phy_connect(priv->dev);+#else
You said it's better to split the fixed-link functionality into a separate patch, but then you didn't :)
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface);+#endif if (!phydev) return 0;
@@ -787,14 +795,17 @@ int tsec_standard_init(bd_t *bis) return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); } #else /* CONFIG_DM_ETH */
+#ifndef CONFIG_DM_MDIO +#error "TSEC with DM_ETH also requires DM_MDIO" +#endif
int tsec_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct tsec_private *priv = dev_get_priv(dev);
struct tsec_mii_mng __iomem *ext_phyregs_mii; struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;struct fsl_pq_mdio_info mdio_info; const char *phy_mode; fdt_addr_t reg; ofnode parent;@@ -803,31 +814,6 @@ int tsec_probe(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,&phandle_args)) {printf("phy-handle does not exist under tsec %s\n", dev->name);return -ENOENT;} else {int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);priv->phyaddr = reg;}parent = ofnode_get_parent(phandle_args.node);if (!ofnode_valid(parent)) {printf("No parent node for PHY?\n");return -ENOENT;}reg = ofnode_get_addr_index(parent, 0);if (reg == FDT_ADDR_T_NONE) {printf("No 'reg' property of MII for external PHY\n");return -ENOENT;}ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,MAP_NOCACHE);ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, &phandle_args); if (ret == 0) {@@ -865,12 +851,6 @@ int tsec_probe(struct udevice *dev) if (priv->interface == PHY_INTERFACE_MODE_SGMII) priv->flags |= TSEC_SGMII;
mdio_info.regs = ext_phyregs_mii;mdio_info.name = (char *)dev->name;ret = fsl_pq_mdio_init(NULL, &mdio_info);if (ret)return ret;/* Reset the MAC */ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); udelay(2); /* Soft Reset must be asserted for 3 TX clocks */-- 2.25.1
Hi Vladimir,
Thanks a lot for your comments!
-----Original Message----- From: Vladimir Oltean [mailto:olteanv@gmail.com] Sent: 2020年6月13日 4:31 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com; Vladimir Oltean vladimir.oltean@nxp.com Subject: Re: [PATCHv3 03/15] net: tsec: convert to use DM_MDIO when DM_ETH enabled
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise.
Signed-off-by: Vladimir Oltean vladimir.oltean@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- Draw from the tsec.c part of the Vladimir's patch below and do some slightly tweaking:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
hwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20200503185227.28731- 4-ol
teanv%40gmail.com%2F&data=02%7C01%7CZhiqiang.Hou%40nxp.com %7Ce4ec9
e0d5ef84ddf730408d80f0f9963%7C686ea1d3bc2b4c6fa92cd99c5c301635%7 C0%7C0
%7C637275906955031325&sdata=muGA37v8K5glLrZJD2u63%2FFSmJ
eNeRVCX8u%
2F400xgQA%3D&reserved=0
drivers/net/tsec.c | 46 +++++++++++++--------------------------------- 1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3d75acb6b4..cb3e56d439 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -18,6 +18,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> +#include <miiphy.h> #include <asm/processor.h> #include <asm/io.h>
@@ -681,8 +682,15 @@ static int init_phy(struct tsec_private *priv) if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv);
+#ifdef CONFIG_DM_ETH
if (ofnode_valid(ofnode_find_subnode(priv->dev->node,"fixed-link")))
phydev = phy_connect(NULL, 0, priv->dev,priv->interface);
elsephydev = dm_eth_phy_connect(priv->dev); #elseYou said it's better to split the fixed-link functionality into a separate patch, but then you didn't :)
Oops, I had amnesia😊 It will be split in next version.
Thanks, Zhiqiang
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface);+#endif if (!phydev) return 0;
@@ -787,14 +795,17 @@ int tsec_standard_init(bd_t *bis) return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); } #else /* CONFIG_DM_ETH */
+#ifndef CONFIG_DM_MDIO +#error "TSEC with DM_ETH also requires DM_MDIO" +#endif
int tsec_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct tsec_private *priv = dev_get_priv(dev);
struct tsec_mii_mng __iomem *ext_phyregs_mii; struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;struct fsl_pq_mdio_info mdio_info; const char *phy_mode; fdt_addr_t reg; ofnode parent;@@ -803,31 +814,6 @@ int tsec_probe(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,&phandle_args)) {printf("phy-handle does not exist under tsec %s\n",dev->name);
return -ENOENT;} else {int reg = ofnode_read_u32_default(phandle_args.node,"reg", 0);
priv->phyaddr = reg;}parent = ofnode_get_parent(phandle_args.node);if (!ofnode_valid(parent)) {printf("No parent node for PHY?\n");return -ENOENT;}reg = ofnode_get_addr_index(parent, 0);if (reg == FDT_ADDR_T_NONE) {printf("No 'reg' property of MII for external PHY\n");return -ENOENT;}ext_phyregs_mii = map_physmem(reg +TSEC_MDIO_REGS_OFFSET, 0,
MAP_NOCACHE);ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, &phandle_args); if (ret == 0) {@@ -865,12 +851,6 @@ int tsec_probe(struct udevice *dev) if (priv->interface == PHY_INTERFACE_MODE_SGMII) priv->flags |= TSEC_SGMII;
mdio_info.regs = ext_phyregs_mii;mdio_info.name = (char *)dev->name;ret = fsl_pq_mdio_init(NULL, &mdio_info);if (ret)return ret;/* Reset the MAC */ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); udelay(2); /* Soft Reset must be asserted for 3 TX clocks */-- 2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string "gianfar" support and update the device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/tsec.c | 16 ++++++++++++++-- include/tsec.h | 4 ++++ 3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt index 8e8574bc97..a44c5fd9d9 100644 --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -2,7 +2,7 @@
Properties:
- - compatible : Should be "fsl,etsec2" + - compatible : Should be "fsl,etsec2" or "gianfar" - reg : Offset and length of the register set for the device - phy-handle : See ethernet.txt file in the same directory. - phy-connection-type : See ethernet.txt file in the same directory. This diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index cb3e56d439..22658506b2 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -806,11 +806,14 @@ int tsec_probe(struct udevice *dev) struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; + struct tsec_data *data; const char *phy_mode; fdt_addr_t reg; ofnode parent; int ret;
+ data = (struct tsec_data *)dev_get_driver_data(dev); + pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);
@@ -831,7 +834,7 @@ int tsec_probe(struct udevice *dev) return -ENOENT; }
- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, + priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off, 0, MAP_NOCACHE); }
@@ -883,8 +886,17 @@ static const struct eth_ops tsec_ops = { .mcast = tsec_mcast_addr, };
+static struct tsec_data etsec2_data = { + .mdio_regs_off = TSEC_MDIO_REGS_OFFSET, +}; + +static struct tsec_data gianfar_data = { + .mdio_regs_off = 0x0, +}; + static const struct udevice_id tsec_ids[] = { - { .compatible = "fsl,etsec2" }, + { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data }, + { .compatible = "gianfar", .data = (ulong)&gianfar_data }, { } };
diff --git a/include/tsec.h b/include/tsec.h index b17fa957df..047dd3c373 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data { + u32 mdio_regs_off; +}; + struct tsec_private { struct txbd8 __iomem txbd[TX_BUF_CNT]; struct rxbd8 __iomem rxbd[PKTBUFSRX];
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string "gianfar" support and update the device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- Rebase the patch, no change intended.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/tsec.c | 16 ++++++++++++++-- include/tsec.h | 4 ++++ 3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt index 8e8574bc97..a44c5fd9d9 100644 --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -2,7 +2,7 @@
Properties:
- compatible : Should be "fsl,etsec2"
- compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index cb3e56d439..22658506b2 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -806,11 +806,14 @@ int tsec_probe(struct udevice *dev) struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct tsec_data *data; const char *phy_mode; fdt_addr_t reg; ofnode parent; int ret;data = (struct tsec_data *)dev_get_driver_data(dev);pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);@@ -831,7 +834,7 @@ int tsec_probe(struct udevice *dev) return -ENOENT; }
priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off, 0, MAP_NOCACHE); }@@ -883,8 +886,17 @@ static const struct eth_ops tsec_ops = { .mcast = tsec_mcast_addr, };
+static struct tsec_data etsec2_data = {
.mdio_regs_off = TSEC_MDIO_REGS_OFFSET,+};
+static struct tsec_data gianfar_data = {
.mdio_regs_off = 0x0,+};
static const struct udevice_id tsec_ids[] = {
{ .compatible = "fsl,etsec2" },
{ .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },{ .compatible = "gianfar", .data = (ulong)&gianfar_data }, { }};
diff --git a/include/tsec.h b/include/tsec.h index b17fa957df..047dd3c373 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data {
u32 mdio_regs_off;+};
struct tsec_private { struct txbd8 __iomem txbd[TX_BUF_CNT]; struct rxbd8 __iomem rxbd[PKTBUFSRX]; -- 2.25.1
Hi Vladimir,
Thanks a lot for your review!
Regards, Zhiqiang
-----Original Message----- From: Vladimir Oltean olteanv@gmail.com Sent: 2020年6月13日 4:40 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 04/15] net: tsec: Add the compatible string "gianfar" support
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string "gianfar" support and update the device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- Rebase the patch, no change intended.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/tsec.c | 16
++++++++++++++--
include/tsec.h | 4 ++++ 3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt index 8e8574bc97..a44c5fd9d9 100644 --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -2,7 +2,7 @@
Properties:
- compatible : Should be "fsl,etsec2"
- compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same
directory. This diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index cb3e56d439..22658506b2 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -806,11 +806,14 @@ int tsec_probe(struct udevice *dev) struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct tsec_data *data; const char *phy_mode; fdt_addr_t reg; ofnode parent; int ret;data = (struct tsec_data *)dev_get_driver_data(dev);pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev);@@ -831,7 +834,7 @@ int tsec_probe(struct udevice *dev) return -ENOENT; }
priv->phyregs_sgmii = map_physmem(reg +TSEC_MDIO_REGS_OFFSET,
priv->phyregs_sgmii = map_physmem(reg +- data->mdio_regs_off, 0,
MAP_NOCACHE);
}@@ -883,8 +886,17 @@ static const struct eth_ops tsec_ops = { .mcast = tsec_mcast_addr, };
+static struct tsec_data etsec2_data = {
.mdio_regs_off = TSEC_MDIO_REGS_OFFSET, };+static struct tsec_data gianfar_data = {
.mdio_regs_off = 0x0,+};
static const struct udevice_id tsec_ids[] = {
{ .compatible = "fsl,etsec2" },
{ .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },{ .compatible = "gianfar", .data = (ulong)&gianfar_data }, { }};
diff --git a/include/tsec.h b/include/tsec.h index b17fa957df..047dd3c373 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data {
u32 mdio_regs_off;+};
struct tsec_private { struct txbd8 __iomem txbd[TX_BUF_CNT]; struct rxbd8 __iomem rxbd[PKTBUFSRX]; -- 2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index da0a80e6fc..b904943b0e 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -347,6 +347,7 @@ int fixup_cpu(void) * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() */ +#ifndef CONFIG_DM_ETH int cpu_eth_init(bd_t *bis) { #if defined(CONFIG_ETHER_ON_FCC) @@ -370,3 +371,4 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } +#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Move vsc7835 firmware uploading to board_early_init_r(), so that the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++++++++++---------- 1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 1353debc0e..3dd6178708 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -316,6 +316,10 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); +#ifdef CONFIG_VSC7385_ENET + unsigned int vscfw_addr; + char *tmp; +#endif
/* * Remap Boot flash region to caching-inhibited @@ -338,6 +342,20 @@ int board_early_init_r(void) set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ + +#ifdef CONFIG_VSC7385_ENET + /* If a VSC7385 microcode image is present, then upload it. */ + tmp = env_get("vscfw_addr"); + if (tmp) { + vscfw_addr = simple_strtoul(tmp, NULL, 16); + printf("uploading VSC7385 microcode from %x\n", vscfw_addr); + if (vsc7385_upload_firmware((void *)vscfw_addr, + CONFIG_VSC7385_IMAGE_SIZE)) + puts("Failure uploading VSC7385 microcode.\n"); + } else { + puts("No address specified for VSC7385 microcode.\n"); + } +#endif return 0; }
@@ -348,10 +366,6 @@ int board_eth_init(bd_t *bis) ccsr_gur_t *gur __attribute__((unused)) = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; -#ifdef CONFIG_VSC7385_ENET - char *tmp; - unsigned int vscfw_addr; -#endif
#ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); @@ -375,19 +389,6 @@ int board_eth_init(bd_t *bis) return 0; }
-#ifdef CONFIG_VSC7385_ENET - /* If a VSC7385 microcode image is present, then upload it. */ - tmp = env_get("vscfw_addr"); - if (tmp) { - vscfw_addr = simple_strtoul(tmp, NULL, 16); - printf("uploading VSC7385 microcode from %x\n", vscfw_addr); - if (vsc7385_upload_firmware((void *) vscfw_addr, - CONFIG_VSC7385_IMAGE_SIZE)) - puts("Failure uploading VSC7385 microcode.\n"); - } else - puts("No address specified for VSC7385 microcode.\n"); -#endif - mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME;
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Move vsc7835 firmware uploading to board_early_init_r(), so that the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
For what it's worth, a DM_DSA uclass has been proposed exactly for this kind of stuff, but has received exactly zero review thus far: https://patchwork.ozlabs.org/project/uboot/cover/1588700588-8587-1-git-send-... So, given the tools we have, this is the best we can do.
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- Rebase the patch, no change intended.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++++++++++---------- 1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 1353debc0e..3dd6178708 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -316,6 +316,10 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); +#ifdef CONFIG_VSC7385_ENET
unsigned int vscfw_addr;char *tmp;+#endif
/* * Remap Boot flash region to caching-inhibited@@ -338,6 +342,20 @@ int board_early_init_r(void) set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */tmp = env_get("vscfw_addr");if (tmp) {vscfw_addr = simple_strtoul(tmp, NULL, 16);printf("uploading VSC7385 microcode from %x\n", vscfw_addr);if (vsc7385_upload_firmware((void *)vscfw_addr,CONFIG_VSC7385_IMAGE_SIZE))puts("Failure uploading VSC7385 microcode.\n");} else {puts("No address specified for VSC7385 microcode.\n");}+#endif return 0; }
@@ -348,10 +366,6 @@ int board_eth_init(bd_t *bis) ccsr_gur_t *gur __attribute__((unused)) = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; -#ifdef CONFIG_VSC7385_ENET
char *tmp;unsigned int vscfw_addr;-#endif
#ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); @@ -375,19 +389,6 @@ int board_eth_init(bd_t *bis) return 0; }
-#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */tmp = env_get("vscfw_addr");if (tmp) {vscfw_addr = simple_strtoul(tmp, NULL, 16);printf("uploading VSC7385 microcode from %x\n", vscfw_addr);if (vsc7385_upload_firmware((void *) vscfw_addr,CONFIG_VSC7385_IMAGE_SIZE))puts("Failure uploading VSC7385 microcode.\n");} elseputs("No address specified for VSC7385 microcode.\n");-#endif
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME;-- 2.25.1
Hi Vladimir,
Thanks a lot for your review!
Regards, Zhiqiang
-----Original Message----- From: Vladimir Oltean olteanv@gmail.com Sent: 2020年6月13日 4:37 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 06/15] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Move vsc7835 firmware uploading to board_early_init_r(), so that the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
For what it's worth, a DM_DSA uclass has been proposed exactly for this kind of stuff, but has received exactly zero review thus far: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch work.ozlabs.org%2Fproject%2Fuboot%2Fcover%2F1588700588-8587-1-git-s end-email-claudiu.manoil%40nxp.com%2F&data=02%7C01%7CZhiqian g.Hou%40nxp.com%7Cd10d8cbe295d402a213408d80f1059f9%7C686ea1d3 bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637275910184645214&sda ta=0gqLyzu96SUYn1t0Rrdjj6bEnT6r8CUSSelFnW%2BRpnE%3D&reserve d=0 So, given the tools we have, this is the best we can do.
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- Rebase the patch, no change intended.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++++++++++---------- 1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 1353debc0e..3dd6178708 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -316,6 +316,10 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); +#ifdef CONFIG_VSC7385_ENET
unsigned int vscfw_addr;char *tmp;+#endif
/* * Remap Boot flash region to caching-inhibited @@ -338,6+342,20 @@ int board_early_init_r(void) set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb,
epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/*perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel,tsize, iprot */
+#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */tmp = env_get("vscfw_addr");if (tmp) {vscfw_addr = simple_strtoul(tmp, NULL, 16);printf("uploading VSC7385 microcode from %x\n",vscfw_addr);
if (vsc7385_upload_firmware((void *)vscfw_addr,CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385microcode.\n");
} else {puts("No address specified for VSC7385microcode.\n");
}+#endif return 0; }
@@ -348,10 +366,6 @@ int board_eth_init(bd_t *bis) ccsr_gur_t *gur __attribute__((unused)) = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; -#ifdef CONFIG_VSC7385_ENET
char *tmp;unsigned int vscfw_addr;-#endif
#ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); @@ -375,19 +389,6
@@ int
board_eth_init(bd_t *bis) return 0; }
-#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */tmp = env_get("vscfw_addr");if (tmp) {vscfw_addr = simple_strtoul(tmp, NULL, 16);printf("uploading VSC7385 microcode from %x\n",vscfw_addr);
if (vsc7385_upload_firmware((void *) vscfw_addr,CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385microcode.\n");
} elseputs("No address specified for VSC7385microcode.\n");
-#endif
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME;-- 2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add the environment 'vscfw_addr' to assign a default address for vsc7385 firmware uploading.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
include/configs/p1_p2_rdb_pc.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 219e5d216b..6e00491cd8 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -460,6 +460,7 @@
/* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET +#define __VSCFW_ADDR "vscfw_addr=ef000000" #define CONFIG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT @@ -819,6 +820,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=120000\0" \ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ +__stringify(__VSCFW_ADDR)"\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P1020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
arch/powerpc/dts/p1020-post.dtsi | 16 +++++++ arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 ++++++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 57 +++++++++++++++++++++++++ arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++++ 11 files changed, 283 insertions(+) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9..2c0aa7a5c3 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -46,8 +46,24 @@
/include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: enet0_grp2: ethernet@b0000 { + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: enet1_grp2: ethernet@b1000 { + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: enet2_grp2: ethernet@b2000 { + }; };
+/include/ "pq3-etsec2-grp2-0.dtsi" +/include/ "pq3-etsec2-grp2-1.dtsi" +/include/ "pq3-etsec2-grp2-2.dtsi" + /* PCIe controller base address 0x9000 */ &pci1 { compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index 7ebaa619df..715330dc50 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -32,4 +32,5 @@ }; };
+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi new file mode 100644 index 0000000000..6bf424fd3f --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24000 { + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + + tbi0: tbi-phy@11 { + device_type = "tbi-phy"; + reg = <0x11>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index c0e5ef4cf4..7680b7c7e1 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -32,4 +32,5 @@ }; };
+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 21174a09be..7868c9b95c 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -17,6 +17,63 @@
soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; + + mdio@24000 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + ptp_clock@b0e00 { + compatible = "fsl,etsec-ptp"; + reg = <0xb0e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0>; + fsl,tclk-period = <10>; + fsl,tmr-prsc = <2>; + fsl,tmr-add = <0x80000016>; + fsl,tmr-fiper1 = <999999990>; + fsl,tmr-fiper2 = <99990>; + fsl,max-adj = <199999999>; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; };
pci1: pcie@ffe09000 { diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 0000000000..f9d3d04650 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; +}; + +ethernet@b0000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb0000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b0000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000 0x1000>; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi new file mode 100644 index 0000000000..6c01481909 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@25000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x25000 0x1000 0xb1030 0x4>; +}; + +ethernet@b1000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb1000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b1000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb1000 0x1000>; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi new file mode 100644 index 0000000000..2a597c0db6 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@26000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x26000 0x1000 0xb1030 0x4>; +}; + +ethernet@b2000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb2000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b2000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb2000 0x1000>; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi new file mode 100644 index 0000000000..16752a7c45 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet0_grp2 { + queue-group@b4000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb4000 0x1000>; + interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi new file mode 100644 index 0000000000..0464938424 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet1_grp2 { + queue-group@b5000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb5000 0x1000>; + interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi new file mode 100644 index 0000000000..fe8003c44a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet2_grp2 { + queue-group@b6000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb6000 0x1000>; + interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>; + }; +};
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P1020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY VSC7385
As you said in a previous patch, VSC7385 is a switch, not a PHY.
eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- Rebase the patch, no change intended.
arch/powerpc/dts/p1020-post.dtsi | 16 +++++++ arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 ++++++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 57 +++++++++++++++++++++++++ arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++++ 11 files changed, 283 insertions(+) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9..2c0aa7a5c3 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -46,8 +46,24 @@
/include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
Could you keep the indentation level of this include the same as the others?
enet0: enet0_grp2: ethernet@b0000 {
I don't understand why you're doing it like this (i.e. specifying the label here, and using it in pq3-etsec2-grp2-0.dtsi, vs just specifying the full path in pq3-etsec2-grp2-0.dtsi).
};+/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {};+/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {};};
+/include/ "pq3-etsec2-grp2-0.dtsi" +/include/ "pq3-etsec2-grp2-1.dtsi" +/include/ "pq3-etsec2-grp2-2.dtsi"
/* PCIe controller base address 0x9000 */ &pci1 { compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index 7ebaa619df..715330dc50 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -32,4 +32,5 @@ }; };
+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi new file mode 100644 index 0000000000..6bf424fd3f --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
- Copyright 2012 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&soc {
mdio@24000 {phy0: ethernet-phy@0 {interrupt-parent = <&mpic>;interrupts = <3 1 0 0>;reg = <0x0>;};phy1: ethernet-phy@1 {interrupt-parent = <&mpic>;interrupts = <2 1 0 0>;reg = <0x1>;};tbi0: tbi-phy@11 {device_type = "tbi-phy";reg = <0x11>;};};mdio@25000 {tbi1: tbi-phy@11 {reg = <0x11>;device_type = "tbi-phy";};};enet0: ethernet@b0000 {phy-connection-type = "rgmii-id";fixed-link {speed = <1000>;full-duplex;};};enet1: ethernet@b1000 {phy-handle = <&phy0>;tbi-handle = <&tbi1>;phy-connection-type = "sgmii";};enet2: ethernet@b2000 {phy-handle = <&phy1>;phy-connection-type = "rgmii-id";};+}; diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index c0e5ef4cf4..7680b7c7e1 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -32,4 +32,5 @@ }; };
+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 21174a09be..7868c9b95c 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -17,6 +17,63 @@
soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>;
mdio@24000 {phy0: ethernet-phy@0 {interrupts = <3 1 0 0>;reg = <0x0>;};phy1: ethernet-phy@1 {interrupts = <2 1 0 0>;reg = <0x1>;};};mdio@25000 {tbi1: tbi-phy@11 {reg = <0x11>;device_type = "tbi-phy";};};mdio@26000 {tbi2: tbi-phy@11 {reg = <0x11>;device_type = "tbi-phy";};};ptp_clock@b0e00 {compatible = "fsl,etsec-ptp";reg = <0xb0e00 0xb0>;interrupts = <68 2 0 0 69 2 0 0>;fsl,tclk-period = <10>;fsl,tmr-prsc = <2>;fsl,tmr-add = <0x80000016>;fsl,tmr-fiper1 = <999999990>;fsl,tmr-fiper2 = <99990>;fsl,max-adj = <199999999>;};
I'm pretty sure the PTP clock is not needed in U-Boot? Doesn't checkpatch give warnings about undocumented compatible string?
enet0: ethernet@b0000 {phy-connection-type = "rgmii-id";fixed-link {speed = <1000>;full-duplex;};};enet1: ethernet@b1000 {phy-handle = <&phy0>;tbi-handle = <&tbi1>;phy-connection-type = "sgmii";};enet2: ethernet@b2000 {phy-handle = <&phy1>;phy-connection-type = "rgmii-id";}; }; pci1: pcie@ffe09000 {diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 0000000000..f9d3d04650 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
- Copyright 2011 Freescale Semiconductor Inc.
Why the 2011 Freescale copyright?
- Copyright 2020 NXP
- */
+mdio@24000 {
You could have labeled the MDIO buses here, and just refer to the label in the board dtsi files. I'm not sure but you may need to use #include instead of /include/ for that.
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,etsec2-mdio";reg = <0x24000 0x1000 0xb0030 0x4>;+};
+ethernet@b0000 {
#address-cells = <1>;#size-cells = <1>;device_type = "network";model = "eTSEC";compatible = "fsl,etsec2";reg = <0xb0000 0x1000>;fsl,num_rx_queues = <0x8>;fsl,num_tx_queues = <0x8>;fsl,magic-packet;local-mac-address = [ 00 00 00 00 00 00 ];
I don't think this is needed.
ranges;queue-group@b0000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb0000 0x1000>;interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
What do these numbers represent? I'm not sure it is in the best interest of maintaining this driver to import so many DT bindings from Linux which are unused. It is highly unlikely that anyone will make use of them in the future.
};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi new file mode 100644 index 0000000000..6c01481909 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+mdio@25000 {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,etsec2-tbi";reg = <0x25000 0x1000 0xb1030 0x4>;+};
+ethernet@b1000 {
#address-cells = <1>;#size-cells = <1>;device_type = "network";model = "eTSEC";compatible = "fsl,etsec2";reg = <0xb1000 0x1000>;fsl,num_rx_queues = <0x8>;fsl,num_tx_queues = <0x8>;fsl,magic-packet;local-mac-address = [ 00 00 00 00 00 00 ];ranges;queue-group@b1000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb1000 0x1000>;interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi new file mode 100644 index 0000000000..2a597c0db6 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+mdio@26000 {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,etsec2-tbi";reg = <0x26000 0x1000 0xb1030 0x4>;+};
+ethernet@b2000 {
#address-cells = <1>;#size-cells = <1>;device_type = "network";model = "eTSEC";compatible = "fsl,etsec2";reg = <0xb2000 0x1000>;fsl,num_rx_queues = <0x8>;fsl,num_tx_queues = <0x8>;fsl,magic-packet;local-mac-address = [ 00 00 00 00 00 00 ];ranges;queue-group@b2000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb2000 0x1000>;interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi new file mode 100644 index 0000000000..16752a7c45 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&enet0_grp2 {
queue-group@b4000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb4000 0x1000>;interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi new file mode 100644 index 0000000000..0464938424 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&enet1_grp2 {
queue-group@b5000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb5000 0x1000>;interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi new file mode 100644 index 0000000000..fe8003c44a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&enet2_grp2 {
queue-group@b6000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb6000 0x1000>;interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;};+};
2.25.1
Hi Vladimir,
Thanks a lot for your comments!
-----Original Message----- From: Vladimir Oltean [mailto:olteanv@gmail.com] Sent: 2020年6月13日 4:15 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 08/15] dts: powerpc: p1020rdb: Add eTSEC DT nodes
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P1020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY VSC7385
As you said in a previous patch, VSC7385 is a switch, not a PHY.
These connection info was copied from the kernel changelog without further polish. I'll correct it in next version.
eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- Rebase the patch, no change intended.
arch/powerpc/dts/p1020-post.dtsi | 16 +++++++ arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55
++++++++++++++++++++++++
arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 57
+++++++++++++++++++++++++
arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++++ 11 files changed, 283 insertions(+) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9..2c0aa7a5c3 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -46,8 +46,24 @@
/include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
Could you keep the indentation level of this include the same as the others?
I don't think it is a good style to add indentation for the /include/ lines, I don't know why Biwen added it for these 2, and not for others. I can help to remove the indentation for the i2c include entries.
enet0: enet0_grp2: ethernet@b0000 {I don't understand why you're doing it like this (i.e. specifying the label here, and using it in pq3-etsec2-grp2-0.dtsi, vs just specifying the full path in pq3-etsec2-grp2-0.dtsi).
These DT nodes was copied from the Linux.
};+/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {};+/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {};};
+/include/ "pq3-etsec2-grp2-0.dtsi" +/include/ "pq3-etsec2-grp2-1.dtsi" +/include/ "pq3-etsec2-grp2-2.dtsi"
/* PCIe controller base address 0x9000 */ &pci1 { compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index 7ebaa619df..715330dc50 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -32,4 +32,5 @@ }; };
+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi new file mode 100644 index 0000000000..6bf424fd3f --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- P1020 RDB-PC Device Tree Source stub (no addresses or top-level
+ranges)
- Copyright 2012 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&soc {
mdio@24000 {phy0: ethernet-phy@0 {interrupt-parent = <&mpic>;interrupts = <3 1 0 0>;reg = <0x0>;};phy1: ethernet-phy@1 {interrupt-parent = <&mpic>;interrupts = <2 1 0 0>;reg = <0x1>;};tbi0: tbi-phy@11 {device_type = "tbi-phy";reg = <0x11>;};};mdio@25000 {tbi1: tbi-phy@11 {reg = <0x11>;device_type = "tbi-phy";};};enet0: ethernet@b0000 {phy-connection-type = "rgmii-id";fixed-link {speed = <1000>;full-duplex;};};enet1: ethernet@b1000 {phy-handle = <&phy0>;tbi-handle = <&tbi1>;phy-connection-type = "sgmii";};enet2: ethernet@b2000 {phy-handle = <&phy1>;phy-connection-type = "rgmii-id";};+}; diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index c0e5ef4cf4..7680b7c7e1 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -32,4 +32,5 @@ }; };
+/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 21174a09be..7868c9b95c 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -17,6 +17,63 @@
soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>;
mdio@24000 {phy0: ethernet-phy@0 {interrupts = <3 1 0 0>;reg = <0x0>;};phy1: ethernet-phy@1 {interrupts = <2 1 0 0>;reg = <0x1>;};};mdio@25000 {tbi1: tbi-phy@11 {reg = <0x11>;device_type = "tbi-phy";};};mdio@26000 {tbi2: tbi-phy@11 {reg = <0x11>;device_type = "tbi-phy";};};ptp_clock@b0e00 {compatible = "fsl,etsec-ptp";reg = <0xb0e00 0xb0>;interrupts = <68 2 0 0 69 2 0 0>;fsl,tclk-period = <10>;fsl,tmr-prsc = <2>;fsl,tmr-add = <0x80000016>;fsl,tmr-fiper1 = <999999990>;fsl,tmr-fiper2 = <99990>;fsl,max-adj = <199999999>;};I'm pretty sure the PTP clock is not needed in U-Boot? Doesn't checkpatch give warnings about undocumented compatible string?
OK, the PTP node will be removed in next version. Checkpatch tool does not report.
enet0: ethernet@b0000 {phy-connection-type = "rgmii-id";fixed-link {speed = <1000>;full-duplex;};};enet1: ethernet@b1000 {phy-handle = <&phy0>;tbi-handle = <&tbi1>;phy-connection-type = "sgmii";};enet2: ethernet@b2000 {phy-handle = <&phy1>;phy-connection-type = "rgmii-id";}; }; pci1: pcie@ffe09000 {diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 0000000000..f9d3d04650 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
- Copyright 2011 Freescale Semiconductor Inc.
Why the 2011 Freescale copyright?
As I had said these are copied from Linux, I think it is better to keep the copyright entry.
- Copyright 2020 NXP
- */
+mdio@24000 {
You could have labeled the MDIO buses here, and just refer to the label in the board dtsi files. I'm not sure but you may need to use #include instead of /include/ for that.
I trend to align with Linux DT nodes to reduce the risk.
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,etsec2-mdio";reg = <0x24000 0x1000 0xb0030 0x4>; };+ethernet@b0000 {
#address-cells = <1>;#size-cells = <1>;device_type = "network";model = "eTSEC";compatible = "fsl,etsec2";reg = <0xb0000 0x1000>;fsl,num_rx_queues = <0x8>;fsl,num_tx_queues = <0x8>;fsl,magic-packet;local-mac-address = [ 00 00 00 00 00 00 ];I don't think this is needed.
ranges;queue-group@b0000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb0000 0x1000>;interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;What do these numbers represent? I'm not sure it is in the best interest of maintaining this driver to import so many DT bindings from Linux which are unused. It is highly unlikely that anyone will make use of them in the future.
I want to align with Linux DT nodes, though I know current uboot doesn't use interrupt, but I don't trend to change them unless necessary.
Thanks, Zhiqiang
};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi new file mode 100644 index 0000000000..6c01481909 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+mdio@25000 {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,etsec2-tbi";reg = <0x25000 0x1000 0xb1030 0x4>; };+ethernet@b1000 {
#address-cells = <1>;#size-cells = <1>;device_type = "network";model = "eTSEC";compatible = "fsl,etsec2";reg = <0xb1000 0x1000>;fsl,num_rx_queues = <0x8>;fsl,num_tx_queues = <0x8>;fsl,magic-packet;local-mac-address = [ 00 00 00 00 00 00 ];ranges;queue-group@b1000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb1000 0x1000>;interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi new file mode 100644 index 0000000000..2a597c0db6 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+mdio@26000 {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,etsec2-tbi";reg = <0x26000 0x1000 0xb1030 0x4>; };+ethernet@b2000 {
#address-cells = <1>;#size-cells = <1>;device_type = "network";model = "eTSEC";compatible = "fsl,etsec2";reg = <0xb2000 0x1000>;fsl,num_rx_queues = <0x8>;fsl,num_tx_queues = <0x8>;fsl,magic-packet;local-mac-address = [ 00 00 00 00 00 00 ];ranges;queue-group@b2000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb2000 0x1000>;interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi new file mode 100644 index 0000000000..16752a7c45 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&enet0_grp2 {
queue-group@b4000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb4000 0x1000>;interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi new file mode 100644 index 0000000000..0464938424 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&enet1_grp2 {
queue-group@b5000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb5000 0x1000>;interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;};+}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi new file mode 100644 index 0000000000..fe8003c44a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
- Copyright 2011 Freescale Semiconductor Inc.
- Copyright 2020 NXP
- */
+&enet2_grp2 {
queue-group@b6000 {#address-cells = <1>;#size-cells = <1>;reg = <0xb6000 0x1000>;interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;};+};
2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 3dd6178708..41585cf342 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -359,6 +359,7 @@ int board_early_init_r(void) return 0; }
+#ifndef CONFIG_DM_ETH int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; @@ -406,6 +407,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis); } +#endif
#if defined(CONFIG_QE) && \ (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 3 +++ configs/P1020RDB-PC_SDCARD_defconfig | 3 +++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PC_defconfig | 3 +++ configs/P1020RDB-PD_NAND_defconfig | 3 +++ configs/P1020RDB-PD_SDCARD_defconfig | 3 +++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++ configs/P1020RDB-PD_defconfig | 3 +++ 12 files changed, 36 insertions(+)
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6ee52fe5e7..139a0be37e 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 489b91d8e7..f533225f26 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 4a8e4e3726..f3e87f0669 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -58,6 +58,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -69,8 +70,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index f9a4b735ca..04c355585d 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -56,8 +57,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 5c8231cba2..ee663c5861 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index ad2bb90a49..cabd6c6022 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -66,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index b8055e49b0..28a097b0ed 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -68,8 +69,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index a71985374e..580b4ef5c5 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -44,6 +44,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -55,8 +56,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 0043fd5f66..f1352d53d5 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -64,6 +64,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -75,8 +76,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index cb0a8aec65..bba6a0ce95 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -70,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 35e60ca856..3125fa1e9f 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index d7f19c3d96..d3a7afb0b4 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -59,8 +60,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P1010RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY AR8033 eTSEC2: Connected to SGMII PHY AR8033 eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi | 62 ++++++++++++++++++++++++++++ arch/powerpc/dts/p1010si-post.dtsi | 25 +++++++++++ 4 files changed, 89 insertions(+)
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts index c66c4923ac..360d254d91 100644 --- a/arch/powerpc/dts/p1010rdb-pa.dts +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -15,3 +15,4 @@ };
/include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts index b943de7cbb..062086a8c0 100644 --- a/arch/powerpc/dts/p1010rdb-pa_36b.dts +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -15,3 +15,4 @@ };
/include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi index 4f58ee2446..f7662648e5 100644 --- a/arch/powerpc/dts/p1010rdb.dtsi +++ b/arch/powerpc/dts/p1010rdb.dtsi @@ -5,6 +5,68 @@ * Copyright 2020 NXP */ &soc { + mdio@24000 { + phy0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy1: ethernet-phy@1 { + reg = <0x0>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + tbi-phy@3 { + device_type = "tbi-phy"; + reg = <0x3>; + }; + }; + + mdio@25000 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + ptp_clock@b0e00 { + compatible = "fsl,etsec-ptp"; + reg = <0xb0e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0>; + fsl,tclk-period = <10>; + fsl,tmr-prsc = <2>; + fsl,tmr-add = <0x80000016>; + fsl,tmr-fiper1 = <999999990>; + fsl,tmr-fiper2 = <99990>; + fsl,max-adj = <199999999>; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy1>; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy2>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + i2c@3000 { rtc@68 { compatible = "pericom,pt7c4338"; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi index 0289441381..f825208056 100644 --- a/arch/powerpc/dts/p1010si-post.dtsi +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -25,6 +25,31 @@ }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: ethernet@b0000 { + queue-group@b0000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: ethernet@b1000 { + queue-group@b1000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: ethernet@b2000 { + queue-group@b2000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + + }; };
/* controller at 0x9000 */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
board/freescale/p1010rdb/p1010rdb.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 66ccc0bd1e..309f4daa88 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -484,6 +484,7 @@ int checkboard(void) return 0; }
+#ifndef CONFIG_DM_ETH int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET @@ -524,6 +525,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis); } +#endif
#if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob)
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Ideally shouldn't all p1010rdb configs be converted to DM_ETH, and then board_eth_init can be deleted? What was the problem with the rest of the configs?
V3:
- Rebase the patch, no change intended.
board/freescale/p1010rdb/p1010rdb.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 66ccc0bd1e..309f4daa88 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -484,6 +484,7 @@ int checkboard(void) return 0; }
+#ifndef CONFIG_DM_ETH int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET @@ -524,6 +525,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);} +#endif
#if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob) -- 2.25.1
Hi Vladimir,
Thanks a lot for your comments!
-----Original Message----- From: Vladimir Oltean [mailto:olteanv@gmail.com] Sent: 2020年6月13日 4:25 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 12/15] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Ideally shouldn't all p1010rdb configs be converted to DM_ETH, and then board_eth_init can be deleted? What was the problem with the rest of the configs?
Now the SECBOOT defconfigs are still not converted.
Thanks, Zhiqiang
V3:
- Rebase the patch, no change intended.
board/freescale/p1010rdb/p1010rdb.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 66ccc0bd1e..309f4daa88 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -484,6 +484,7 @@ int checkboard(void) return 0; }
+#ifndef CONFIG_DM_ETH int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET @@ -524,6 +525,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);} +#endif
#if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob) -- 2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig | 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig | 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+)
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index da04cab014..bd31e7c8fa 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e6edd395e7..f5c5f0ead5 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index dcd606b0c2..229365a1eb 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index c0800c8d7d..147198fb88 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 29ba692ca1..1f2472a338 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index d8f87b5dac..35232a87fc 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 9711082529..6a46e3a253 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index de2ac2235f..6c7c12efc1 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 9f4876dd13..832f7ce431 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index e85af32e2c..61afaf67ac 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 45feab4ee4..8f483b4398 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 3cd94f84ea..447ef19530 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index ddfe7b43a1..d8aae17e84 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 6011f8a9d8..632afeaa89 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 65f86fff60..4ba919b206 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index f71ee19ba6..d5b9aca56d 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
I think you missed some configs. There are 28 P1010RDB configs, you updated only 16.
V3:
- Rebase the patch, no change intended.
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig | 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig | 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+)
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index da04cab014..bd31e7c8fa 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e6edd395e7..f5c5f0ead5 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index dcd606b0c2..229365a1eb 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index c0800c8d7d..147198fb88 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 29ba692ca1..1f2472a338 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index d8f87b5dac..35232a87fc 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 9711082529..6a46e3a253 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index de2ac2235f..6c7c12efc1 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 9f4876dd13..832f7ce431 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index e85af32e2c..61afaf67ac 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 45feab4ee4..8f483b4398 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 3cd94f84ea..447ef19530 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index ddfe7b43a1..d8aae17e84 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 6011f8a9d8..632afeaa89 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 65f86fff60..4ba919b206 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index f71ee19ba6..d5b9aca56d 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -- 2.25.1
Hi Vladimir,
Thanks a lot for your comments!
-----Original Message----- From: Vladimir Oltean [mailto:olteanv@gmail.com] Sent: 2020年6月13日 4:21 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 13/15] configs: P1010RDB: Enable DM_ETH config
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
I think you missed some configs. There are 28 P1010RDB configs, you updated only 16.
The *SECBOOT* ones are not converted to DM_ETH in this series since I don’t know how to verify the SECBOOT. SECBOOT owner can enable the DM_ETH directly if the SECBOOT works with DM mode.
Thanks, Zhiqiang
V3:
- Rebase the patch, no change intended.
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig | 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig | 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ 16 files changed, 32 insertions(+)
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index da04cab014..bd31e7c8fa 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e6edd395e7..f5c5f0ead5 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index dcd606b0c2..229365a1eb 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index c0800c8d7d..147198fb88 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 29ba692ca1..1f2472a338 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index d8f87b5dac..35232a87fc 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 9711082529..6a46e3a253 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index de2ac2235f..6c7c12efc1 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 9f4876dd13..832f7ce431 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index e85af32e2c..61afaf67ac 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 45feab4ee4..8f483b4398 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 3cd94f84ea..447ef19530 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index ddfe7b43a1..d8aae17e84 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -71,8 +71,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 6011f8a9d8..632afeaa89 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -53,8 +53,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 65f86fff60..4ba919b206 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -65,8 +65,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index f71ee19ba6..d5b9aca56d 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -- 2.25.1
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P2020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
arch/powerpc/dts/p2020-post.dtsi | 10 ++++ arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 59 ++++++++++++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi | 28 +++++++++++ arch/powerpc/dts/pq3-etsec1-1.dtsi | 28 +++++++++++ arch/powerpc/dts/pq3-etsec1-2.dtsi | 28 +++++++++++ arch/powerpc/dts/pq3-etsec1-3.dtsi | 28 +++++++++++ arch/powerpc/dts/pq3-etsec1-timer-0.dtsi | 13 ++++++ 9 files changed, 196 insertions(+) create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 4ed093dad4..af79705eba 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -40,6 +40,16 @@
/include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-timer-0.dtsi" + + ptp_clock@24e00 { + interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; + }; + +/include/ "pq3-etsec1-1.dtsi" +/include/ "pq3-etsec1-2.dtsi" };
/* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 08befd4c59..f3f6be1080 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -37,4 +37,5 @@ }; };
+/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi new file mode 100644 index 0000000000..9abd700999 --- /dev/null +++ b/arch/powerpc/dts/p2020rdb-pc.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24520 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25520 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26520 { + status = "disabled"; + }; + + ptp_clock@24e00 { + fsl,tclk-period = <5>; + fsl,tmr-prsc = <2>; + fsl,tmr-add = <0xaaaaaaab>; + fsl,tmr-fiper1 = <999999995>; + fsl,tmr-fiper2 = <99990>; + fsl,max-adj = <299999999>; + }; + + enet0: ethernet@24000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@25000 { + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@26000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 04b2519e1a..6d983b7d71 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -37,4 +37,5 @@ }; };
+/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi new file mode 100644 index 0000000000..8800243f34 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; +}; + +mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi new file mode 100644 index 0000000000..2bc62d1a57 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; +}; + +mdio@25520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x25520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi new file mode 100644 index 0000000000..d45865fe03 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; +}; + +mdio@26520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x26520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi new file mode 100644 index 0000000000..853a27359d --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; +}; + +mdio@27520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x27520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi new file mode 100644 index 0000000000..19b37aca1d --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ptp_clock@24e00 { + compatible = "fsl,etsec-ptp"; + reg = <0x24e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0>; +};
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Rebase the patch, no change intended.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig | 3 +++ 8 files changed, 24 insertions(+)
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3e6ea64ee3..4cd689f55d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 187cbee0d6..f46463a297 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 88c9224001..73d1be1013 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 88e24c30ba..21a0e85f98 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index dda34dd43e..800c728ed3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index c2b6ad5f32..81cbac2fe8 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 3ec208ee00..89308a503b 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 0f0a6ad810..66fc3b0a14 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -60,8 +61,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- Rebase the patch, no change intended.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig | 3 +++ 8 files changed, 24 insertions(+)
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3e6ea64ee3..4cd689f55d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 187cbee0d6..f46463a297 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 88c9224001..73d1be1013 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 88e24c30ba..21a0e85f98 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index dda34dd43e..800c728ed3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index c2b6ad5f32..81cbac2fe8 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 3ec208ee00..89308a503b 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 0f0a6ad810..66fc3b0a14 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -60,8 +61,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -- 2.25.1
Hi Vladimir,
Thanks a lot for your review!
Regards, Zhiqiang
-----Original Message----- From: Vladimir Oltean olteanv@gmail.com Sent: 2020年6月13日 4:17 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; Bin Meng bmeng.cn@gmail.com Subject: Re: [PATCHv3 15/15] configs: P2020RDB: Enable DM_ETH config
On Fri, 12 Jun 2020 at 18:23, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com
V3:
- Rebase the patch, no change intended.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_defconfig | 3 +++ configs/P2020RDB-PC_NAND_defconfig | 3 +++ configs/P2020RDB-PC_SDCARD_defconfig | 3 +++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++ configs/P2020RDB-PC_defconfig | 3 +++ 8 files changed, 24 insertions(+)
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3e6ea64ee3..4cd689f55d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 187cbee0d6..f46463a297 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 88c9224001..73d1be1013 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 88e24c30ba..21a0e85f98 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index dda34dd43e..800c728ed3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index c2b6ad5f32..81cbac2fe8 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 3ec208ee00..89308a503b 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 0f0a6ad810..66fc3b0a14 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -60,8 +61,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -- 2.25.1
participants (3)
-
Vladimir Oltean -
Z.q. Hou -
Zhiqiang Hou