We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay. The MASK was used in a wrong way.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- drivers/net/gmac_rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 30a24d1..0f91731 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -350,7 +350,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3328_RXCLK_DLY_ENA_GMAC_MASK | RK3328_TXCLK_DLY_ENA_GMAC_MASK, RK3328_GMAC_PHY_INTF_SEL_RGMII | - RK3328_RXCLK_DLY_ENA_GMAC_MASK | + RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);

rk_clrsetreg(&grf->mac_con[0],

This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device.

One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux).

Based on commit 'fc6d39c39581f3c12c95f166ce95ef8beb2047e8' of mainline linux kernel

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- drivers/net/phy/ti.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index d7ae881..086ea4a 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DP83867_CTRL 0x1f

/* Extended Registers */ +#define DP83867_CFG4 0x0031 #define DP83867_RGMIICTL 0x0032 #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170 @@ -92,11 +93,21 @@ DECLARE_GLOBAL_DATA_PTR; #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f

+/* CFG4 bits */ +#define DP83867_CFG4_PORT_MIRROR_EN BIT(0) + +enum { + DP83867_PORT_MIRRORING_KEEP, + DP83867_PORT_MIRRORING_EN, + DP83867_PORT_MIRRORING_DIS, +}; + struct dp83867_private { int rx_id_delay; int tx_id_delay; int fifo_depth; int io_impedance; + int port_mirroring; };

/** @@ -165,6 +176,26 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, phy_write(phydev, addr, MII_MMD_DATA, data); }

+static int dp83867_config_port_mirroring(struct phy_device *phydev) +{ + struct dp83867_private *dp83867 = + (struct dp83867_private *)phydev->priv; + u16 val; + + val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + phydev->addr); + + if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN) + val |= DP83867_CFG4_PORT_MIRROR_EN; + else + val &= ~DP83867_CFG4_PORT_MIRROR_EN; + + phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + phydev->addr, val); + + return 0; +} + #if defined(CONFIG_DM_ETH) /** * dp83867_data_init - Convenience function for setting PHY specific data @@ -191,6 +222,12 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,tx-internal-delay", -1);

+ if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap")) + dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN; + + if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap")) + dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS; + dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,fifo-depth", -1);

@@ -307,6 +344,9 @@ static int dp83867_config(struct phy_device *phydev) } }

+ if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP) + dp83867_config_port_mirroring(phydev); + genphy_config_aneg(phydev); return 0;

The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)).

There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY.

Implement driver support for device-tree property meant to advertise the wrong strapping.

[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf

Based on commit '371444764b9882d754d1e67dd212c932359a2293' of mainline linux kernel.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- drivers/net/phy/ti.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 16c8929..cc04789 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -112,6 +112,7 @@ struct dp83867_private { int fifo_depth; int io_impedance; int port_mirroring; + bool rxctrl_strap_quirk; };

/** @@ -220,6 +221,9 @@ static int dp83867_of_init(struct phy_device *phydev) else dp83867->io_impedance = -EINVAL;

+ dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node, + "ti,dp83867-rxctrl-strap-quirk"); + dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,rx-internal-delay", -1);

@@ -275,6 +279,15 @@ static int dp83867_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, val | DP83867_SW_RESTART);

+ /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ + if (dp83867->rxctrl_strap_quirk) { + val = phy_read_mmd_indirect(phydev, DP83867_CFG4, + DP83867_DEVADDR, phydev->addr); + val &= ~BIT(7); + phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + phydev->addr, val); + } + if (phy_interface_is_rgmii(phydev)) { val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL); if (val < 0)

Using PHY internal delays in combination with the phy-mode rgmii-id/rxid/txid was not possible. Only rgmii was supported.

Now we can disable rockchip's gmac delay lines and also use rgmii-id/rxid/txid.

Based on commit 'eaf70ad14cbbb99d46b78b1307628a16a3f6075d' from mainline linux kernel.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 63 insertions(+), 17 deletions(-)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 0f91731..c01ae75 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -24,6 +24,11 @@ #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h"

+DECLARE_GLOBAL_DATA_PTR; +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \ + ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE)) + /* * Platform data for the gmac * @@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3228_RXCLK_DLY_ENA_GMAC_MASK | RK3228_TXCLK_DLY_ENA_GMAC_MASK, RK3228_GMAC_PHY_INTF_SEL_RGMII | - RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); + DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));

rk_clrsetreg(&grf->mac_con[0], RK3228_CLK_RX_DL_CFG_GMAC_MASK | @@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3288_TXCLK_DLY_ENA_GMAC_MASK | RK3288_CLK_RX_DL_CFG_GMAC_MASK | RK3288_CLK_TX_DL_CFG_GMAC_MASK, - RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) | pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3328_RXCLK_DLY_ENA_GMAC_MASK | RK3328_TXCLK_DLY_ENA_GMAC_MASK, RK3328_GMAC_PHY_INTF_SEL_RGMII | - RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); + DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));

rk_clrsetreg(&grf->mac_con[0], RK3328_CLK_RX_DL_CFG_GMAC_MASK | @@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3368_TXCLK_DLY_ENA_GMAC_MASK | RK3368_CLK_RX_DL_CFG_GMAC_MASK | RK3368_CLK_TX_DL_CFG_GMAC_MASK, - RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) | pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3399_TXCLK_DLY_ENA_GMAC_MASK | RK3399_CLK_RX_DL_CFG_GMAC_MASK | RK3399_CLK_TX_DL_CFG_GMAC_MASK, - RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) | pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)

switch (eth_pdata->phy_interface) { case PHY_INTERFACE_MODE_RGMII: + /* Set to RGMII mode */ + if (ops->set_to_rgmii) + ops->set_to_rgmii(pdata); + else + return -EPERM; + /* * If the gmac clock is from internal pll, need to set and * check the return value for gmac clock at RGMII mode. If * the gmac clock is from external source, the clock rate * is not set, because of it is bypassed. */ + if (!pdata->clock_input) { rate = clk_set_rate(&clk, 125000000); if (rate != 125000000) return -EINVAL; } + break;

+ case PHY_INTERFACE_MODE_RGMII_ID: /* Set to RGMII mode */ - if (ops->set_to_rgmii) + if (ops->set_to_rgmii) { + pdata->tx_delay = 0; + pdata->rx_delay = 0; ops->set_to_rgmii(pdata); - else + } else return -EPERM;

- break; - case PHY_INTERFACE_MODE_RMII: - /* The commet is the same as RGMII mode */ if (!pdata->clock_input) { - rate = clk_set_rate(&clk, 50000000); - if (rate != 50000000) + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) return -EINVAL; } + break;

+ case PHY_INTERFACE_MODE_RMII: /* Set to RMII mode */ if (ops->set_to_rmii) ops->set_to_rmii(pdata); else return -EPERM;

+ if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 50000000); + if (rate != 50000000) + return -EINVAL; + } + break; + + case PHY_INTERFACE_MODE_RGMII_RXID: + /* Set to RGMII_RXID mode */ + if (ops->set_to_rgmii) { + pdata->tx_delay = 0; + ops->set_to_rgmii(pdata); + } else + return -EPERM; + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) + return -EINVAL; + } break; + + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set to RGMII_TXID mode */ + if (ops->set_to_rgmii) { + pdata->rx_delay = 0; + ops->set_to_rgmii(pdata); + } else + return -EPERM; + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) + return -EINVAL; + } + break; + default: debug("NO interface defined!\n"); return -ENXIO;

Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT.

The phy-handle also needs to be stored and passed to the phy to access any phy data that is available.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- drivers/net/designware.c | 11 ++++++++++- drivers/net/designware.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/net/designware.c b/drivers/net/designware.c index cf12521..8cc7fb9 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -467,7 +467,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; int mask = 0xffffffff, ret; - + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); #ifdef CONFIG_PHY_ADDR mask = 1 << CONFIG_PHY_ADDR; #endif @@ -486,6 +486,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) } phydev->advertising = phydev->supported;

+#ifdef CONFIG_DM_ETH + if (dw_pdata->phy_of_handle) + dev_set_of_offset(phydev->dev, dw_pdata->phy_of_handle); +#endif + priv->phydev = phydev; phy_config(phydev);

@@ -786,6 +791,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) int reset_flags = GPIOD_IS_OUT; #endif int ret = 0; + int node = dev_of_offset(dev);

pdata->iobase = dev_read_addr(dev); pdata->phy_interface = -1; @@ -797,6 +803,9 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }

+ dw_pdata->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);

#ifdef CONFIG_DM_GPIO diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7..a6b0443 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + int phy_of_handle; };

int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);

The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels. Create a binding to select a specific clock for CLK_OUT pin.

Based on commit '9708fb630d19ee51ae3aeb3a533e3010da0e8570' mainline linux kernel.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- drivers/net/phy/ti.c | 24 ++++++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 15 +++++++++++++++ 2 files changed, 39 insertions(+)

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index cc04789..9044b0f 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -96,6 +96,8 @@ DECLARE_GLOBAL_DATA_PTR;

#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f +#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) +#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8

/* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) @@ -113,6 +115,7 @@ struct dp83867_private { int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; + int clk_output_sel; };

/** @@ -213,6 +216,16 @@ static int dp83867_of_init(struct phy_device *phydev) struct udevice *dev = phydev->dev; int node = dev_of_offset(dev); const void *fdt = gd->fdt_blob; + u16 val; + + /* Optional configuration */ + + /* Keep the default value if ti,clk-output-sel is not set + * or to high + */ + + dp83867->clk_output_sel = fdtdec_get_uint(fdt, node, + "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);

if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance")) dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; @@ -239,6 +252,17 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,fifo-depth", -1);

+ /* Clock output selection if muxing property is set */ + if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) { + val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG, + DP83867_DEVADDR, phydev->addr); + val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; + val |= (dp83867->clk_output_sel << + DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT); + phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG, + DP83867_DEVADDR, phydev->addr, val); + } + return 0; } #else diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index b8e5df6..85d08f6 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -31,4 +31,19 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf

+/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC + #endif

The CLK_O_SEL default is synchronus to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- arch/arm/dts/rk3288-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 02d1196..2dba0aa 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -191,6 +191,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; }; }; };