[U-Boot] [PATCH 0/2] net: phy: mv88e61xx: Revise as a PHY driver
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Prafulla Wadaskar prafulla@marvell.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de
Kevin Smith (2): net: Remove unused mv88e61xx switch driver net: phy: Add PHY driver for mv88e61xx switches
drivers/net/phy/mv88e61xx.c | 959 +++++++++++++++++++++++++------------------- drivers/net/phy/mv88e61xx.h | 61 --- drivers/net/phy/phy.c | 3 + include/netdev.h | 58 --- include/phy.h | 1 + 5 files changed, 547 insertions(+), 535 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.h
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is a complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de
Kevin Smith (2): net: Remove unused mv88e61xx switch driver net: phy: Add PHY driver for mv88e61xx switches
drivers/net/phy/mv88e61xx.c | 959 +++++++++++++++++++++++++------------------- drivers/net/phy/mv88e61xx.h | 61 --- drivers/net/phy/phy.c | 3 + include/netdev.h | 58 --- include/phy.h | 1 + 5 files changed, 547 insertions(+), 535 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.h
Hello Kevin,
On Mon, 21 Dec 2015 21:45:32 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is a complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Actually the driver was for the Wireless Space, which was removed but which I will resurrect as I did the Open-RDs. I will test the switch on the WS I have.
Amicalement,
Hi Albert,
On Tue, Jan 26, 2016 at 10:09 AM, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hello Kevin,
On Mon, 21 Dec 2015 21:45:32 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is a complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Actually the driver was for the Wireless Space, which was removed but which I will resurrect as I did the Open-RDs. I will test the switch on the WS I have.
That's great. I'm currently reviewing the new driver and will appreciate the testing. I don't have any boards with this switch.
Thanks, -Joe
Hi Albert,
On 01/26/2016 10:13 AM, Joe Hershberger wrote:
Hi Albert,
On Tue, Jan 26, 2016 at 10:09 AM, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hello Kevin,
On Mon, 21 Dec 2015 21:45:32 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is a complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Actually the driver was for the Wireless Space, which was removed but which I will resurrect as I did the Open-RDs. I will test the switch on the WS I have.
That's great. I'm currently reviewing the new driver and will appreciate the testing. I don't have any boards with this switch.
Thanks, -Joe
Could you please send me more info on the Wireless Space board? I would like something other than our custom board to test this on. I tried to get a Marvell RD-A370, but they are too expensive. I will be glad to add back in the command-line interface for configuring this board if it is needed to support your work.
Thanks for testing, Kevin
P.S. I did not receive your e-mail at my business address somehow; I added my personal e-mail to ensure I get your responses.
Hello Kevin,
On Tue, 26 Jan 2016 16:56:21 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
Hi Albert,
On 01/26/2016 10:13 AM, Joe Hershberger wrote:
Hi Albert,
On Tue, Jan 26, 2016 at 10:09 AM, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hello Kevin,
On Mon, 21 Dec 2015 21:45:32 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is a complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Actually the driver was for the Wireless Space, which was removed but which I will resurrect as I did the Open-RDs. I will test the switch on the WS I have.
That's great. I'm currently reviewing the new driver and will appreciate the testing. I don't have any boards with this switch.
Thanks, -Joe
Could you please send me more info on the Wireless Space board? I would like something other than our custom board to test this on. I tried to get a Marvell RD-A370, but they are too expensive. I will be glad to add back in the command-line interface for configuring this board if it is needed to support your work.
Not sure if you can find one... You can find some doc there:
http://lacie.nas-central.org/wiki/Category:Wireless_Space
The switch is a 88E6161-LG02.
Thanks for testing, Kevin
P.S. I did not receive your e-mail at my business address somehow; I added my personal e-mail to ensure I get your responses.
Weird. Maybe your business mail exchanger relies on a blocking list which considers that only professional mail providers should be allowed to deliver e-mail; I am using my own mail exchanger. Thanks for letting me know!
Amicalement,
No boards are using this driver. Remove in preparation for a new driver with integrated PHY support.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de --- drivers/net/phy/mv88e61xx.c | 537 -------------------------------------------- drivers/net/phy/mv88e61xx.h | 61 ----- include/netdev.h | 58 ----- 3 files changed, 656 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.c delete mode 100644 drivers/net/phy/mv88e61xx.h
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c deleted file mode 100644 index 302abe8..0000000 --- a/drivers/net/phy/mv88e61xx.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include "mv88e61xx.h" - -/* - * Uncomment either of the following line for local debug control; - * otherwise global debug control will apply. - */ - -/* #undef DEBUG */ -/* #define DEBUG */ - -#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE -/* Chip Address mode - * The Switch support two modes of operation - * 1. single chip mode and - * 2. Multi-chip mode - * Refer section 9.2 &9.3 in chip datasheet-02 for more details - * - * By default single chip mode is configured - * multichip mode operation can be configured in board header - */ -static int mv88e61xx_busychk_multic(char *name, u32 devaddr) -{ - u16 reg = 0; - u32 timeout = MV88E61XX_PHY_TIMEOUT; - - /* Poll till SMIBusy bit is clear */ - do { - miiphy_read(name, devaddr, 0x0, ®); - if (timeout-- == 0) { - printf("SMI busy timeout\n"); - return -1; - } - } while (reg & (1 << 15)); - return 0; -} - -static void mv88e61xx_switch_write(char *name, u32 phy_adr, - u32 reg_ofs, u16 data) -{ - u16 mii_dev_addr; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { - printf("Error..could not read PHY dev address\n"); - return; - } - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Write data to Switch indirect data register */ - miiphy_write(name, mii_dev_addr, 0x1, data); - /* Write command to Switch indirect command register (write) */ - miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << - 15)); -} - -static void mv88e61xx_switch_read(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data) -{ - u16 mii_dev_addr; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { - printf("Error..could not read PHY dev address\n"); - return; - } - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Write command to Switch indirect command register (read) */ - miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 << - 15)); - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Read data from Switch indirect data register */ - miiphy_read(name, mii_dev_addr, 0x1, data); -} -#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ - -/* - * Convenience macros for switch device/port reads/writes - * These macros output valid 'mv88e61xx' U_BOOT_CMDs - */ - -#ifndef DEBUG -#define WR_SWITCH_REG wr_switch_reg -#define RD_SWITCH_REG rd_switch_reg -#define WR_SWITCH_PORT_REG(n, p, r, d) \ - WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) -#define RD_SWITCH_PORT_REG(n, p, r, d) \ - RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) -#else -static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) -{ - printf("mv88e61xx %s dev %02x reg %02x write %04x\n", - name, dev_adr, reg_ofs, data); - wr_switch_reg(name, dev_adr, reg_ofs, data); -} -static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) -{ - rd_switch_reg(name, dev_adr, reg_ofs, data); - printf("mv88e61xx %s dev %02x reg %02x read %04x\n", - name, dev_adr, reg_ofs, *data); -} -static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, - u16 data) -{ - printf("mv88e61xx %s port %02x reg %02x write %04x\n", - name, prt_adr, reg_ofs, data); - wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); -} -static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, - u16 *data) -{ - rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); - printf("mv88e61xx %s port %02x reg %02x read %04x\n", - name, prt_adr, reg_ofs, *data); -} -#endif - -/* - * Local functions to read/write registers on the switch PHYs. - * NOTE! This goes through switch, not direct miiphy, writes and reads! - */ - -/* - * Make sure SMIBusy bit cleared before another - * SMI operation can take place - */ -static int mv88e61xx_busychk(char *name) -{ - u16 reg = 0; - u32 timeout = MV88E61XX_PHY_TIMEOUT; - do { - rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, ®); - if (timeout-- == 0) { - printf("SMI busy timeout\n"); - return -1; - } - } while (reg & 1 << 15); /* busy mask */ - return 0; -} - -static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, - u32 reg, u16 data) -{ - /* write switch data reg then cmd reg then check completion */ - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, - data); - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, - (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); - return mv88e61xx_busychk(name); -} - -static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, - u32 reg, u16 *data) -{ - /* write switch cmd reg, check for completion */ - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, - (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); - if (mv88e61xx_busychk(name)) - return -1; - /* read switch data reg and return success */ - rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); - return 0; -} - -/* - * Convenience macros for switch PHY reads/writes - */ - -#ifndef DEBUG -#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write -#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read -#else -static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, - u32 reg_ofs, u16 data) -{ - int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); - if (r) - printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", - name, phy_adr, reg_ofs); - else - printf("mv88e61xx %s phy %02x reg %02x write %04x\n", - name, phy_adr, reg_ofs, data); - return r; -} -static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data) -{ - int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); - if (r) - printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", - name, phy_adr, reg_ofs); - else - printf("mv88e61xx %s phy %02x reg %02x read %04x\n", - name, phy_adr, reg_ofs, *data); - return r; -} -#endif - -static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) -{ - u32 prt; - u16 reg; - char *name = swconfig->name; - u32 port_mask = swconfig->ports_enabled; - - /* apply internal vlan config */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - /* only for enabled ports */ - if ((1 << prt) & port_mask) { - /* take vlan map from swconfig */ - u8 vlanmap = swconfig->vlancfg[prt]; - /* remove disabled ports from vlan map */ - vlanmap &= swconfig->ports_enabled; - /* apply vlan map to port */ - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VMAP_REG, ®); - reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); - reg |= vlanmap; - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VMAP_REG, reg); - } - } -} - -/* - * Power up the specified port and reset PHY - */ -static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - /* Write Copper Specific control reg1 (0x10) for- - * Enable Phy power up - * Energy Detect on (sense&Xmit NLP Periodically - * reset other settings default - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) - return -1; - - /* Write PHY ctrl reg (0x0) to apply - * Phy reset (set bit 15 low) - * reset other default values - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) - return -1; - - return 0; -} - -/* - * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) - * is set to "On-1000Mb/s Link, Off Else" - * This function sets it to "On-Link, Blink-Activity, Off-NoLink" - * - * This is optional settings may be needed on some boards - * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s - * Link status - */ -static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - if (swconfig->led_init != MV88E61XX_LED_INIT_EN) - return 0; - - /* set page address to 3 */ - if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) - return -1; - - /* - * set LED Func Ctrl reg - * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) - return -1; - - /* set page address to 0 */ - if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) - return -1; - - return 0; -} - -/* - * Reverse Transmit polarity for Media Dependent Interface - * Pins (MDIP) bits in Copper Specific Control Register 3 - * (Page 0, Reg 20 for each phy (except cpu port) - * Reference: Section 1.1 Switch datasheet-3 - * - * This is optional settings may be needed on some boards - * for PHY<->magnetics h/w tuning - */ -static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) - return 0; - - /*Reverse MDIP/N[3:0] bits */ - if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) - return -1; - - return 0; -} - -/* - * Marvell 88E61XX Switch initialization - */ -int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) -{ - u32 prt; - u16 reg; - char *idstr; - char *name = swconfig->name; - int time; - - if (miiphy_set_current_dev(name)) { - printf("%s failed\n", __FUNCTION__); - return -1; - } - - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { - swconfig->cpuport = (1 << 5); - printf("Invalid cpu port config, using default port5\n"); - } - - RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); - switch (reg &= 0xfff0) { - case 0x1610: - idstr = "88E6161"; - break; - case 0x1650: - idstr = "88E6165"; - break; - case 0x1210: - idstr = "88E6123"; - /* ports 2,3,4 not available */ - swconfig->ports_enabled &= 0x023; - break; - default: - /* Could not detect switch id */ - idstr = "88E61??"; - break; - } - - /* be sure all ports are disabled */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); - } - - /* wait 2 ms for queues to drain */ - udelay(2000); - - /* reset switch */ - RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); - reg |= 0x8000; - WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); - - /* wait up to 1 second for switch reset complete */ - for (time = 1000; time; time--) { - RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, - ®); - if ((reg & 0xc800) == 0xc800) - break; - udelay(1000); - } - if (!time) - return -1; - - /* Port based VLANs configuration */ - mv88e61xx_port_vlan_config(swconfig); - - if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 9.5 of chip datasheet-02 - */ - /*Force port link down */ - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); - /* configure port RGMII delay */ - WR_SWITCH_PORT_REG(name, 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); - RD_SWITCH_PORT_REG(name, 5, - MV88E61XX_RGMII_TIMECTRL_REG, ®); - WR_SWITCH_PORT_REG(name, 5, - MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); - WR_SWITCH_PORT_REG(name, 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); - /* Force port to RGMII FDX 1000Base then up */ - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); - } - - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - - /* configure port's PHY */ - if (!((1 << prt) & swconfig->cpuport)) { - /* port 4 has phy 6, not 4 */ - int phy = (prt == 4) ? 6 : prt; - if (mv88361xx_powerup(swconfig, phy)) - return -1; - if (mv88361xx_reverse_mdipn(swconfig, phy)) - return -1; - if (mv88361xx_led_init(swconfig, phy)) - return -1; - } - - /* set port VID to port+1 except for cpu port */ - if (!((1 << prt) & swconfig->cpuport)) { - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VID_REG, ®); - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VID_REG, - (reg & ~1023) | (prt+1)); - } - - /*Program port state */ - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_CTRL_REG, ®); - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_CTRL_REG, - reg | (swconfig->portstate & 0x03)); - - } - - printf("%s Initialized on %s\n", idstr, name); - return 0; -} - -#ifdef CONFIG_MV88E61XX_CMD -static int -do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *name, *endp; - int write = 0; - enum { dev, prt, phy } target = dev; - u32 addrlo, addrhi, addr; - u32 reglo, reghi, reg; - u16 data, rdata; - - if (argc < 7) - return -1; - - name = argv[1]; - - if (strcmp(argv[2], "phy") == 0) - target = phy; - else if (strcmp(argv[2], "port") == 0) - target = prt; - else if (strcmp(argv[2], "dev") != 0) - return 1; - - addrlo = simple_strtoul(argv[3], &endp, 16); - - if (!*endp) { - addrhi = addrlo; - } else { - while (*endp < '0' || *endp > '9') - endp++; - addrhi = simple_strtoul(endp, NULL, 16); - } - - reglo = simple_strtoul(argv[5], &endp, 16); - if (!*endp) { - reghi = reglo; - } else { - while (*endp < '0' || *endp > '9') - endp++; - reghi = simple_strtoul(endp, NULL, 16); - } - - if (strcmp(argv[6], "write") == 0) - write = 1; - else if (strcmp(argv[6], "read") != 0) - return 1; - - data = simple_strtoul(argv[7], NULL, 16); - - for (addr = addrlo; addr <= addrhi; addr++) { - for (reg = reglo; reg <= reghi; reg++) { - if (write) { - if (target == phy) - mv88e61xx_switch_miiphy_write( - name, addr, reg, data); - else if (target == prt) - wr_switch_reg(name, - addr+MV88E61XX_PRT_OFST, - reg, data); - else - wr_switch_reg(name, addr, reg, data); - } else { - if (target == phy) - mv88e61xx_switch_miiphy_read( - name, addr, reg, &rdata); - else if (target == prt) - rd_switch_reg(name, - addr+MV88E61XX_PRT_OFST, - reg, &rdata); - else - rd_switch_reg(name, addr, reg, &rdata); - printf("%s %s %s %02x %s %02x %s %04x\n", - argv[0], argv[1], argv[2], addr, - argv[4], reg, argv[6], rdata); - if (write && argc == 7 && rdata != data) - return 1; - } - } - } - return 0; -} - -U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, - "Read or write mv88e61xx switch registers", - "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n" - "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n" - " - read/write switch device, port or phy at (addr,reg)\n" - " addr=0..0x1C for dev, 0..5 for port or phy.\n" - " reg=0..0x1F.\n" - " data=0..0xFFFF (tested if present against actual read).\n" - " All numeric parameters are assumed to be hex.\n" - " <addr> and <<reg> arguments can be ranges (x..y)" -); -#endif /* CONFIG_MV88E61XX_CMD */ diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h deleted file mode 100644 index 9c62e4a..0000000 --- a/drivers/net/phy/mv88e61xx.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MV88E61XX_H -#define _MV88E61XX_H - -#include <miiphy.h> - -#define MV88E61XX_CPU_PORT 0x5 - -#define MV88E61XX_PHY_TIMEOUT 100000 - -/* port dev-addr (= port + 0x10) */ -#define MV88E61XX_PRT_OFST 0x10 -/* port registers */ -#define MV88E61XX_PCS_CTRL_REG 0x1 -#define MV88E61XX_PRT_CTRL_REG 0x4 -#define MV88E61XX_PRT_VMAP_REG 0x6 -#define MV88E61XX_PRT_VID_REG 0x7 -#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A - -/* global registers dev-addr */ -#define MV88E61XX_GLBREG_DEVADR 0x1B -/* global registers */ -#define MV88E61XX_SGSR 0x00 -#define MV88E61XX_SGCR 0x04 - -/* global 2 registers dev-addr */ -#define MV88E61XX_GLB2REG_DEVADR 0x1C -/* global 2 registers */ -#define MV88E61XX_PHY_CMD 0x18 -#define MV88E61XX_PHY_DATA 0x19 -/* global 2 phy commands */ -#define MV88E61XX_PHY_WRITE_CMD 0x9400 -#define MV88E61XX_PHY_READ_CMD 0x9800 - -#define MV88E61XX_BUSY_OFST 15 -#define MV88E61XX_MODE_OFST 12 -#define MV88E61XX_OP_OFST 10 -#define MV88E61XX_ADDR_OFST 5 - -#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE -static int mv88e61xx_busychk_multic(char *name, u32 devaddr); -static void mv88e61xx_switch_write(char *name, u32 phy_adr, - u32 reg_ofs, u16 data); -static void mv88e61xx_switch_read(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data); -#define wr_switch_reg mv88e61xx_switch_write -#define rd_switch_reg mv88e61xx_switch_read -#else -/* switch appears a s simple PHY and can thus use miiphy */ -#define wr_switch_reg miiphy_write -#define rd_switch_reg miiphy_read -#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ - -#endif /* _MV88E61XX_H */ diff --git a/include/netdev.h b/include/netdev.h index de74b9a..37a6549 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -139,64 +139,6 @@ static inline int pci_eth_init(bd_t *bis) return num; }
-/* - * Boards with mv88e61xx switch can use this by defining - * CONFIG_MV88E61XX_SWITCH in respective board configheader file - * the stuct and enums here are used to specify switch configuration params - */ -#if defined(CONFIG_MV88E61XX_SWITCH) - -/* constants for any 88E61xx switch */ -#define MV88E61XX_MAX_PORTS_NUM 6 - -enum mv88e61xx_cfg_mdip { - MV88E61XX_MDIP_NOCHANGE, - MV88E61XX_MDIP_REVERSE -}; - -enum mv88e61xx_cfg_ledinit { - MV88E61XX_LED_INIT_DIS, - MV88E61XX_LED_INIT_EN -}; - -enum mv88e61xx_cfg_rgmiid { - MV88E61XX_RGMII_DELAY_DIS, - MV88E61XX_RGMII_DELAY_EN -}; - -enum mv88e61xx_cfg_prtstt { - MV88E61XX_PORTSTT_DISABLED, - MV88E61XX_PORTSTT_BLOCKING, - MV88E61XX_PORTSTT_LEARNING, - MV88E61XX_PORTSTT_FORWARDING -}; - -struct mv88e61xx_config { - char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; - enum mv88e61xx_cfg_rgmiid rgmii_delay; - enum mv88e61xx_cfg_prtstt portstate; - enum mv88e61xx_cfg_ledinit led_init; - enum mv88e61xx_cfg_mdip mdip; - u32 ports_enabled; - u8 cpuport; -}; - -/* - * Common mappings for Internal VLANs - * These mappings consider that all ports are useable; the driver - * will mask inexistent/unused ports. - */ - -/* Switch mode : routes any port to any port */ -#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } - -/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ -#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } - -int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); -#endif /* CONFIG_MV88E61XX_SWITCH */ - struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device;
On Mon, Dec 21, 2015 at 3:45 PM, Kevin Smith kevin.smith@elecsyscorp.com wrote:
No boards are using this driver. Remove in preparation for a new driver with integrated PHY support.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de
drivers/net/phy/mv88e61xx.c | 537 -------------------------------------------- drivers/net/phy/mv88e61xx.h | 61 ----- include/netdev.h | 58 ----- 3 files changed, 656 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.c delete mode 100644 drivers/net/phy/mv88e61xx.h
Acked-by: Joe Hershberger joe.hershberger@ni.com
The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Prafulla Wadaskar prafulla@marvell.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de --- drivers/net/phy/mv88e61xx.c | 664 ++++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 1 + 3 files changed, 668 insertions(+) create mode 100644 drivers/net/phy/mv88e61xx.c
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 0000000..d24272e --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,664 @@ +/* + * (C) Copyright 2015 + * Elecsys Corporation <www.elecsyscorp.com> + * Kevin Smith kevin.smith@elecsyscorp.com + * + * Original driver: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar prafulla@marvell.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * PHY driver for mv88e61xx ethernet switches. + * + * This driver configures the mv88e61xx for basic use as a PHY. The switch + * supports a VLAN configuration that determines how traffic will be routed + * between the ports. This driver uses a simple configuration that routes + * traffic from each PHY port only to the CPU port, and from the CPU port to + * any PHY port. + * + * The configuration determines which PHY ports to activate using the + * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit + * 1 activates port 1, etc. Do not set the bit for the port the CPU is + * connected to unless it is connected over a PHY interface (not MII). + * + * This driver was written for and tested on the mv88e6176 with an SGMII + * connection. Other configurations should be supported, but some additions or + * changes may be required. + */ + +#include <common.h> +#include <errno.h> +#include <miiphy.h> +#include <netdev.h> + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +#define PORT_COUNT 7 +#define PORT_MASK ((1 << PORT_COUNT) - 1) + +/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_PORT(p) (0x10 + (p)) +#define DEVADDR_SERDES 0x0F +#define DEVADDR_GLOBAL_1 0x1B +#define DEVADDR_GLOBAL_2 0x1C + +/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CONTROL 0x04 +#define GLOBAL1_MONITOR_CONTROL 0x1A + +/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD 0x18 +#define GLOBAL2_REG_PHY_DATA 0x19 + +/* Port registers */ +#define PORT_REG_STATUS 0x00 +#define PORT_REG_PHYS_CONTROL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CONTROL 0x04 +#define PORT_REG_VLAN_MAP 0x06 +#define PORT_REG_VLAN_ID 0x07 + +/* Phy registers */ +#define PHY_REG_CONTROL1 0x10 +#define PHY_REG_STATUS1 0x11 +#define PHY_REG_PAGE 0x16 + +/* Serdes registers */ +#define SERDES_REG_CONTROL_1 0x10 + +/* Phy page numbers */ +#define PHY_PAGE_COPPER 0 +#define PHY_PAGE_SERDES 1 + +#define PHY_WRITE_CMD 0x9400 +#define PHY_READ_CMD 0x9800 + +/* PHY Status Register */ +#define PHY_REG_STATUS1_SPEED 0xc000 +#define PHY_REG_STATUS1_GBIT 0x8000 +#define PHY_REG_STATUS1_100 0x4000 +#define PHY_REG_STATUS1_DUPLEX 0x2000 +#define PHY_REG_STATUS1_SPDDONE 0x0800 +#define PHY_REG_STATUS1_LINK 0x0400 +#define PHY_REG_STATUS1_ENERGY 0x0010 + +/* Check for required macros */ +#ifndef CONFIG_MV88E61XX_PHY_PORTS +#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \ + to activate +#endif +#ifndef CONFIG_MV88E61XX_CPU_PORT +#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to +#endif + + +enum { + SWITCH_MODEL_6176, + /* Leave this last */ + SWITCH_MODEL_UNKNOWN +}; + +static u16 switch_model_ids[] = { + [SWITCH_MODEL_6176] = 0x176, +}; + + +/* Wait for the current SMI PHY command to complete */ +static int mv88e61xx_smi_wait(struct mii_dev *bus) +{ + int reg; + u32 timeout = 100; + + do { + reg = bus->read(bus, DEVADDR_GLOBAL_2, MDIO_DEVAD_NONE, + GLOBAL2_REG_PHY_CMD); + if (reg >= 0 && (reg & (1 << 15)) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + puts("SMI busy timeout\n"); + return -1; +} + + +/* Write a PHY register indirectly */ +static int mv88e61xx_phy_write_bus(struct mii_dev *bus, int addr, int devad, + int reg, u16 data) +{ + struct mii_dev *phys_bus; + + /* Retrieve the actual MII bus device from private data */ + phys_bus = (struct mii_dev *)bus->priv; + + phys_bus->write(phys_bus, DEVADDR_GLOBAL_2, devad, + GLOBAL2_REG_PHY_DATA, data); + phys_bus->write(phys_bus, DEVADDR_GLOBAL_2, devad, + GLOBAL2_REG_PHY_CMD, (PHY_WRITE_CMD | (addr << 5) | reg)); + + return mv88e61xx_smi_wait(phys_bus); +} + + +/* Read a PHY register indirectly */ +static int mv88e61xx_phy_read_bus(struct mii_dev *bus, int addr, int devad, + int reg) +{ + struct mii_dev *phys_bus; + int res; + + /* Retrieve the actual MII bus device from private data */ + phys_bus = (struct mii_dev *)bus->priv; + + phys_bus->write(phys_bus, DEVADDR_GLOBAL_2, devad, GLOBAL2_REG_PHY_CMD, + (PHY_READ_CMD | (addr << 5) | reg)); + + if (mv88e61xx_smi_wait(phys_bus)) + return -1; + + res = phys_bus->read(phys_bus, DEVADDR_GLOBAL_2, devad, + GLOBAL2_REG_PHY_DATA); + + return res; +} + + +static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, + int reg, u16 *val) +{ + int res; + + res = mv88e61xx_phy_read_bus(phydev->bus, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg); + if (res < 0) + return -1; + + *val = (u16)res; + return 0; +} + + +static int mv88e61xx_phy_write(struct phy_device *phydev, int phy, + int reg, u16 val) +{ + return mv88e61xx_phy_write_bus(phydev->bus, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg, val); +} + + +static int mv88e61xx_switch_read(struct phy_device *phydev, u8 addr, u8 reg, + u16 *val) +{ + struct mii_dev *bus; + int res; + + bus = phydev->bus->priv; + + res = bus->read(bus, addr, MDIO_DEVAD_NONE, reg); + if (res < 0) + return -1; + + *val = (u16)res; + + return 0; +} + + +static int mv88e61xx_switch_write(struct phy_device *phydev, u8 addr, u8 reg, + u16 val) +{ + struct mii_dev *bus; + + bus = phydev->bus->priv; + + return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, val); +} + + +static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg, + u16 *val) +{ + return mv88e61xx_switch_read(phydev, DEVADDR_PORT(port), reg, val); +} + + +static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg, + u16 val) +{ + return mv88e61xx_switch_write(phydev, DEVADDR_PORT(port), reg, val); +} + + +static int mv88e61xx_set_page(struct phy_device *phydev, u8 addr, u8 page) +{ + return mv88e61xx_phy_write(phydev, addr, PHY_REG_PAGE, page); +} + + +static u16 mv88e61xx_get_switch_model(struct phy_device *phydev) +{ + u16 id; + int i; + + if (mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID, &id)) + return -1; + id >>= 4; + + for (i = 0; i < ARRAY_SIZE(switch_model_ids); i++) { + if (id == switch_model_ids[i]) + return i; + } + + return SWITCH_MODEL_UNKNOWN; +} + + +static int mv88e61xx_parse_status(struct phy_device *phydev) +{ + unsigned int speed; + unsigned int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1); + + if ((mii_reg & PHY_REG_STATUS1_LINK) && + !(mii_reg & PHY_REG_STATUS1_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + phydev->link = 0; + break; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, + PHY_REG_STATUS1); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & PHY_REG_STATUS1_LINK) + phydev->link = 1; + else + phydev->link = 0; + } + + if (mii_reg & PHY_REG_STATUS1_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & PHY_REG_STATUS1_SPEED; + + switch (speed) { + case PHY_REG_STATUS1_GBIT: + phydev->speed = SPEED_1000; + break; + case PHY_REG_STATUS1_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + + +static int mv88e61xx_switch_reset(struct phy_device *phydev) +{ + int time; + int res; + u16 reg; + u8 port; + + /* Disable all ports */ + for (port = 0; port < PORT_COUNT; port++) { + if (mv88e61xx_port_read(phydev, port, PORT_REG_CONTROL, ®)) + return -1; + reg &= ~0x3; + if (mv88e61xx_port_write(phydev, port, PORT_REG_CONTROL, reg)) + return -1; + } + + /* Wait 2 ms for queues to drain */ + udelay(2000); + + /* Reset switch */ + if (mv88e61xx_switch_read(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CONTROL, ®)) + return -1; + reg |= 0x8000; + if (mv88e61xx_switch_write(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CONTROL, reg)) + return -1; + + /* Wait up to 1 second for switch reset complete */ + for (time = 1000; time; time--) { + res = mv88e61xx_switch_read(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CONTROL, ®); + if (res == 0 && ((reg & 0x8000) == 0)) + break; + udelay(1000); + } + if (!time) + return -1; + + return 0; +} + + +static int mv88e61xx_serdes_init(struct phy_device *phydev) +{ + u16 val; + + /* Serdes registers are on page 1 */ + if (mv88e61xx_set_page(phydev, DEVADDR_SERDES, 1)) + return -1; + + /* Powerup and reset. Disable auto-negotiation, as two MACs (CPU and + * switch) cannot negotiate with each other. */ + if (mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR, &val)) + return -1; + val &= ~(BMCR_PDOWN | BMCR_ANENABLE); + val |= BMCR_RESET; + if (mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val)) + return -1; + + /* 2 MACs cannot auto-negotiate, so we must force the link good */ + if (mv88e61xx_phy_read(phydev, DEVADDR_SERDES, SERDES_REG_CONTROL_1, + &val)) + return -1; + val |= 0x0400; + if (mv88e61xx_phy_write(phydev, DEVADDR_SERDES, SERDES_REG_CONTROL_1, + val)) + return -1; + + return 0; +} + + +static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) +{ + u16 val; + + if (mv88e61xx_port_read(phydev, port, PORT_REG_CONTROL, &val)) + return -1; + val |= 0x03; + if (mv88e61xx_port_write(phydev, port, PORT_REG_CONTROL, val)) + return -1; + + return 0; +} + + +static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, + u8 mask) +{ + u16 val; + + /* Set VID to port number plus one */ + if (mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID, &val)) + return -1; + val &= ~((1 << 12) - 1); + val |= port + 1; + if (mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val)) + return -1; + + /* Set VID mask */ + if (mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP, &val)) + return -1; + val &= ~PORT_MASK; + val |= (mask & PORT_MASK); + if (mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val)) + return -1; + + return 0; +} + + +static int mv88e61xx_set_cpu_port(struct phy_device *phydev) +{ + u16 val; + + /* Set CPUDest */ + if (mv88e61xx_switch_read(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_MONITOR_CONTROL, &val)) + return -1; + val &= ~(0xf << 4); + val |= (CONFIG_MV88E61XX_CPU_PORT << 4); + if (mv88e61xx_switch_write(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_MONITOR_CONTROL, val)) + return -1; + + /* Enable CPU port */ + if (mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT)) + return -1; + + /* Allow CPU to route to any port */ + val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT); + if (mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val)) + return -1; + + return 0; +} + + +static int mv88e61xx_switch_init(struct phy_device *phydev) +{ + static int init; + + if (init) + return 0; + + if (mv88e61xx_switch_reset(phydev)) + return -1; + + if (mv88e61xx_set_cpu_port(phydev)) + return -1; + + /* Only the 6176 has the SERDES interface */ + if (mv88e61xx_get_switch_model(phydev) == SWITCH_MODEL_6176) + if (mv88e61xx_serdes_init(phydev)) + return -1; + + init = 1; + + return 0; +} + + +static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy) +{ + u16 val; + + if (mv88e61xx_phy_read(phydev, phy, MII_BMCR, &val)) + return -1; + val &= ~(BMCR_PDOWN); + if (mv88e61xx_phy_write(phydev, phy, MII_BMCR, val)) + return -1; + + return 0; +} + + +static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) +{ + u16 val; + + /* Enable energy-detect sensing on PHY, used to determine when a PHY + * port is physically connected */ + if (mv88e61xx_phy_read(phydev, phy, PHY_REG_CONTROL1, &val)) + return -1; + val |= (0x3 << 8); + if (mv88e61xx_phy_write(phydev, phy, PHY_REG_CONTROL1, val)) + return -1; + + return 0; +} + + +static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) +{ + if (mv88e61xx_port_enable(phydev, phy)) + return -1; + if (mv88e61xx_port_set_vlan(phydev, phy, + 1 << CONFIG_MV88E61XX_CPU_PORT)) + return -1; + + return 0; +} + + +static int mv88e61xx_probe(struct phy_device *phydev) +{ + struct mii_dev *mii_dev; + + /* This device requires indirect reads/writes to the PHY registers + * which the generic PHY code can't handle. Make a fake MII device to + * handle reads/writes */ + mii_dev = mdio_alloc(); + if (!mii_dev) + return -1; + + /* Store the actual bus in the fake mii device */ + mii_dev->priv = phydev->bus; + strncpy(mii_dev->name, "mv88e61xx_protocol", sizeof(mii_dev->name)); + mii_dev->read = mv88e61xx_phy_read_bus; + mii_dev->write = mv88e61xx_phy_write_bus; + + /* Replace the bus with the fake device */ + phydev->bus = mii_dev; + + return 0; +} + + +static int mv88e61xx_phy_config(struct phy_device *phydev) +{ + int mac_addr; + int i; + + if (mv88e61xx_switch_init(phydev)) + return -1; + + mac_addr = phydev->addr; + + for (i = 0; i < PORT_COUNT; i++) { + if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { + phydev->addr = i; + mv88e61xx_phy_enable(phydev, i); + mv88e61xx_phy_setup(phydev, i); + mv88e61xx_phy_config_port(phydev, i); + + genphy_config_aneg(phydev); + phy_reset(phydev); + } + } + + phydev->addr = mac_addr; + + return 0; +} + + +static int mv88e61xx_phy_is_connected(struct phy_device *phydev) +{ + u16 val; + + if (mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1, &val)) + return 0; + + /* After reset, the energy detect signal remains high for a few seconds + * regardless of whether a cable is connected. This function will + * return false positives during this time. */ + return (val & PHY_REG_STATUS1_ENERGY) == 0; +} + + +static int mv88e61xx_phy_startup(struct phy_device *phydev) +{ + int i; + int mac_addr; + int link = 0; + + mac_addr = phydev->addr; + for (i = 0; i < PORT_COUNT; i++) { + if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { + phydev->addr = i; + if (!mv88e61xx_phy_is_connected(phydev)) + continue; + genphy_update_link(phydev); + mv88e61xx_parse_status(phydev); + link = (link || phydev->link); + } + } + phydev->addr = mac_addr; + phydev->link = link; + + if (mv88e61xx_get_switch_model(phydev) == SWITCH_MODEL_6176) { + /* Configure MAC to the speed of the SGMII interface */ + phydev->speed = SPEED_1000; + phydev->duplex = DUPLEX_FULL; + } + + return 0; +} + + +static struct phy_driver mv88e61xx_driver = { + .name = "Marvell MV88E61xx", + .uid = 0x01410eb1, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + + +int phy_mv88e61xx_init(void) +{ + phy_register(&mv88e61xx_driver); + + return 0; +} + + +/* Overload weak get_phy_id definition since we need non-standard functions + * to read PHY registers */ +int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{ + struct mii_dev fake_bus; + int phy_reg; + + fake_bus.priv = bus; + + phy_reg = mv88e61xx_phy_read_bus(&fake_bus, addr, devad, MII_PHYSID1); + if (phy_reg < 0) + return -EIO; + + *phy_id = phy_reg << 16; + + phy_reg = mv88e61xx_phy_read_bus(&fake_bus, addr, devad, MII_PHYSID2); + if (phy_reg < 0) + return -EIO; + + *phy_id |= (phy_reg & 0xffff); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 51b5746..077c9f5 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -446,6 +446,9 @@ static LIST_HEAD(phy_drivers);
int phy_init(void) { +#ifdef CONFIG_MV88E61XX_SWITCH + phy_mv88e61xx_init(); +#endif #ifdef CONFIG_PHY_AQUANTIA phy_aquantia_init(); #endif diff --git a/include/phy.h b/include/phy.h index 66cf61b..7cec9b8 100644 --- a/include/phy.h +++ b/include/phy.h @@ -238,6 +238,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_mv88e61xx_init(void); int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void);
Hi Kevin,
On Mon, Dec 21, 2015 at 3:45 PM, Kevin Smith kevin.smith@elecsyscorp.com wrote:
The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Prafulla Wadaskar prafulla@marvell.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de
drivers/net/phy/mv88e61xx.c | 664 ++++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 1 + 3 files changed, 668 insertions(+) create mode 100644 drivers/net/phy/mv88e61xx.c
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 0000000..d24272e --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,664 @@ +/*
- (C) Copyright 2015
- Elecsys Corporation <www.elecsyscorp.com>
- Kevin Smith kevin.smith@elecsyscorp.com
- Original driver:
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Prafulla Wadaskar prafulla@marvell.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/*
- PHY driver for mv88e61xx ethernet switches.
- This driver configures the mv88e61xx for basic use as a PHY. The switch
- supports a VLAN configuration that determines how traffic will be routed
- between the ports. This driver uses a simple configuration that routes
- traffic from each PHY port only to the CPU port, and from the CPU port to
- any PHY port.
- The configuration determines which PHY ports to activate using the
- CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
- 1 activates port 1, etc. Do not set the bit for the port the CPU is
- connected to unless it is connected over a PHY interface (not MII).
- This driver was written for and tested on the mv88e6176 with an SGMII
- connection. Other configurations should be supported, but some additions or
- changes may be required.
- */
+#include <common.h> +#include <errno.h> +#include <miiphy.h> +#include <netdev.h>
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+#define PORT_COUNT 7 +#define PORT_MASK ((1 << PORT_COUNT) - 1)
+/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_PORT(p) (0x10 + (p)) +#define DEVADDR_SERDES 0x0F +#define DEVADDR_GLOBAL_1 0x1B +#define DEVADDR_GLOBAL_2 0x1C
+/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CONTROL 0x04 +#define GLOBAL1_MONITOR_CONTROL 0x1A
+/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD 0x18 +#define GLOBAL2_REG_PHY_DATA 0x19
+/* Port registers */ +#define PORT_REG_STATUS 0x00 +#define PORT_REG_PHYS_CONTROL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CONTROL 0x04 +#define PORT_REG_VLAN_MAP 0x06 +#define PORT_REG_VLAN_ID 0x07
+/* Phy registers */ +#define PHY_REG_CONTROL1 0x10 +#define PHY_REG_STATUS1 0x11 +#define PHY_REG_PAGE 0x16
+/* Serdes registers */ +#define SERDES_REG_CONTROL_1 0x10
+/* Phy page numbers */ +#define PHY_PAGE_COPPER 0 +#define PHY_PAGE_SERDES 1
+#define PHY_WRITE_CMD 0x9400 +#define PHY_READ_CMD 0x9800
Please at least include a comment that these are commands written to the GLOBAL2_REG_PHY_CMD and are made selecting...
Enable Busy (start), Clause 22 frames, and write / read.
Even better would be to also use names that are a closer to the register they apply to, though that can get a bit long with these windowed interfaces. Maybe GLOBAL2_REG_PHY_WRITE_CMD and GLOBAL2_REG_PHY_READ_CMD?
Even better than that would be constants for the bitfield values that are ORed in these commands.
+/* PHY Status Register */ +#define PHY_REG_STATUS1_SPEED 0xc000 +#define PHY_REG_STATUS1_GBIT 0x8000 +#define PHY_REG_STATUS1_100 0x4000 +#define PHY_REG_STATUS1_DUPLEX 0x2000 +#define PHY_REG_STATUS1_SPDDONE 0x0800 +#define PHY_REG_STATUS1_LINK 0x0400 +#define PHY_REG_STATUS1_ENERGY 0x0010
+/* Check for required macros */ +#ifndef CONFIG_MV88E61XX_PHY_PORTS +#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
to activate+#endif +#ifndef CONFIG_MV88E61XX_CPU_PORT +#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to +#endif
+enum {
SWITCH_MODEL_6176,/* Leave this last */SWITCH_MODEL_UNKNOWN+};
+static u16 switch_model_ids[] = {
[SWITCH_MODEL_6176] = 0x176,+};
+/* Wait for the current SMI PHY command to complete */ +static int mv88e61xx_smi_wait(struct mii_dev *bus) +{
int reg;u32 timeout = 100;do {reg = bus->read(bus, DEVADDR_GLOBAL_2, MDIO_DEVAD_NONE,GLOBAL2_REG_PHY_CMD);if (reg >= 0 && (reg & (1 << 15)) == 0)
Please add a constant for SMI_BUSY instead of "1 << 15".
return 0;mdelay(1);} while (--timeout);puts("SMI busy timeout\n");return -1;
-ETIMEDOUT?
+}
Generally avoid multiple consecutive blank lines unless it really helps to structure the code.
+/* Write a PHY register indirectly */
It would be good to make these "indirect" functions more clear.
+static int mv88e61xx_phy_write_bus(struct mii_dev *bus, int addr, int devad,
Maybe this should be called mv88e61xx_phy_write_external or mv88e61xx_phy_write_indirect.
int reg, u16 data)+{
struct mii_dev *phys_bus;
Why "phys_bus"? Isn't it an mdio_bus? Maybe that would be a better name.
/* Retrieve the actual MII bus device from private data */
This comment doesn't help. With a well named local var, that will be self-explanatory.
phys_bus = (struct mii_dev *)bus->priv;phys_bus->write(phys_bus, DEVADDR_GLOBAL_2, devad,GLOBAL2_REG_PHY_DATA, data);phys_bus->write(phys_bus, DEVADDR_GLOBAL_2, devad,GLOBAL2_REG_PHY_CMD, (PHY_WRITE_CMD | (addr << 5) | reg));
Reg and addr need to be masked to only include the valid bits (i.e. make sure reg < 32). This is done cleanly by building up the value with the functions in include/bitfield.h
return mv88e61xx_smi_wait(phys_bus);+}
Same comments for read...
+/* Read a PHY register indirectly */ +static int mv88e61xx_phy_read_bus(struct mii_dev *bus, int addr, int devad,
int reg)+{
struct mii_dev *phys_bus;int res;/* Retrieve the actual MII bus device from private data */phys_bus = (struct mii_dev *)bus->priv;phys_bus->write(phys_bus, DEVADDR_GLOBAL_2, devad, GLOBAL2_REG_PHY_CMD,(PHY_READ_CMD | (addr << 5) | reg));if (mv88e61xx_smi_wait(phys_bus))return -1;
Probably throughout, you should be passing error codes along instead of replacing them with -1.
res = phys_bus->read(phys_bus, DEVADDR_GLOBAL_2, devad,GLOBAL2_REG_PHY_DATA);return res;+}
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy,
int reg, u16 *val)+{
int res;res = mv88e61xx_phy_read_bus(phydev->bus, DEVADDR_PHY(phy),MDIO_DEVAD_NONE, reg);if (res < 0)return -1;*val = (u16)res;return 0;+}
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
int reg, u16 val)+{
return mv88e61xx_phy_write_bus(phydev->bus, DEVADDR_PHY(phy),MDIO_DEVAD_NONE, reg, val);+}
+static int mv88e61xx_switch_read(struct phy_device *phydev, u8 addr, u8 reg,
u16 *val)+{
struct mii_dev *bus;int res;bus = phydev->bus->priv;res = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);if (res < 0)return -1;
-EIO? Or probably just pass whatever was returned.
*val = (u16)res;return 0;+}
+static int mv88e61xx_switch_write(struct phy_device *phydev, u8 addr, u8 reg,
u16 val)+{
struct mii_dev *bus;bus = phydev->bus->priv;
This is a bit ugly to read... bus = bus->priv. Maybe use mdio_bus for the local var like above?
return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, val);+}
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg,
u16 *val)+{
return mv88e61xx_switch_read(phydev, DEVADDR_PORT(port), reg, val);+}
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
u16 val)+{
return mv88e61xx_switch_write(phydev, DEVADDR_PORT(port), reg, val);+}
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 addr, u8 page) +{
return mv88e61xx_phy_write(phydev, addr, PHY_REG_PAGE, page);+}
+static u16 mv88e61xx_get_switch_model(struct phy_device *phydev) +{
u16 id;int i;if (mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID, &id))return -1;id >>= 4;for (i = 0; i < ARRAY_SIZE(switch_model_ids); i++) {if (id == switch_model_ids[i])return i;}return SWITCH_MODEL_UNKNOWN;+}
+static int mv88e61xx_parse_status(struct phy_device *phydev) +{
unsigned int speed;unsigned int mii_reg;mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);if ((mii_reg & PHY_REG_STATUS1_LINK) &&!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {int i = 0;puts("Waiting for PHY realtime link");while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {/* Timeout reached ? */if (i > PHY_AUTONEGOTIATE_TIMEOUT) {puts(" TIMEOUT !\n");phydev->link = 0;break;}if ((i++ % 1000) == 0)putc('.');udelay(1000);mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,PHY_REG_STATUS1);}puts(" done\n");udelay(500000); /* another 500 ms (results in faster booting) */} else {if (mii_reg & PHY_REG_STATUS1_LINK)phydev->link = 1;elsephydev->link = 0;}if (mii_reg & PHY_REG_STATUS1_DUPLEX)phydev->duplex = DUPLEX_FULL;elsephydev->duplex = DUPLEX_HALF;speed = mii_reg & PHY_REG_STATUS1_SPEED;switch (speed) {case PHY_REG_STATUS1_GBIT:phydev->speed = SPEED_1000;break;case PHY_REG_STATUS1_100:phydev->speed = SPEED_100;break;default:phydev->speed = SPEED_10;break;}return 0;+}
+static int mv88e61xx_switch_reset(struct phy_device *phydev) +{
int time;int res;u16 reg;u8 port;/* Disable all ports */for (port = 0; port < PORT_COUNT; port++) {if (mv88e61xx_port_read(phydev, port, PORT_REG_CONTROL, ®))return -1;reg &= ~0x3;if (mv88e61xx_port_write(phydev, port, PORT_REG_CONTROL, reg))return -1;}/* Wait 2 ms for queues to drain */udelay(2000);/* Reset switch */if (mv88e61xx_switch_read(phydev, DEVADDR_GLOBAL_1,GLOBAL1_CONTROL, ®))return -1;reg |= 0x8000;
For all bitwise operations like this you should be using the functions from include/bitfield.h
if (mv88e61xx_switch_write(phydev, DEVADDR_GLOBAL_1,GLOBAL1_CONTROL, reg))return -1;/* Wait up to 1 second for switch reset complete */for (time = 1000; time; time--) {res = mv88e61xx_switch_read(phydev, DEVADDR_GLOBAL_1,GLOBAL1_CONTROL, ®);if (res == 0 && ((reg & 0x8000) == 0))break;udelay(1000);}if (!time)return -1;
-ETIMEDOUT?
return 0;+}
+static int mv88e61xx_serdes_init(struct phy_device *phydev) +{
u16 val;/* Serdes registers are on page 1 */if (mv88e61xx_set_page(phydev, DEVADDR_SERDES, 1))return -1;/* Powerup and reset. Disable auto-negotiation, as two MACs (CPU and* switch) cannot negotiate with each other. */
Multi-line comment format: /* * */
if (mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR, &val))return -1;val &= ~(BMCR_PDOWN | BMCR_ANENABLE);val |= BMCR_RESET;if (mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val))return -1;/* 2 MACs cannot auto-negotiate, so we must force the link good */if (mv88e61xx_phy_read(phydev, DEVADDR_SERDES, SERDES_REG_CONTROL_1,&val))return -1;val |= 0x0400;if (mv88e61xx_phy_write(phydev, DEVADDR_SERDES, SERDES_REG_CONTROL_1,val))return -1;return 0;+}
+static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) +{
u16 val;if (mv88e61xx_port_read(phydev, port, PORT_REG_CONTROL, &val))return -1;val |= 0x03;if (mv88e61xx_port_write(phydev, port, PORT_REG_CONTROL, val))return -1;return 0;+}
+static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
u8 mask)+{
u16 val;/* Set VID to port number plus one */if (mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID, &val))return -1;val &= ~((1 << 12) - 1);val |= port + 1;if (mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val))return -1;/* Set VID mask */if (mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP, &val))return -1;val &= ~PORT_MASK;val |= (mask & PORT_MASK);if (mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val))return -1;return 0;+}
+static int mv88e61xx_set_cpu_port(struct phy_device *phydev) +{
u16 val;/* Set CPUDest */if (mv88e61xx_switch_read(phydev, DEVADDR_GLOBAL_1,GLOBAL1_MONITOR_CONTROL, &val))return -1;val &= ~(0xf << 4);val |= (CONFIG_MV88E61XX_CPU_PORT << 4);if (mv88e61xx_switch_write(phydev, DEVADDR_GLOBAL_1,GLOBAL1_MONITOR_CONTROL, val))return -1;/* Enable CPU port */if (mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT))return -1;/* Allow CPU to route to any port */val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);if (mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val))return -1;return 0;+}
+static int mv88e61xx_switch_init(struct phy_device *phydev) +{
static int init;if (init)return 0;if (mv88e61xx_switch_reset(phydev))return -1;if (mv88e61xx_set_cpu_port(phydev))return -1;/* Only the 6176 has the SERDES interface */if (mv88e61xx_get_switch_model(phydev) == SWITCH_MODEL_6176)if (mv88e61xx_serdes_init(phydev))return -1;init = 1;return 0;+}
+static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy) +{
u16 val;if (mv88e61xx_phy_read(phydev, phy, MII_BMCR, &val))return -1;val &= ~(BMCR_PDOWN);if (mv88e61xx_phy_write(phydev, phy, MII_BMCR, val))return -1;return 0;+}
+static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) +{
u16 val;/* Enable energy-detect sensing on PHY, used to determine when a PHY* port is physically connected */if (mv88e61xx_phy_read(phydev, phy, PHY_REG_CONTROL1, &val))return -1;val |= (0x3 << 8);if (mv88e61xx_phy_write(phydev, phy, PHY_REG_CONTROL1, val))return -1;return 0;+}
+static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) +{
if (mv88e61xx_port_enable(phydev, phy))return -1;if (mv88e61xx_port_set_vlan(phydev, phy,1 << CONFIG_MV88E61XX_CPU_PORT))return -1;return 0;+}
+static int mv88e61xx_probe(struct phy_device *phydev) +{
struct mii_dev *mii_dev;/* This device requires indirect reads/writes to the PHY registers* which the generic PHY code can't handle. Make a fake MII device to* handle reads/writes */mii_dev = mdio_alloc();if (!mii_dev)return -1;
-ENOMEM
/* Store the actual bus in the fake mii device */mii_dev->priv = phydev->bus;strncpy(mii_dev->name, "mv88e61xx_protocol", sizeof(mii_dev->name));mii_dev->read = mv88e61xx_phy_read_bus;mii_dev->write = mv88e61xx_phy_write_bus;/* Replace the bus with the fake device */
Fake how? This is a confusing comment to me as written.
phydev->bus = mii_dev;return 0;+}
+static int mv88e61xx_phy_config(struct phy_device *phydev) +{
int mac_addr;int i;if (mv88e61xx_switch_init(phydev))return -1;
Pass the returned value through.
mac_addr = phydev->addr;for (i = 0; i < PORT_COUNT; i++) {if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {phydev->addr = i;mv88e61xx_phy_enable(phydev, i);mv88e61xx_phy_setup(phydev, i);mv88e61xx_phy_config_port(phydev, i);
These all return status, but are ignored.
genphy_config_aneg(phydev);phy_reset(phydev);}}phydev->addr = mac_addr;return 0;+}
+static int mv88e61xx_phy_is_connected(struct phy_device *phydev) +{
u16 val;if (mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1, &val))return 0;/* After reset, the energy detect signal remains high for a few seconds* regardless of whether a cable is connected. This function will* return false positives during this time. */
This is OK?
return (val & PHY_REG_STATUS1_ENERGY) == 0;+}
+static int mv88e61xx_phy_startup(struct phy_device *phydev) +{
int i;int mac_addr;int link = 0;mac_addr = phydev->addr;
This is a confusing name to use here. I assume the meaning it that it is the phy address of the port wired up to the mac on this host. However, the name overloads a common name for the L2 address of an Ethernet MAC.
Maybe use something like phy_addr_for_mac?
for (i = 0; i < PORT_COUNT; i++) {if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {phydev->addr = i;if (!mv88e61xx_phy_is_connected(phydev))continue;genphy_update_link(phydev);mv88e61xx_parse_status(phydev);link = (link || phydev->link);}}phydev->addr = mac_addr;phydev->link = link;if (mv88e61xx_get_switch_model(phydev) == SWITCH_MODEL_6176) {/* Configure MAC to the speed of the SGMII interface */phydev->speed = SPEED_1000;phydev->duplex = DUPLEX_FULL;}return 0;+}
+static struct phy_driver mv88e61xx_driver = {
.name = "Marvell MV88E61xx",.uid = 0x01410eb1,.mask = 0xfffffff0,.features = PHY_GBIT_FEATURES,.probe = mv88e61xx_probe,.config = mv88e61xx_phy_config,.startup = mv88e61xx_phy_startup,.shutdown = &genphy_shutdown,+};
+int phy_mv88e61xx_init(void) +{
phy_register(&mv88e61xx_driver);return 0;+}
+/* Overload weak get_phy_id definition since we need non-standard functions
- to read PHY registers */
Multi-line comment format.
+int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{
struct mii_dev fake_bus;int phy_reg;fake_bus.priv = bus;phy_reg = mv88e61xx_phy_read_bus(&fake_bus, addr, devad, MII_PHYSID1);if (phy_reg < 0)return -EIO;*phy_id = phy_reg << 16;phy_reg = mv88e61xx_phy_read_bus(&fake_bus, addr, devad, MII_PHYSID2);if (phy_reg < 0)return -EIO;*phy_id |= (phy_reg & 0xffff);return 0;+} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 51b5746..077c9f5 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -446,6 +446,9 @@ static LIST_HEAD(phy_drivers);
int phy_init(void) { +#ifdef CONFIG_MV88E61XX_SWITCH
phy_mv88e61xx_init();+#endif #ifdef CONFIG_PHY_AQUANTIA phy_aquantia_init(); #endif diff --git a/include/phy.h b/include/phy.h index 66cf61b..7cec9b8 100644 --- a/include/phy.h +++ b/include/phy.h @@ -238,6 +238,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_mv88e61xx_init(void); int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void); -- 2.4.6 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi Joe,
Thanks for the review. ACK to all comments. A few clarifications are included below. I will submit a v3, including multichip addressing for Albert's platform.
On 01/26/2016 06:11 PM, Joe Hershberger wrote:
int reg, u16 data)+{
struct mii_dev *phys_bus;Why "phys_bus"? Isn't it an mdio_bus? Maybe that would be a better name.
Agreed. This is extracting the actual mdio bus from the "fake" indirect mii device (see below). I will change to a better name.
+static int mv88e61xx_probe(struct phy_device *phydev) +{
struct mii_dev *mii_dev;/* This device requires indirect reads/writes to the PHY registers* which the generic PHY code can't handle. Make a fake MII device to* handle reads/writes */mii_dev = mdio_alloc();if (!mii_dev)return -1;/* Store the actual bus in the fake mii device */mii_dev->priv = phydev->bus;strncpy(mii_dev->name, "mv88e61xx_protocol", sizeof(mii_dev->name));mii_dev->read = mv88e61xx_phy_read_bus;mii_dev->write = mv88e61xx_phy_write_bus;/* Replace the bus with the fake device */Fake how? This is a confusing comment to me as written.
The genphy functions assume that they can write to the PHY directly using the MII bus, and the address it uses is the address of a register. This is not the case for this chip with multiple PHY interfaces, which have to be accessed indirectly. To handle this, I have created a "fake" mii_dev whose read/write functions are the indirection functions, and stored the actual mdio_bus in the private data for the "fake" device, which is then used by the indirect functions. This allows this driver to make use of common genphy stuff where appropriate. Maybe "wrapper" or "indirect bus" is a better name for it. Let me know if you have a preference or better idea.
mac_addr = phydev->addr;for (i = 0; i < PORT_COUNT; i++) {if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {phydev->addr = i;mv88e61xx_phy_enable(phydev, i);mv88e61xx_phy_setup(phydev, i);mv88e61xx_phy_config_port(phydev, i);These all return status, but are ignored.
Even if one fails, it seems appropriate to me to continue initializing the others and not bail completely. Should I catch the error, print a warning and "continue" in the loop? Or is completely bailing the right thing to do? If there are some errors, but other successes, what should the function return?
/* After reset, the energy detect signal remains high for a few seconds* regardless of whether a cable is connected. This function will* return false positives during this time. */This is OK?
Yes. This is used to skip the autonegotiation process if nothing is plugged into the port. If you have 5-6 ports enabled but only one cable plugged in, waiting for all the other autonegotiation timeouts takes a long time. This tries to be smart and not wait when nothing is plugged in. A false positive just tries to autonegotiate. After the first autonegotiate timeout, the energy detection hysteresis (or whatever) has corrected itself, so you only have to wait for one.
Thanks, Kevin
Hello Kevin,
On Wed, 27 Jan 2016 16:29:42 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
Hi Joe,
On 01/26/2016 06:11 PM, Joe Hershberger wrote:
/* Replace the bus with the fake device */Fake how? This is a confusing comment to me as written.
The genphy functions assume that they can write to the PHY directly using the MII bus, and the address it uses is the address of a register. This is not the case for this chip with multiple PHY interfaces, which have to be accessed indirectly. To handle this, I have created a "fake" mii_dev whose read/write functions are the indirection functions, and stored the actual mdio_bus in the private data for the "fake" device, which is then used by the indirect functions. This allows this driver to make use of common genphy stuff where appropriate. Maybe "wrapper" or "indirect bus" is a better name for it. Let me know if you have a preference or better idea.
"Indirect bus" is better IMO, as it gives a clue about what actually happens.
mac_addr = phydev->addr;for (i = 0; i < PORT_COUNT; i++) {if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {phydev->addr = i;mv88e61xx_phy_enable(phydev, i);mv88e61xx_phy_setup(phydev, i);mv88e61xx_phy_config_port(phydev, i);These all return status, but are ignored.
Even if one fails, it seems appropriate to me to continue initializing the others and not bail completely. Should I catch the error, print a warning and "continue" in the loop? Or is completely bailing the right thing to do? If there are some errors, but other successes, what should the function return?
Warn for each port switch initialization failure, bail out if no port could be initialized?
Thanks, Kevin
Amicalement,
On Wed, Jan 27, 2016 at 11:28 AM, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hello Kevin,
On Wed, 27 Jan 2016 16:29:42 +0000, Kevin Smith kevin.smith@elecsyscorp.com wrote:
Hi Joe,
On 01/26/2016 06:11 PM, Joe Hershberger wrote:
/* Replace the bus with the fake device */Fake how? This is a confusing comment to me as written.
The genphy functions assume that they can write to the PHY directly using the MII bus, and the address it uses is the address of a register. This is not the case for this chip with multiple PHY interfaces, which have to be accessed indirectly. To handle this, I have created a "fake" mii_dev whose read/write functions are the indirection functions, and stored the actual mdio_bus in the private data for the "fake" device, which is then used by the indirect functions. This allows this driver to make use of common genphy stuff where appropriate. Maybe "wrapper" or "indirect bus" is a better name for it. Let me know if you have a preference or better idea.
"Indirect bus" is better IMO, as it gives a clue about what actually happens.
Sounds good to me. May as well use the same nomenclature for the read and write functions.
mac_addr = phydev->addr;for (i = 0; i < PORT_COUNT; i++) {if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {phydev->addr = i;mv88e61xx_phy_enable(phydev, i);mv88e61xx_phy_setup(phydev, i);mv88e61xx_phy_config_port(phydev, i);These all return status, but are ignored.
Even if one fails, it seems appropriate to me to continue initializing the others and not bail completely. Should I catch the error, print a warning and "continue" in the loop? Or is completely bailing the right thing to do? If there are some errors, but other successes, what should the function return?
Warn for each port switch initialization failure, bail out if no port could be initialized?
I like it.
Cheers, -Joe
The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is a complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added.
This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports.
This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated.
Changes in v3: * Clean up chip register accessor functions to be more clear. * Support multi-chip addressing mode in the way that Linux DSA does * Detect hardware strap configuration for CPU port settings like Linux DSA does * Remove some unnecessary serdes settings * Use functions in bitfield.h to clean up bit operations * Use correct error return codes * Comment/code formatting improvements and clarifications
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Prafulla Wadaskar prafulla@marvell.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de
Kevin Smith (2): net: Remove unused mv88e61xx switch driver net: phy: Add PHY driver for mv88e61xx switches
drivers/net/phy/mv88e61xx.c | 1322 +++++++++++++++++++++++++++++-------------- drivers/net/phy/mv88e61xx.h | 61 -- drivers/net/phy/phy.c | 3 + include/netdev.h | 58 -- include/phy.h | 1 + 5 files changed, 905 insertions(+), 540 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.h
No boards are using this driver. Remove in preparation for a new driver with integrated PHY support.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Joe Hershberger joe.hershberger@ni.com Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de --- drivers/net/phy/mv88e61xx.c | 537 -------------------------------------------- drivers/net/phy/mv88e61xx.h | 61 ----- include/netdev.h | 58 ----- 3 files changed, 656 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.c delete mode 100644 drivers/net/phy/mv88e61xx.h
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c deleted file mode 100644 index 302abe8..0000000 --- a/drivers/net/phy/mv88e61xx.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include "mv88e61xx.h" - -/* - * Uncomment either of the following line for local debug control; - * otherwise global debug control will apply. - */ - -/* #undef DEBUG */ -/* #define DEBUG */ - -#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE -/* Chip Address mode - * The Switch support two modes of operation - * 1. single chip mode and - * 2. Multi-chip mode - * Refer section 9.2 &9.3 in chip datasheet-02 for more details - * - * By default single chip mode is configured - * multichip mode operation can be configured in board header - */ -static int mv88e61xx_busychk_multic(char *name, u32 devaddr) -{ - u16 reg = 0; - u32 timeout = MV88E61XX_PHY_TIMEOUT; - - /* Poll till SMIBusy bit is clear */ - do { - miiphy_read(name, devaddr, 0x0, ®); - if (timeout-- == 0) { - printf("SMI busy timeout\n"); - return -1; - } - } while (reg & (1 << 15)); - return 0; -} - -static void mv88e61xx_switch_write(char *name, u32 phy_adr, - u32 reg_ofs, u16 data) -{ - u16 mii_dev_addr; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { - printf("Error..could not read PHY dev address\n"); - return; - } - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Write data to Switch indirect data register */ - miiphy_write(name, mii_dev_addr, 0x1, data); - /* Write command to Switch indirect command register (write) */ - miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << - 15)); -} - -static void mv88e61xx_switch_read(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data) -{ - u16 mii_dev_addr; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { - printf("Error..could not read PHY dev address\n"); - return; - } - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Write command to Switch indirect command register (read) */ - miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 << - 15)); - mv88e61xx_busychk_multic(name, mii_dev_addr); - /* Read data from Switch indirect data register */ - miiphy_read(name, mii_dev_addr, 0x1, data); -} -#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ - -/* - * Convenience macros for switch device/port reads/writes - * These macros output valid 'mv88e61xx' U_BOOT_CMDs - */ - -#ifndef DEBUG -#define WR_SWITCH_REG wr_switch_reg -#define RD_SWITCH_REG rd_switch_reg -#define WR_SWITCH_PORT_REG(n, p, r, d) \ - WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) -#define RD_SWITCH_PORT_REG(n, p, r, d) \ - RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) -#else -static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) -{ - printf("mv88e61xx %s dev %02x reg %02x write %04x\n", - name, dev_adr, reg_ofs, data); - wr_switch_reg(name, dev_adr, reg_ofs, data); -} -static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) -{ - rd_switch_reg(name, dev_adr, reg_ofs, data); - printf("mv88e61xx %s dev %02x reg %02x read %04x\n", - name, dev_adr, reg_ofs, *data); -} -static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, - u16 data) -{ - printf("mv88e61xx %s port %02x reg %02x write %04x\n", - name, prt_adr, reg_ofs, data); - wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); -} -static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, - u16 *data) -{ - rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); - printf("mv88e61xx %s port %02x reg %02x read %04x\n", - name, prt_adr, reg_ofs, *data); -} -#endif - -/* - * Local functions to read/write registers on the switch PHYs. - * NOTE! This goes through switch, not direct miiphy, writes and reads! - */ - -/* - * Make sure SMIBusy bit cleared before another - * SMI operation can take place - */ -static int mv88e61xx_busychk(char *name) -{ - u16 reg = 0; - u32 timeout = MV88E61XX_PHY_TIMEOUT; - do { - rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, ®); - if (timeout-- == 0) { - printf("SMI busy timeout\n"); - return -1; - } - } while (reg & 1 << 15); /* busy mask */ - return 0; -} - -static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, - u32 reg, u16 data) -{ - /* write switch data reg then cmd reg then check completion */ - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, - data); - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, - (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); - return mv88e61xx_busychk(name); -} - -static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, - u32 reg, u16 *data) -{ - /* write switch cmd reg, check for completion */ - wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, - (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); - if (mv88e61xx_busychk(name)) - return -1; - /* read switch data reg and return success */ - rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); - return 0; -} - -/* - * Convenience macros for switch PHY reads/writes - */ - -#ifndef DEBUG -#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write -#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read -#else -static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, - u32 reg_ofs, u16 data) -{ - int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); - if (r) - printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", - name, phy_adr, reg_ofs); - else - printf("mv88e61xx %s phy %02x reg %02x write %04x\n", - name, phy_adr, reg_ofs, data); - return r; -} -static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data) -{ - int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); - if (r) - printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", - name, phy_adr, reg_ofs); - else - printf("mv88e61xx %s phy %02x reg %02x read %04x\n", - name, phy_adr, reg_ofs, *data); - return r; -} -#endif - -static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) -{ - u32 prt; - u16 reg; - char *name = swconfig->name; - u32 port_mask = swconfig->ports_enabled; - - /* apply internal vlan config */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - /* only for enabled ports */ - if ((1 << prt) & port_mask) { - /* take vlan map from swconfig */ - u8 vlanmap = swconfig->vlancfg[prt]; - /* remove disabled ports from vlan map */ - vlanmap &= swconfig->ports_enabled; - /* apply vlan map to port */ - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VMAP_REG, ®); - reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); - reg |= vlanmap; - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VMAP_REG, reg); - } - } -} - -/* - * Power up the specified port and reset PHY - */ -static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - /* Write Copper Specific control reg1 (0x10) for- - * Enable Phy power up - * Energy Detect on (sense&Xmit NLP Periodically - * reset other settings default - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) - return -1; - - /* Write PHY ctrl reg (0x0) to apply - * Phy reset (set bit 15 low) - * reset other default values - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) - return -1; - - return 0; -} - -/* - * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) - * is set to "On-1000Mb/s Link, Off Else" - * This function sets it to "On-Link, Blink-Activity, Off-NoLink" - * - * This is optional settings may be needed on some boards - * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s - * Link status - */ -static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - if (swconfig->led_init != MV88E61XX_LED_INIT_EN) - return 0; - - /* set page address to 3 */ - if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) - return -1; - - /* - * set LED Func Ctrl reg - * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink - */ - if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) - return -1; - - /* set page address to 0 */ - if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) - return -1; - - return 0; -} - -/* - * Reverse Transmit polarity for Media Dependent Interface - * Pins (MDIP) bits in Copper Specific Control Register 3 - * (Page 0, Reg 20 for each phy (except cpu port) - * Reference: Section 1.1 Switch datasheet-3 - * - * This is optional settings may be needed on some boards - * for PHY<->magnetics h/w tuning - */ -static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) -{ - char *name = swconfig->name; - - if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) - return 0; - - /*Reverse MDIP/N[3:0] bits */ - if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) - return -1; - - return 0; -} - -/* - * Marvell 88E61XX Switch initialization - */ -int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) -{ - u32 prt; - u16 reg; - char *idstr; - char *name = swconfig->name; - int time; - - if (miiphy_set_current_dev(name)) { - printf("%s failed\n", __FUNCTION__); - return -1; - } - - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { - swconfig->cpuport = (1 << 5); - printf("Invalid cpu port config, using default port5\n"); - } - - RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); - switch (reg &= 0xfff0) { - case 0x1610: - idstr = "88E6161"; - break; - case 0x1650: - idstr = "88E6165"; - break; - case 0x1210: - idstr = "88E6123"; - /* ports 2,3,4 not available */ - swconfig->ports_enabled &= 0x023; - break; - default: - /* Could not detect switch id */ - idstr = "88E61??"; - break; - } - - /* be sure all ports are disabled */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); - } - - /* wait 2 ms for queues to drain */ - udelay(2000); - - /* reset switch */ - RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); - reg |= 0x8000; - WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); - - /* wait up to 1 second for switch reset complete */ - for (time = 1000; time; time--) { - RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, - ®); - if ((reg & 0xc800) == 0xc800) - break; - udelay(1000); - } - if (!time) - return -1; - - /* Port based VLANs configuration */ - mv88e61xx_port_vlan_config(swconfig); - - if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 9.5 of chip datasheet-02 - */ - /*Force port link down */ - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); - /* configure port RGMII delay */ - WR_SWITCH_PORT_REG(name, 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); - RD_SWITCH_PORT_REG(name, 5, - MV88E61XX_RGMII_TIMECTRL_REG, ®); - WR_SWITCH_PORT_REG(name, 5, - MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); - WR_SWITCH_PORT_REG(name, 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); - /* Force port to RGMII FDX 1000Base then up */ - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); - WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); - } - - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - - /* configure port's PHY */ - if (!((1 << prt) & swconfig->cpuport)) { - /* port 4 has phy 6, not 4 */ - int phy = (prt == 4) ? 6 : prt; - if (mv88361xx_powerup(swconfig, phy)) - return -1; - if (mv88361xx_reverse_mdipn(swconfig, phy)) - return -1; - if (mv88361xx_led_init(swconfig, phy)) - return -1; - } - - /* set port VID to port+1 except for cpu port */ - if (!((1 << prt) & swconfig->cpuport)) { - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VID_REG, ®); - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_VID_REG, - (reg & ~1023) | (prt+1)); - } - - /*Program port state */ - RD_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_CTRL_REG, ®); - WR_SWITCH_PORT_REG(name, prt, - MV88E61XX_PRT_CTRL_REG, - reg | (swconfig->portstate & 0x03)); - - } - - printf("%s Initialized on %s\n", idstr, name); - return 0; -} - -#ifdef CONFIG_MV88E61XX_CMD -static int -do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *name, *endp; - int write = 0; - enum { dev, prt, phy } target = dev; - u32 addrlo, addrhi, addr; - u32 reglo, reghi, reg; - u16 data, rdata; - - if (argc < 7) - return -1; - - name = argv[1]; - - if (strcmp(argv[2], "phy") == 0) - target = phy; - else if (strcmp(argv[2], "port") == 0) - target = prt; - else if (strcmp(argv[2], "dev") != 0) - return 1; - - addrlo = simple_strtoul(argv[3], &endp, 16); - - if (!*endp) { - addrhi = addrlo; - } else { - while (*endp < '0' || *endp > '9') - endp++; - addrhi = simple_strtoul(endp, NULL, 16); - } - - reglo = simple_strtoul(argv[5], &endp, 16); - if (!*endp) { - reghi = reglo; - } else { - while (*endp < '0' || *endp > '9') - endp++; - reghi = simple_strtoul(endp, NULL, 16); - } - - if (strcmp(argv[6], "write") == 0) - write = 1; - else if (strcmp(argv[6], "read") != 0) - return 1; - - data = simple_strtoul(argv[7], NULL, 16); - - for (addr = addrlo; addr <= addrhi; addr++) { - for (reg = reglo; reg <= reghi; reg++) { - if (write) { - if (target == phy) - mv88e61xx_switch_miiphy_write( - name, addr, reg, data); - else if (target == prt) - wr_switch_reg(name, - addr+MV88E61XX_PRT_OFST, - reg, data); - else - wr_switch_reg(name, addr, reg, data); - } else { - if (target == phy) - mv88e61xx_switch_miiphy_read( - name, addr, reg, &rdata); - else if (target == prt) - rd_switch_reg(name, - addr+MV88E61XX_PRT_OFST, - reg, &rdata); - else - rd_switch_reg(name, addr, reg, &rdata); - printf("%s %s %s %02x %s %02x %s %04x\n", - argv[0], argv[1], argv[2], addr, - argv[4], reg, argv[6], rdata); - if (write && argc == 7 && rdata != data) - return 1; - } - } - } - return 0; -} - -U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, - "Read or write mv88e61xx switch registers", - "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n" - "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n" - " - read/write switch device, port or phy at (addr,reg)\n" - " addr=0..0x1C for dev, 0..5 for port or phy.\n" - " reg=0..0x1F.\n" - " data=0..0xFFFF (tested if present against actual read).\n" - " All numeric parameters are assumed to be hex.\n" - " <addr> and <<reg> arguments can be ranges (x..y)" -); -#endif /* CONFIG_MV88E61XX_CMD */ diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h deleted file mode 100644 index 9c62e4a..0000000 --- a/drivers/net/phy/mv88e61xx.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MV88E61XX_H -#define _MV88E61XX_H - -#include <miiphy.h> - -#define MV88E61XX_CPU_PORT 0x5 - -#define MV88E61XX_PHY_TIMEOUT 100000 - -/* port dev-addr (= port + 0x10) */ -#define MV88E61XX_PRT_OFST 0x10 -/* port registers */ -#define MV88E61XX_PCS_CTRL_REG 0x1 -#define MV88E61XX_PRT_CTRL_REG 0x4 -#define MV88E61XX_PRT_VMAP_REG 0x6 -#define MV88E61XX_PRT_VID_REG 0x7 -#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A - -/* global registers dev-addr */ -#define MV88E61XX_GLBREG_DEVADR 0x1B -/* global registers */ -#define MV88E61XX_SGSR 0x00 -#define MV88E61XX_SGCR 0x04 - -/* global 2 registers dev-addr */ -#define MV88E61XX_GLB2REG_DEVADR 0x1C -/* global 2 registers */ -#define MV88E61XX_PHY_CMD 0x18 -#define MV88E61XX_PHY_DATA 0x19 -/* global 2 phy commands */ -#define MV88E61XX_PHY_WRITE_CMD 0x9400 -#define MV88E61XX_PHY_READ_CMD 0x9800 - -#define MV88E61XX_BUSY_OFST 15 -#define MV88E61XX_MODE_OFST 12 -#define MV88E61XX_OP_OFST 10 -#define MV88E61XX_ADDR_OFST 5 - -#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE -static int mv88e61xx_busychk_multic(char *name, u32 devaddr); -static void mv88e61xx_switch_write(char *name, u32 phy_adr, - u32 reg_ofs, u16 data); -static void mv88e61xx_switch_read(char *name, u32 phy_adr, - u32 reg_ofs, u16 *data); -#define wr_switch_reg mv88e61xx_switch_write -#define rd_switch_reg mv88e61xx_switch_read -#else -/* switch appears a s simple PHY and can thus use miiphy */ -#define wr_switch_reg miiphy_write -#define rd_switch_reg miiphy_read -#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ - -#endif /* _MV88E61XX_H */ diff --git a/include/netdev.h b/include/netdev.h index 244f23f..7a211bc 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -134,64 +134,6 @@ static inline int pci_eth_init(bd_t *bis) return num; }
-/* - * Boards with mv88e61xx switch can use this by defining - * CONFIG_MV88E61XX_SWITCH in respective board configheader file - * the stuct and enums here are used to specify switch configuration params - */ -#if defined(CONFIG_MV88E61XX_SWITCH) - -/* constants for any 88E61xx switch */ -#define MV88E61XX_MAX_PORTS_NUM 6 - -enum mv88e61xx_cfg_mdip { - MV88E61XX_MDIP_NOCHANGE, - MV88E61XX_MDIP_REVERSE -}; - -enum mv88e61xx_cfg_ledinit { - MV88E61XX_LED_INIT_DIS, - MV88E61XX_LED_INIT_EN -}; - -enum mv88e61xx_cfg_rgmiid { - MV88E61XX_RGMII_DELAY_DIS, - MV88E61XX_RGMII_DELAY_EN -}; - -enum mv88e61xx_cfg_prtstt { - MV88E61XX_PORTSTT_DISABLED, - MV88E61XX_PORTSTT_BLOCKING, - MV88E61XX_PORTSTT_LEARNING, - MV88E61XX_PORTSTT_FORWARDING -}; - -struct mv88e61xx_config { - char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; - enum mv88e61xx_cfg_rgmiid rgmii_delay; - enum mv88e61xx_cfg_prtstt portstate; - enum mv88e61xx_cfg_ledinit led_init; - enum mv88e61xx_cfg_mdip mdip; - u32 ports_enabled; - u8 cpuport; -}; - -/* - * Common mappings for Internal VLANs - * These mappings consider that all ports are useable; the driver - * will mask inexistent/unused ports. - */ - -/* Switch mode : routes any port to any port */ -#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } - -/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ -#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } - -int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); -#endif /* CONFIG_MV88E61XX_SWITCH */ - struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device;
The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Prafulla Wadaskar prafulla@marvell.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de --- drivers/net/phy/mv88e61xx.c | 1017 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 1 + 3 files changed, 1021 insertions(+) create mode 100644 drivers/net/phy/mv88e61xx.c
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 0000000..74d5609 --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,1017 @@ +/* + * (C) Copyright 2015 + * Elecsys Corporation <www.elecsyscorp.com> + * Kevin Smith kevin.smith@elecsyscorp.com + * + * Original driver: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar prafulla@marvell.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * PHY driver for mv88e61xx ethernet switches. + * + * This driver configures the mv88e61xx for basic use as a PHY. The switch + * supports a VLAN configuration that determines how traffic will be routed + * between the ports. This driver uses a simple configuration that routes + * traffic from each PHY port only to the CPU port, and from the CPU port to + * any PHY port. + * + * The configuration determines which PHY ports to activate using the + * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit + * 1 activates port 1, etc. Do not set the bit for the port the CPU is + * connected to unless it is connected over a PHY interface (not MII). + * + * This driver was written for and tested on the mv88e6176 with an SGMII + * connection. Other configurations should be supported, but some additions or + * changes may be required. + */ + +#include <common.h> + +#include <bitfield.h> +#include <errno.h> +#include <malloc.h> +#include <miiphy.h> +#include <netdev.h> + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +#define PORT_COUNT 7 +#define PORT_MASK ((1 << PORT_COUNT) - 1) + +/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_PORT(p) (0x10 + (p)) +#define DEVADDR_SERDES 0x0F +#define DEVADDR_GLOBAL_1 0x1B +#define DEVADDR_GLOBAL_2 0x1C + +/* SMI indirection registers for multichip addressing mode */ +#define SMI_CMD_REG 0x00 +#define SMI_DATA_REG 0x01 + +/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CTRL 0x04 +#define GLOBAL1_MON_CTRL 0x1A + +/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD 0x18 +#define GLOBAL2_REG_PHY_DATA 0x19 + +/* Port registers */ +#define PORT_REG_STATUS 0x00 +#define PORT_REG_PHYS_CTRL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CTRL 0x04 +#define PORT_REG_VLAN_MAP 0x06 +#define PORT_REG_VLAN_ID 0x07 + +/* Phy registers */ +#define PHY_REG_CTRL1 0x10 +#define PHY_REG_STATUS1 0x11 +#define PHY_REG_PAGE 0x16 + +/* Serdes registers */ +#define SERDES_REG_CTRL_1 0x10 + +/* Phy page numbers */ +#define PHY_PAGE_COPPER 0 +#define PHY_PAGE_SERDES 1 + +/* Register fields */ +#define GLOBAL1_CTRL_SWRESET BIT(15) + +#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4 +#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4 + +#define PORT_REG_STATUS_LINK BIT(11) +#define PORT_REG_STATUS_DUPLEX BIT(10) + +#define PORT_REG_STATUS_SPEED_SHIFT 8 +#define PORT_REG_STATUS_SPEED_WIDTH 2 +#define PORT_REG_STATUS_SPEED_10 0 +#define PORT_REG_STATUS_SPEED_100 1 +#define PORT_REG_STATUS_SPEED_1000 2 + +#define PORT_REG_STATUS_CMODE_MASK 0xF +#define PORT_REG_STATUS_CMODE_100BASE_X 0x8 +#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 +#define PORT_REG_STATUS_CMODE_SGMII 0xa + +#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) +#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) + +#define PORT_REG_CTRL_PSTATE_SHIFT 0 +#define PORT_REG_CTRL_PSTATE_WIDTH 2 + +#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0 +#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12 + +#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 +#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11 + +#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10) + +#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 +#define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2 + +/* Field values */ +#define PORT_REG_CTRL_PSTATE_DISABLED 0 +#define PORT_REG_CTRL_PSTATE_FORWARD 3 + +#define PHY_REG_CTRL1_ENERGY_DET_OFF 0 +#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2 +#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3 + +/* PHY Status Register */ +#define PHY_REG_STATUS1_SPEED 0xc000 +#define PHY_REG_STATUS1_GBIT 0x8000 +#define PHY_REG_STATUS1_100 0x4000 +#define PHY_REG_STATUS1_DUPLEX 0x2000 +#define PHY_REG_STATUS1_SPDDONE 0x0800 +#define PHY_REG_STATUS1_LINK 0x0400 +#define PHY_REG_STATUS1_ENERGY 0x0010 + +/* + * Macros for building commands for indirect addressing modes. These are valid + * for both the indirect multichip addressing mode and the PHY indirection + * required for the writes to any PHY register. + */ +#define SMI_BUSY BIT(15) +#define SMI_CMD_CLAUSE_22 BIT(12) +#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) +#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) + +#define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \ + SMI_CMD_CLAUSE_22_OP_READ) +#define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \ + SMI_CMD_CLAUSE_22_OP_WRITE) + +#define SMI_CMD_ADDR_SHIFT 5 +#define SMI_CMD_ADDR_WIDTH 5 +#define SMI_CMD_REG_SHIFT 0 +#define SMI_CMD_REG_WIDTH 5 + +/* Check for required macros */ +#ifndef CONFIG_MV88E61XX_PHY_PORTS +#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \ + to activate +#endif +#ifndef CONFIG_MV88E61XX_CPU_PORT +#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to +#endif + +/* ID register values for different switch models */ +#define PORT_SWITCH_ID_6172 0x1720 +#define PORT_SWITCH_ID_6176 0x1760 +#define PORT_SWITCH_ID_6240 0x2400 +#define PORT_SWITCH_ID_6352 0x3520 + +struct mv88e61xx_phy_priv { + struct mii_dev *mdio_bus; + int smi_addr; + int id; +}; + +static inline int smi_cmd(int cmd, int addr, int reg) +{ + cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH, + addr); + cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg); + return cmd; +} + +static inline int smi_cmd_read(int addr, int reg) +{ + return smi_cmd(SMI_CMD_READ, addr, reg); +} + +static inline int smi_cmd_write(int addr, int reg) +{ + return smi_cmd(SMI_CMD_WRITE, addr, reg); +} + +__weak int mv88e61xx_hw_reset(struct phy_device *phydev) +{ + return 0; +} + +/* Wait for the current SMI indirect command to complete */ +static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr) +{ + int val; + u32 timeout = 100; + + do { + val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); + if (val >= 0 && (val & SMI_BUSY) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + puts("SMI busy timeout\n"); + return -ETIMEDOUT; +} + +/* + * The mv88e61xx has three types of addresses: the smi bus address, the device + * address, and the register address. The smi bus address distinguishes it on + * the smi bus from other PHYs or switches. The device address determines + * which on-chip register set you are reading/writing (the various PHYs, their + * associated ports, or global configuration registers). The register address + * is the offset of the register you are reading/writing. + * + * When the mv88e61xx is hardware configured to have address zero, it behaves in + * single-chip addressing mode, where it responds to all SMI addresses, using + * the smi address as its device address. This obviously only works when this + * is the only chip on the SMI bus. This allows the driver to access device + * registers without using indirection. When the chip is configured to a + * non-zero address, it only responds to that SMI address and requires indirect + * writes to access the different device addresses. + */ +static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + struct mii_dev *mdio_bus = priv->mdio_bus; + int smi_addr = priv->smi_addr; + int res; + + /* In single-chip mode, the device can be addressed directly */ + if (smi_addr == 0) + return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg); + + /* Wait for the bus to become free */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + /* Issue the read command */ + res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, + smi_cmd_read(dev, reg)); + if (res < 0) + return res; + + /* Wait for the read command to complete */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + /* Read the data */ + res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG); + if (res < 0) + return res; + + return bitfield_extract(res, 0, 16); +} + +/* See the comment above mv88e61xx_reg_read */ +static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, + u16 val) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + struct mii_dev *mdio_bus = priv->mdio_bus; + int smi_addr = priv->smi_addr; + int res; + + /* In single-chip mode, the device can be addressed directly */ + if (smi_addr == 0) { + return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg, + val); + } + + /* Wait for the bus to become free */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + /* Set the data to write */ + res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, + SMI_DATA_REG, val); + if (res < 0) + return res; + + /* Issue the write command */ + res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, + smi_cmd_write(dev, reg)); + if (res < 0) + return res; + + /* Wait for the write command to complete */ + res = mv88e61xx_smi_wait(mdio_bus, smi_addr); + if (res < 0) + return res; + + return 0; +} + +static int mv88e61xx_phy_wait(struct phy_device *phydev) +{ + int val; + u32 timeout = 100; + + do { + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_CMD); + if (val >= 0 && (val & SMI_BUSY) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + +static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev, + int devad, int reg) +{ + struct phy_device *phydev; + int res; + + phydev = (struct phy_device *)smi_wrapper->priv; + + /* Issue command to read */ + res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_CMD, + smi_cmd_read(dev, reg)); + + /* Wait for data to be read */ + res = mv88e61xx_phy_wait(phydev); + if (res < 0) + return res; + + /* Read retrieved data */ + return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_DATA); +} + +static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev, + int devad, int reg, u16 data) +{ + struct phy_device *phydev; + int res; + + phydev = (struct phy_device *)smi_wrapper->priv; + + /* Set the data to write */ + res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_DATA, data); + if (res < 0) + return res; + /* Issue the write command */ + res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, + GLOBAL2_REG_PHY_CMD, + smi_cmd_write(dev, reg)); + if (res < 0) + return res; + + /* Wait for command to complete */ + return mv88e61xx_phy_wait(phydev); +} + +/* Wrapper function to make calls to phy_read_indirect simpler */ +static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) +{ + return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg); +} + +/* Wrapper function to make calls to phy_read_indirect simpler */ +static int mv88e61xx_phy_write(struct phy_device *phydev, int phy, + int reg, u16 val) +{ + return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg, val); +} + +static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg) +{ + return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg); +} + +static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg, + u16 val) +{ + return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val); +} + +static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page) +{ + return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page); +} + +static int mv88e61xx_get_switch_id(struct phy_device *phydev) +{ + int res; + + res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID); + if (res < 0) + return res; + return res & 0xfff0; +} + +static bool mv88e61xx_6352_family(struct phy_device *phydev) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + + switch (priv->id) { + case PORT_SWITCH_ID_6172: + case PORT_SWITCH_ID_6176: + case PORT_SWITCH_ID_6240: + case PORT_SWITCH_ID_6352: + return true; + } + return false; +} + +static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port) +{ + int res; + + res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS); + if (res < 0) + return res; + return res & PORT_REG_STATUS_CMODE_MASK; +} + +static int mv88e61xx_parse_status(struct phy_device *phydev) +{ + unsigned int speed; + unsigned int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1); + + if ((mii_reg & PHY_REG_STATUS1_LINK) && + !(mii_reg & PHY_REG_STATUS1_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + phydev->link = 0; + break; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, + PHY_REG_STATUS1); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & PHY_REG_STATUS1_LINK) + phydev->link = 1; + else + phydev->link = 0; + } + + if (mii_reg & PHY_REG_STATUS1_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & PHY_REG_STATUS1_SPEED; + + switch (speed) { + case PHY_REG_STATUS1_GBIT: + phydev->speed = SPEED_1000; + break; + case PHY_REG_STATUS1_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int mv88e61xx_switch_reset(struct phy_device *phydev) +{ + int time; + int val; + u8 port; + + /* Disable all ports */ + for (port = 0; port < PORT_COUNT; port++) { + val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT, + PORT_REG_CTRL_PSTATE_WIDTH, + PORT_REG_CTRL_PSTATE_DISABLED); + val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val); + if (val < 0) + return val; + } + + /* Wait 2 ms for queues to drain */ + udelay(2000); + + /* Reset switch */ + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL); + if (val < 0) + return val; + val |= GLOBAL1_CTRL_SWRESET; + val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CTRL, val); + if (val < 0) + return val; + + /* Wait up to 1 second for switch reset complete */ + for (time = 1000; time; time--) { + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_CTRL); + if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0)) + break; + udelay(1000); + } + if (!time) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e61xx_serdes_init(struct phy_device *phydev) +{ + int val; + + val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES); + if (val < 0) + return val; + + /* Power up serdes module */ + val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR); + if (val < 0) + return val; + val &= ~(BMCR_PDOWN); + val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT, + PORT_REG_CTRL_PSTATE_WIDTH, + PORT_REG_CTRL_PSTATE_FORWARD); + val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, + u8 mask) +{ + int val; + + /* Set VID to port number plus one */ + val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT, + PORT_REG_VLAN_ID_DEF_VID_WIDTH, + port + 1); + val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val); + if (val < 0) + return val; + + /* Set VID mask */ + val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP); + if (val < 0) + return val; + val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT, + PORT_REG_VLAN_MAP_TABLE_WIDTH, + mask); + val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port) +{ + int res; + int val; + bool forced = false; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS); + if (val < 0) + return val; + if (!(val & PORT_REG_STATUS_LINK)) { + /* Temporarily force link to read port configuration */ + u32 timeout = 100; + forced = true; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + val |= (PORT_REG_PHYS_CTRL_LINK_FORCE | + PORT_REG_PHYS_CTRL_LINK_VALUE); + val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); + if (val < 0) + return val; + + /* Wait for status register to reflect forced link */ + do { + val = mv88e61xx_port_read(phydev, port, + PORT_REG_STATUS); + if (val < 0) + goto unforce; + if (val & PORT_REG_STATUS_LINK) + break; + } while (--timeout); + + if (timeout == 0) { + res = -ETIMEDOUT; + goto unforce; + } + } + + if (val & PORT_REG_STATUS_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT, + PORT_REG_STATUS_SPEED_WIDTH); + switch (val) { + case PORT_REG_STATUS_SPEED_1000: + phydev->speed = SPEED_1000; + break; + case PORT_REG_STATUS_SPEED_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + res = 0; + +unforce: + if (forced) { + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE | + PORT_REG_PHYS_CTRL_LINK_VALUE); + val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); + if (val < 0) + return val; + } + + return res; +} + +static int mv88e61xx_set_cpu_port(struct phy_device *phydev) +{ + int val; + + /* Set CPUDest */ + val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL); + if (val < 0) + return val; + val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT, + GLOBAL1_MON_CTRL_CPUDEST_WIDTH, + CONFIG_MV88E61XX_CPU_PORT); + val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1, + GLOBAL1_MON_CTRL, val); + if (val < 0) + return val; + + /* Allow CPU to route to any port */ + val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT); + val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val); + if (val < 0) + return val; + + /* Enable CPU port */ + val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + + val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + + /* If CPU is connected to serdes, initialize serdes */ + if (mv88e61xx_6352_family(phydev)) { + val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + if (val == PORT_REG_STATUS_CMODE_100BASE_X || + val == PORT_REG_STATUS_CMODE_1000BASE_X || + val == PORT_REG_STATUS_CMODE_SGMII) { + val = mv88e61xx_serdes_init(phydev); + if (val < 0) + return val; + } + } + + return 0; +} + +static int mv88e61xx_switch_init(struct phy_device *phydev) +{ + static int init; + int res; + + if (init) + return 0; + + res = mv88e61xx_switch_reset(phydev); + if (res < 0) + return res; + + res = mv88e61xx_set_cpu_port(phydev); + if (res < 0) + return res; + + init = 1; + + return 0; +} + +static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy) +{ + int val; + + val = mv88e61xx_phy_read(phydev, phy, MII_BMCR); + if (val < 0) + return val; + val &= ~(BMCR_PDOWN); + val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) +{ + int val; + + /* + * Enable energy-detect sensing on PHY, used to determine when a PHY + * port is physically connected + */ + val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1); + if (val < 0) + return val; + val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT, + PHY_REG_CTRL1_ENERGY_DET_WIDTH, + PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT); + val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) +{ + int val; + + val = mv88e61xx_port_enable(phydev, phy); + if (val < 0) + return val; + + val = mv88e61xx_port_set_vlan(phydev, phy, + 1 << CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; + + return 0; +} + +static int mv88e61xx_probe(struct phy_device *phydev) +{ + struct mii_dev *smi_wrapper; + struct mv88e61xx_phy_priv *priv; + int res; + + res = mv88e61xx_hw_reset(phydev); + if (res < 0) + return res; + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + memset(priv, 0, sizeof(*priv)); + + /* + * This device requires indirect reads/writes to the PHY registers + * which the generic PHY code can't handle. Make a wrapper MII device + * to handle reads/writes + */ + smi_wrapper = mdio_alloc(); + if (!smi_wrapper) { + free(priv); + return -ENOMEM; + } + + /* + * Store the mdio bus in the private data, as we are going to replace + * the bus with the wrapper bus + */ + priv->mdio_bus = phydev->bus; + + /* + * Store the smi bus address in private data. This lets us use the + * phydev addr field for device address instead, as the genphy code + * expects. + */ + priv->smi_addr = phydev->addr; + + /* + * Store the phy_device in the wrapper mii device. This lets us get it + * back when genphy functions call phy_read/phy_write. + */ + smi_wrapper->priv = phydev; + strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name)); + smi_wrapper->read = mv88e61xx_phy_read_indirect; + smi_wrapper->write = mv88e61xx_phy_write_indirect; + + /* Replace the bus with the wrapper device */ + phydev->bus = smi_wrapper; + + phydev->priv = priv; + + priv->id = mv88e61xx_get_switch_id(phydev); + + return 0; +} + +static int mv88e61xx_phy_config(struct phy_device *phydev) +{ + int res; + int i; + int ret = -1; + + res = mv88e61xx_switch_init(phydev); + if (res < 0) + return res; + + for (i = 0; i < PORT_COUNT; i++) { + if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { + phydev->addr = i; + + res = mv88e61xx_phy_enable(phydev, i); + if (res < 0) { + printf("Error enabling PHY %i\n", i); + continue; + } + res = mv88e61xx_phy_setup(phydev, i); + if (res < 0) { + printf("Error setting up PHY %i\n", i); + continue; + } + res = mv88e61xx_phy_config_port(phydev, i); + if (res < 0) { + printf("Error configuring PHY %i\n", i); + continue; + } + + res = genphy_config_aneg(phydev); + if (res < 0) { + printf("Error setting PHY %i autoneg\n", i); + continue; + } + res = phy_reset(phydev); + if (res < 0) { + printf("Error resetting PHY %i\n", i); + continue; + } + + /* Return success if any PHY succeeds */ + ret = 0; + } + } + + return ret; +} + +static int mv88e61xx_phy_is_connected(struct phy_device *phydev) +{ + int val; + + val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1); + if (val < 0) + return 0; + + /* + * After reset, the energy detect signal remains high for a few seconds + * regardless of whether a cable is connected. This function will + * return false positives during this time. + */ + return (val & PHY_REG_STATUS1_ENERGY) == 0; +} + +static int mv88e61xx_phy_startup(struct phy_device *phydev) +{ + int i; + int link = 0; + int res; + int speed = phydev->speed; + int duplex = phydev->duplex; + + for (i = 0; i < PORT_COUNT; i++) { + if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { + phydev->addr = i; + if (!mv88e61xx_phy_is_connected(phydev)) + continue; + res = genphy_update_link(phydev); + if (res < 0) + continue; + res = mv88e61xx_parse_status(phydev); + if (res < 0) + continue; + link = (link || phydev->link); + } + } + phydev->link = link; + + /* Restore CPU interface speed and duplex after it was changed for + * other ports */ + phydev->speed = speed; + phydev->duplex = duplex; + + return 0; +} + +static struct phy_driver mv88e61xx_driver = { + .name = "Marvell MV88E61xx", + .uid = 0x01410eb1, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_mv88e61xx_init(void) +{ + phy_register(&mv88e61xx_driver); + + return 0; +} + +/* + * Overload weak get_phy_id definition since we need non-standard functions + * to read PHY registers + */ +int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) +{ + struct phy_device temp_phy; + struct mv88e61xx_phy_priv temp_priv; + struct mii_dev temp_mii; + int val; + + /* + * Buid temporary data structures that the chip reading code needs to + * read the ID + */ + temp_priv.mdio_bus = bus; + temp_priv.smi_addr = smi_addr; + temp_phy.priv = &temp_priv; + temp_mii.priv = &temp_phy; + + val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1); + if (val < 0) + return -EIO; + + *phy_id = val << 16; + + val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2); + if (val < 0) + return -EIO; + + *phy_id |= (val & 0xffff); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 17866a2..32c7e20 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -458,6 +458,9 @@ static LIST_HEAD(phy_drivers);
int phy_init(void) { +#ifdef CONFIG_MV88E61XX_SWITCH + phy_mv88e61xx_init(); +#endif #ifdef CONFIG_PHY_AQUANTIA phy_aquantia_init(); #endif diff --git a/include/phy.h b/include/phy.h index 09bbe48..42a0f8c 100644 --- a/include/phy.h +++ b/include/phy.h @@ -249,6 +249,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_mv88e61xx_init(void); int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void);
On Thu, Mar 31, 2016 at 2:33 PM, Kevin Smith kevin.smith@elecsyscorp.com wrote:
The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY.
Signed-off-by: Kevin Smith kevin.smith@elecsyscorp.com Acked-by: Prafulla Wadaskar prafulla@marvell.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Joe Hershberger joe.hershberger@ni.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de
Acked-by: Joe Hershberger joe.hershberger@ni.com
participants (4)
-
Albert ARIBAUD -
Joe Hershberger -
Joe Hershberger -
Kevin Smith