[U-Boot] [PATCH 0/2] Fix memory instability on ROCK64
These two patches fix small issues with the Rockchip RK3328 SDRAM driver that prevented my PINE64 ROCK64 from booting and running normally using U-Boot's TPL [1].
The first patch updates the phy_dll_bypass_set() function to use the correct units for its DDR-frequency parameter, which is already specified in MHz and does not need converting. This issue caused the DRAM controller to be misconfigured for all but the lowest memory speeds.
The second patch fixes an apparent typo in phy_cfg() that caused the DRAM controller's deskew registers to be loaded with incorrect values: Instead of copying from the second 44-element portion of the skew-value array the driver instead re-used a portion of the first. This also produced instability.
With both these patches applied my ROCK64 boots and runs normally using the U-Boot TPL and a memory frequency of either 800 or 933 MHz: In both cases the "mtest" memory-test command runs indefinitely without error, and I can boot into NetBSD successfully without the kernel hanging or panicking.
[1] https://lists.denx.de/pipermail/u-boot/2019-September/384076.html
Simon South (2): ram: rk3328: Use correct frequency units in function ram: rk3328: Fix loading of skew values
drivers/ram/rockchip/sdram_rk3328.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases.
Signed-off-by: Simon South simon@simonsouth.net --- drivers/ram/rockchip/sdram_rk3328.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 656696ac3c..0541bbadf0 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -311,12 +311,12 @@ static void phy_dll_bypass_set(struct dram_info *dram, u32 freq) setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
- if (freq <= (400 * MHz)) + if (freq <= 400) /* DLL bypass */ setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); else clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); - if (freq <= (680 * MHz)) + if (freq <= 680) tmp = 2; else tmp = 1;
On 2019/10/7 上午12:28, Simon South wrote:
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases.
Signed-off-by: Simon South simon@simonsouth.net
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Thanks, - Kever
drivers/ram/rockchip/sdram_rk3328.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 656696ac3c..0541bbadf0 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -311,12 +311,12 @@ static void phy_dll_bypass_set(struct dram_info *dram, u32 freq) setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
- if (freq <= (400 * MHz))
- if (freq <= 400) /* DLL bypass */ setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); else clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
- if (freq <= (680 * MHz))
- if (freq <= 680) tmp = 2; else tmp = 1;
On 2019/10/8 上午10:55, Kever Yang wrote:
On 2019/10/7 上午12:28, Simon South wrote:
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases.
Signed-off-by: Simon South simon@simonsouth.net
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Applied to u-boot-rockchip master.
Thanks,
- Kever
drivers/ram/rockchip/sdram_rk3328.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 656696ac3c..0541bbadf0 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -311,12 +311,12 @@ static void phy_dll_bypass_set(struct dram_info *dram, u32 freq) setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3); - if (freq <= (400 * MHz)) + if (freq <= 400) /* DLL bypass */ setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); else clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); - if (freq <= (680 * MHz)) + if (freq <= 680) tmp = 2; else tmp = 1;
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers.
Signed-off-by: Simon South simon@simonsouth.net --- drivers/ram/rockchip/sdram_rk3328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 0541bbadf0..e84c9be6a2 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -394,7 +394,7 @@ static void phy_cfg(struct dram_info *dram, copy_to_reg(PHY_REG(phy_base, 0x70), &sdram_params->skew.cs0_dm0_skew[0], 44 * 4); copy_to_reg(PHY_REG(phy_base, 0xc0), - &sdram_params->skew.cs0_dm1_skew[0], 44 * 4); + &sdram_params->skew.cs1_dm0_skew[0], 44 * 4); }
static int update_refresh_reg(struct dram_info *dram)
On 2019/10/7 上午12:28, Simon South wrote:
Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers.
Signed-off-by: Simon South simon@simonsouth.net
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Thanks, - Kever
drivers/ram/rockchip/sdram_rk3328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 0541bbadf0..e84c9be6a2 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -394,7 +394,7 @@ static void phy_cfg(struct dram_info *dram, copy_to_reg(PHY_REG(phy_base, 0x70), &sdram_params->skew.cs0_dm0_skew[0], 44 * 4); copy_to_reg(PHY_REG(phy_base, 0xc0),
&sdram_params->skew.cs0_dm1_skew[0], 44 * 4);
&sdram_params->skew.cs1_dm0_skew[0], 44 * 4);}
static int update_refresh_reg(struct dram_info *dram)
On 2019/10/8 上午10:55, Kever Yang wrote:
On 2019/10/7 上午12:28, Simon South wrote:
Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers.
Signed-off-by: Simon South simon@simonsouth.net
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Applied to u-boot-rockchip master.
Thanks,
- Kever
drivers/ram/rockchip/sdram_rk3328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 0541bbadf0..e84c9be6a2 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -394,7 +394,7 @@ static void phy_cfg(struct dram_info *dram, copy_to_reg(PHY_REG(phy_base, 0x70), &sdram_params->skew.cs0_dm0_skew[0], 44 * 4); copy_to_reg(PHY_REG(phy_base, 0xc0), - &sdram_params->skew.cs0_dm1_skew[0], 44 * 4); + &sdram_params->skew.cs1_dm0_skew[0], 44 * 4); } static int update_refresh_reg(struct dram_info *dram)
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On Sun, 2019-10-06 at 12:28 -0400, Simon South wrote:
These two patches fix small issues with the Rockchip RK3328 SDRAM driver that prevented my PINE64 ROCK64 from booting and running normally using U-Boot's TPL [1].
The first patch updates the phy_dll_bypass_set() function to use the correct units for its DDR-frequency parameter, which is already specified in MHz and does not need converting. This issue caused the DRAM controller to be misconfigured for all but the lowest memory speeds.
The second patch fixes an apparent typo in phy_cfg() that caused the DRAM controller's deskew registers to be loaded with incorrect values: Instead of copying from the second 44-element portion of the skew-value array the driver instead re-used a portion of the first. This also produced instability.
With both these patches applied my ROCK64 boots and runs normally using the U-Boot TPL and a memory frequency of either 800 or 933 MHz: In both cases the "mtest" memory-test command runs indefinitely without error, and I can boot into NetBSD successfully without the kernel hanging or panicking.
[1] https://lists.denx.de/pipermail/u-boot/2019-September/384076.html
Simon South (2): ram: rk3328: Use correct frequency units in function ram: rk3328: Fix loading of skew values
drivers/ram/rockchip/sdram_rk3328.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Your corrections also have helped OpenBSD/arm64 boot using u-boot TPL on Rock64. Here is one test report result:
https://marc.info/?l=openbsd-arm&m=157041723301520&w=2
Thank you for tracking down the problems.
-Kurt
participants (3)
-
Kever Yang -
Kurt Miller -
Simon South