[v2 00/22] Add Intel Diamond Mesa SoC support
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Diamond Mesa are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex.
Patch status: Have changes: Patch 20, 22 Other patches unchanged.
Detail changelog can find in commit message.
v1->v2: -------- Patch 20: - Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in socfpga_dm-u-boot.dtsi
Patch 22: - Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to socfpga_dm_atf_defconfig. Use binman to generate FIT image instead of local script.
History: -------- [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200922094930.100855-1-ell...
These patchsets have dependency on:
Enable ARM Trusted Firmware for U-Boot https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly...
[1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-dev...
Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
Pali Rohár (1): Makefile: Fix calling make with V=1
Siew Chin Lim (2): arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman
Simon Glass (5): odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings x86: Provide default SMBIOS manufacturer/product smbios: Drop the unused Kconfig options
From: Simon Glass sjg@chromium.org
Add settings and enable the default sysinfo driver so that these can come from the device tree.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com --- arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 +++++++++++++++++++++++ configs/odroid-c2_defconfig | 4 ++-- 2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi index 484b40504d..90087b00db 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi +++ b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi @@ -6,6 +6,29 @@
#include "meson-gx-u-boot.dtsi"
+/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + + smbios { + system { + manufacturer = "Hardkernel Co., Ltd."; + product = "ODROID-C2"; + }; + + baseboard { + manufacturer = "Hardkernel Co., Ltd."; + product = "ODROID-C2"; + }; + + chassis { + manufacturer = "Hardkernel Co., Ltd."; + product = "ODROID-C2"; + }; + }; + }; +}; + &usb0 { status = "disabled"; }; diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 5fdce3b463..f2c9fa7277 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" -CONFIG_SMBIOS_PRODUCT_NAME="ODROID-C2" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -64,4 +63,5 @@ CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="Hardkernel Co., Ltd." +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y
From: Simon Glass sjg@chromium.org
Add settings and enable the default sysinfo driver so that these can come from the device tree.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com --- arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20 ++++++++++++++++++++ configs/uDPU_defconfig | 3 ++- 2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi index ef178bdc86..fdad90ad12 100644 --- a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi +++ b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi @@ -1,5 +1,25 @@ // SPDX-License-Identifier: GPL-2.0+
+/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + + smbios { + system { + product = "uDPU"; + }; + + baseboard { + product = "uDPU"; + }; + + chassis { + product = "uDPU"; + }; + }; + }; +}; + &spi0 { u-boot,dm-pre-reloc;
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index dfab2b306b..ec97489523 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -11,7 +11,6 @@ CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU" -CONFIG_SMBIOS_PRODUCT_NAME="uDPU" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -97,3 +96,5 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_LZO=y CONFIG_SPL_LZO=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y
From: Simon Glass sjg@chromium.org
Add settings and enable the default sysinfo driver so that these can come from the device tree.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com --- arch/x86/dts/galileo.dts | 28 ++++++++++++++++++++++++++++ board/intel/galileo/Kconfig | 11 ----------- 2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 5de4568679..501047124e 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -164,4 +164,32 @@ }; };
+ smbios { + compatible = "u-boot,sysinfo-smbios"; + + /* + * Override the default product name U-Boot reports in the + * SMBIOS table, to be compatible with the Intel provided UEFI + * BIOS, as Linux kernel drivers + * (drivers/mfd/intel_quark_i2c_gpio.c and + * drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of + * it to do different board level configuration. + * + * This can be "Galileo" for GEN1 Galileo board. + */ + smbios { + system { + product = "GalileoGen2"; + }; + + baseboard { + product = "GalileoGen2"; + }; + + chassis { + product = "GalileoGen2"; + }; + }; + }; + }; diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 1416c891e8..fb8d94fb5b 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -22,15 +22,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select SPI_FLASH_WINBOND
-config SMBIOS_PRODUCT_NAME - default "GalileoGen2" - help - Override the default product name U-Boot reports in the SMBIOS - table, to be compatible with the Intel provided UEFI BIOS, as - Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and - drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of - it to do different board level configuration. - - This can be "Galileo" for GEN1 Galileo board. - endif
From: Simon Glass sjg@chromium.org
Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor.
Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng bmeng.cn@gmail.com --- arch/Kconfig | 2 ++ arch/x86/dts/bayleybay.dts | 2 ++ arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 ++ arch/x86/dts/cherryhill.dts | 2 ++ arch/x86/dts/chromebook_link.dts | 2 ++ arch/x86/dts/chromebook_samus.dts | 2 ++ arch/x86/dts/chromebox_panther.dts | 2 ++ arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 ++ arch/x86/dts/cougarcanyon2.dts | 2 ++ arch/x86/dts/crownbay.dts | 2 ++ arch/x86/dts/dfi-bt700.dtsi | 2 ++ arch/x86/dts/edison.dts | 2 ++ arch/x86/dts/minnowmax.dts | 2 ++ arch/x86/dts/qemu-x86_i440fx.dts | 2 ++ arch/x86/dts/qemu-x86_q35.dts | 2 ++ arch/x86/dts/smbios.dtsi | 32 +++++++++++++++++++++++++++ configs/chromebook_coral_defconfig | 2 +- 17 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/smbios.dtsi
diff --git a/arch/Kconfig b/arch/Kconfig index 3b9fcce980..041e179256 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -198,6 +198,8 @@ config X86 imply RTC_MC146818 imply IRQ imply ACPIGEN if !QEMU + imply SYSINFO if GENERATE_SMBIOS_TABLE + imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
# Thing to enable for when SPL/TPL are enabled: SPL imply SPL_DM diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index d0168e88db..70e5798403 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -16,6 +16,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Intel Bayley Bay"; compatible = "intel,bayleybay", "intel,baytrail"; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 5abbc66ce9..a7dc03b645 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -16,6 +16,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Advantech SOM-DB5800-SOM-6867"; compatible = "advantech,som-db5800-som-6867", "intel,baytrail"; diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 37146fde2b..2ce7f1aa91 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -14,6 +14,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Intel Cherry Hill"; compatible = "intel,cherryhill", "intel,braswell"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 09488f13b5..e529c4b63e 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -11,6 +11,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Google Link"; compatible = "google,link", "intel,celeron-ivybridge"; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index d8e04a6698..adaeb1ea35 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -9,6 +9,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + #ifdef CONFIG_CHROMEOS_VBOOT #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index bcd4c4d9c1..77b6ac9ab9 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -6,6 +6,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Google Panther"; compatible = "google,panther", "intel,haswell"; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 70b8c04519..bbea99da2c 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -16,6 +16,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "congatec-QEVAL20-QA3-E3845"; compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index c6ba811e05..602523333e 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -14,6 +14,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Intel Cougar Canyon 2"; compatible = "intel,cougarcanyon2", "intel,chiefriver"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index f492c35875..a7166a9749 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -15,6 +15,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Intel Crown Bay"; compatible = "intel,crownbay", "intel,queensbay"; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index e9930cb043..7d7b8357d9 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -13,6 +13,8 @@ #include "rtc.dtsi" #include "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { config { silent_console = <0>; diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index e2f9469de3..bc84bc892e 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -12,6 +12,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Intel Edison"; compatible = "intel,edison"; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index f4cdb2c3cd..133d55bc20 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -15,6 +15,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "Intel Minnowboard Max"; compatible = "intel,minnowmax", "intel,baytrail"; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 2e5210d4ee..c33a11d593 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -14,6 +14,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "QEMU x86 (I440FX)"; compatible = "qemu,x86"; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index e8f55b19a2..9faae7fb56 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -24,6 +24,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi" + / { model = "QEMU x86 (Q35)"; compatible = "qemu,x86"; diff --git a/arch/x86/dts/smbios.dtsi b/arch/x86/dts/smbios.dtsi new file mode 100644 index 0000000000..9fa8c638a5 --- /dev/null +++ b/arch/x86/dts/smbios.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Default SMBIOS information. Include this in your board .dts file if you want + * these defaults. + * + * Copyright 2020 Google LLC + */ + +#include <config.h> + +/ { + smbios: smbios { + compatible = "u-boot,sysinfo-smbios"; + + smbios { + system { + manufacturer = CONFIG_SYS_VENDOR; + product = CONFIG_SYS_BOARD; + }; + + baseboard { + manufacturer = CONFIG_SYS_VENDOR; + product = CONFIG_SYS_BOARD; + }; + + chassis { + manufacturer = CONFIG_SYS_VENDOR; + /* chassis product is not set by default */ + }; + }; + }; +}; diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index d960793d9a..51f892fb13 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -99,7 +99,7 @@ CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_RT5677=y CONFIG_SPI=y CONFIG_ICH_SPI=y -CONFIG_SYSINFO=y +# CONFIG_SYSINFO_SMBIOS is not set CONFIG_TPL_SYSRESET=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_CR50_I2C=y
From: Simon Glass sjg@chromium.org
Now that we can use devicetree to specify this information, drop the old CONFIG options.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com --- configs/clearfog_gt_8k_defconfig | 2 -- configs/mt7622_rfb_defconfig | 1 - configs/mvebu_db_armada8k_defconfig | 2 -- configs/r8a774a1_beacon_defconfig | 2 -- configs/r8a77970_eagle_defconfig | 2 -- configs/r8a77980_condor_defconfig | 2 -- configs/r8a77990_ebisu_defconfig | 2 -- configs/r8a77995_draak_defconfig | 2 -- configs/rcar3_salvator-x_defconfig | 2 -- configs/rcar3_ulcb_defconfig | 2 -- lib/Kconfig | 16 ------------- lib/smbios.c | 46 +++++++++++-------------------------- 12 files changed, 13 insertions(+), 68 deletions(-)
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 552df3a8b8..9bb1f212a7 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -12,7 +12,6 @@ CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -78,4 +77,3 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index a6089d6cf6..ccf926e104 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x41e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" CONFIG_LOGLEVEL=7 diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index a88d5cc98b..5d8a1b655c 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -72,4 +71,3 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig index 5d564d82c2..2f45edd92e 100644 --- a/configs/r8a774a1_beacon_defconfig +++ b/configs/r8a774a1_beacon_defconfig @@ -8,7 +8,6 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_BEACON_RZG2M=y # CONFIG_SPL is not set CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -64,4 +63,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index a777484235..9dbe0e1d5b 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_EAGLE=y CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -74,4 +73,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 4e457234ed..dbe2912779 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_CONDOR=y CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -75,4 +74,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 4667284bb3..cb75b5c3a6 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_EBISU=y CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -84,4 +83,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 5cc0f608da..46a7314fa9 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_DRAAK=y CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -85,4 +84,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 5f2f366554..ff6e0e945e 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -89,4 +88,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index 03865dfc34..df202a7598 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -87,4 +86,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/lib/Kconfig b/lib/Kconfig index fdc35a9232..7673d2e4e0 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -661,22 +661,6 @@ config GENERATE_SMBIOS_TABLE See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in the devicetree.
-config SMBIOS_MANUFACTURER - string "SMBIOS Manufacturer" - depends on GENERATE_SMBIOS_TABLE - default SYS_VENDOR - help - The board manufacturer to store in SMBIOS structures. - Change this to override the default one (CONFIG_SYS_VENDOR). - -config SMBIOS_PRODUCT_NAME - string "SMBIOS Product Name" - depends on GENERATE_SMBIOS_TABLE - default SYS_BOARD - help - The product name to store in SMBIOS structures. - Change this to override the default one (CONFIG_SYS_BOARD). - endmenu
config ASN1_COMPILER diff --git a/lib/smbios.c b/lib/smbios.c index a52a9d5b30..485a812c77 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -65,43 +65,28 @@ static int smbios_add_string(char *start, const char *str) }
/** - * smbios_add_prop_default() - Add a property from the device tree or default + * smbios_add_prop() - Add a property from the device tree * * @start: string area start address * @node: node containing the information to write (ofnode_null() if none) * @prop: property to write - * @def: default string if the node has no such property * @return 0 if not found, else SMBIOS string number (1 or more) */ -static int smbios_add_prop_default(char *start, ofnode node, const char *prop, - const char *def) +static int smbios_add_prop(char *start, ofnode node, const char *prop) { - const char *str = NULL;
- if (IS_ENABLED(CONFIG_OF_CONTROL)) + if (IS_ENABLED(CONFIG_OF_CONTROL)) { + const char *str; + str = ofnode_read_string(node, prop); - if (str) - return smbios_add_string(start, str); - else if (def) - return smbios_add_string(start, def); + if (str) + return smbios_add_string(start, str); + }
return 0; }
/** - * smbios_add_prop() - Add a property from the device tree - * - * @start: string area start address - * @node: node containing the information to write (ofnode_null() if none) - * @prop: property to write - * @return 0 if not found, else SMBIOS string number (1 or more) - */ -static int smbios_add_prop(char *start, ofnode node, const char *prop) -{ - return smbios_add_prop_default(start, node, prop, NULL); -} - -/** * smbios_string_table_len() - compute the string area size * * This computes the size of the string area including the string terminator. @@ -169,10 +154,8 @@ static int smbios_write_type1(ulong *current, int handle, ofnode node) t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type1)); fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); - t->manufacturer = smbios_add_prop_default(t->eos, node, "manufacturer", - CONFIG_SMBIOS_MANUFACTURER); - t->product_name = smbios_add_prop_default(t->eos, node, "product", - CONFIG_SMBIOS_PRODUCT_NAME); + t->manufacturer = smbios_add_prop(t->eos, node, "manufacturer"); + t->product_name = smbios_add_prop(t->eos, node, "product"); t->version = smbios_add_prop(t->eos, node, "version"); if (serial_str) { t->serial_number = smbios_add_string(t->eos, serial_str); @@ -198,10 +181,8 @@ static int smbios_write_type2(ulong *current, int handle, ofnode node) t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type2)); fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); - t->manufacturer = smbios_add_prop_default(t->eos, node, "manufacturer", - CONFIG_SMBIOS_MANUFACTURER); - t->product_name = smbios_add_prop_default(t->eos, node, "product", - CONFIG_SMBIOS_PRODUCT_NAME); + t->manufacturer = smbios_add_prop(t->eos, node, "manufacturer"); + t->product_name = smbios_add_prop(t->eos, node, "product"); t->asset_tag_number = smbios_add_prop(t->eos, node, "asset-tag"); t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; t->board_type = SMBIOS_BOARD_MOTHERBOARD; @@ -221,8 +202,7 @@ static int smbios_write_type3(ulong *current, int handle, ofnode node) t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type3)); fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); - t->manufacturer = smbios_add_prop_default(t->eos, node, "manufacturer", - CONFIG_SMBIOS_MANUFACTURER); + t->manufacturer = smbios_add_prop(t->eos, node, "manufacturer"); t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE;
From: Pali Rohár pali@kernel.org
Calling 'make V=1 all' on Ubuntu 18.04 with gcc version 9.2.1 and GNU Make version 4.1 fails on error:
scripts/Kbuild.include:220: *** Recursive variable 'echo-cmd' references itself (eventually). Stop.
As a workaround expand 'echo-cmd' variable via 'call' construction instead of expanding it directly.
Signed-off-by: Pali Rohár pali@kernel.org Reported-by: Patrick Delaunay patrick.delaunay@st.com Reviewed-by: Patrick Delaunay patrick.delaunay@st.com Fixes: ae897022d7bd ("Makefile: Fix u-boot-nodtb.bin target") --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile index 89c42c1024..59ba3330cd 100644 --- a/Makefile +++ b/Makefile @@ -1309,7 +1309,7 @@ init_sp_bss_offset_check: u-boot.dtb FORCE fi endif
-shell_cmd = { $(echo-cmd) $(cmd_$(1)); } +shell_cmd = { $(call echo-cmd,$(1)) $(cmd_$(1)); }
quiet_cmd_objcopy_uboot = OBJCOPY $@ cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || rm -f $@
From: Chee Hong Ang chee.hong.ang@intel.com
Add board_fit_config_name_match() for matching board name with device tree files in FIT image. This will ensure correct DTB file is loaded for different board type. Currently, we are not supporting multiple device tree files in FIT image therefore this function basically do nothing for now. Users are allowed to override this 'weak' function in their specific board implementation.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/board.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 340abf9305..7993c27646 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -13,7 +13,7 @@ #include <asm/arch/clock_manager.h> #include <asm/arch/misc.h> #include <asm/io.h> - +#include <log.h> #include <usb.h> #include <usb/dwc2_udc.h>
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void) return 1; } #endif + +#ifdef CONFIG_SPL_BUILD +__weak int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif
From: Chee Hong Ang chee.hong.ang@intel.com
Instead of loading u-boot proper image (u-boot.img), SPL now loads FIT image (u-boot.itb) which includes u-boot proper, ATF and u-boot proper's DTB.
For OS, u-boot now loads FIT images (kernel.itb) which includes Linux Image and Linux's DTB.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- include/configs/socfpga_soc64_common.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index fb5e2e8aaf..990f879b07 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -78,12 +78,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * CONFIG_BOOTARGS goes into the environment value "bootargs". * Do note the value will override also the chosen node in FDT blob. */ + +#ifdef CONFIG_FIT +#define CONFIG_BOOTFILE "kernel.itb" +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \ + "run mmcfitboot" +#else +#define CONFIG_BOOTFILE "Image" #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ "run mmcboot" +#endif
#define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "bootfile=Image\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mmcroot=/dev/mmcblk0p2\0" \ @@ -93,6 +101,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootfile};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootm ${loadaddr}\0" \ + "mmcfitload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ "linux_qspi_enable=if sf probe; then " \ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ @@ -193,6 +206,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); - CONFIG_SYS_SPL_MALLOC_SIZE)
/* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
From: Chee Hong Ang chee.hong.ang@intel.com
Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S new file mode 100644 index 0000000000..612ea8a037 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else + branch_if_slave x0, 1f +#endif + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 2f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent slaves observing incorrect + * value of spin table and jumping to wrong place. + */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* + * All slaves will enter EL2 and optionally EL1. + */ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init)
From: Chee Hong Ang chee.hong.ang@intel.com
Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX
choice
From: Chee Hong Ang chee.hong.ang@intel.com
invoke_smc() allow U-Boot proper running in non-secure mode (EL2) to invoke SMC call to ATF's PSCI runtime services such as System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD) to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++++++ arch/arm/mach-socfpga/smc_api.c | 56 ++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index c63162a5c6..0b05283a7a 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += firewall.o obj-y += spl_agilex.o endif +else +obj-$(CONFIG_SPL_ATF) += smc_api.o endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h b/arch/arm/mach-socfpga/include/mach/smc_api.h new file mode 100644 index 0000000000..bbefdd8dd9 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/smc_api.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Intel Corporation + */ + +#ifndef _SMC_API_H_ +#define _SMC_API_H_ + +int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len); +int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, + u32 *resp_buf); + +#endif /* _SMC_API_H_ */ diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c new file mode 100644 index 0000000000..085daba162 --- /dev/null +++ b/arch/arm/mach-socfpga/smc_api.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/ptrace.h> +#include <asm/system.h> +#include <linux/intel-smc.h> + +int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len) +{ + struct pt_regs regs; + + memset(®s, 0, sizeof(regs)); + regs.regs[0] = func_id; + + if (args) + memcpy(®s.regs[1], args, arg_len * sizeof(*args)); + + smc_call(®s); + + if (ret_arg) + memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg)); + + return regs.regs[0]; +} + +int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, + u32 *resp_buf) +{ + int ret; + u64 args[6]; + u64 resp[3]; + + args[0] = cmd; + args[1] = (u64)arg; + args[2] = len; + args[3] = urgent; + args[4] = (u64)resp_buf; + if (resp_buf_len) + args[5] = *resp_buf_len; + else + args[5] = 0; + + ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args), + resp, ARRAY_SIZE(resp)); + + if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) { + if (!resp[0]) + *resp_buf_len = resp[1]; + } + + return (int)resp[0]; +}
From: Chee Hong Ang chee.hong.ang@intel.com
This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- include/linux/intel-smc.h | 573 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 0000000000..cacb410691 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include <linux/arm-smccc.h> +#include <linux/bitops.h> + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of u-boot tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * values. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * SMC call completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the SMC call process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF +#define INTEL_SIP_SMC_STATUS_OK 0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR 0x5 +#define INTEL_SIP_SMC_RSU_ERROR 0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + * 0 full reconfiguration. + * 1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, otherwise zero value. + * a2: 64bit physical address of 2nd completed memory block if any completed + * block, otherwise zero value. + * a3: 64bit physical address of 3rd completed memory block if any completed + * block, otherwise zero value. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 +#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ + INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE + * + * Sync call used by service driver at EL1 to track the completed write + * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * call returns INTEL_SIP_SMC_STATUS_BUSY. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block. + * a2: 64bit physical address of 2nd completed memory block if + * any completed block, otherwise zero value. + * a3: 64bit physical address of 3rd completed memory block if + * any completed block, otherwise zero value. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 +#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ +INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE + * + * Sync call used by service driver at EL1 to inform secure world that all + * data are sent, to check whether or not the secure world had completed + * the FPGA configuration process. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 +#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM + * + * Sync call used by service driver at EL1 to query the physical address of + * memory block reserved by secure monitor software. + * + * Call register usage: + * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. + * a1: start of physical address of reserved memory block. + * a2: size of reserved memory block. + * a3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 +#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK + * + * For SMC loop-back mode only, used for internal integration, debugging + * or troubleshooting. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. + * a1-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 +#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) + +/* + * Request INTEL_SIP_SMC_REG_READ + * + * Read a protected register using SMCCC + * + * Call register usage: + * a0: INTEL_SIP_SMC_REG_READ. + * a1: register address. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. + * a1: Value in the register + * a2-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_REG_READ 7 +#define INTEL_SIP_SMC_REG_READ \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) + +/* + * Request INTEL_SIP_SMC_REG_WRITE + * + * Write a protected register using SMCCC + * + * Call register usage: + * a0: INTEL_SIP_SMC_REG_WRITE. + * a1: register address + * a2: value to program into register. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 +#define INTEL_SIP_SMC_REG_WRITE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) + +/* + * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE + * + * Update one or more bits in a protected register using a + * read-modify-write operation. + * + * Call register usage: + * a0: INTEL_SIP_SMC_REG_UPDATE. + * a1: register address + * a2: Write Mask. + * a3: Value to write. + * a4-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. + * a1-3: Not used. + */ +#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 +#define INTEL_SIP_SMC_REG_UPDATE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) + +/* +* Request INTEL_SIP_SMC_RSU_STATUS +* +* Sync call used by service driver at EL1 to query the RSU status +* +* Call register usage: +* a0 INTEL_SIP_SMC_RSU_STATUS +* a1-7 not used +* +* Return status +* a0: Current Image +* a1: Last Failing Image +* a2: Version [width 32 bit] | State [width 32 bit] +* a3: Error details [width 32 bit] | Error location [width 32 bit] +* +* Or +* +* a0: INTEL_SIP_SMC_RSU_ERROR +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 +#define INTEL_SIP_SMC_RSU_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) + +/* +* Request INTEL_SIP_SMC_RSU_UPDATE +* +* Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE +* +* Call register usage: +* a0 INTEL_SIP_SMC_RSU_UPDATE +* a1 64bit physical address of the configuration data memory in flash +* a2-7 not used +* +* Return status + * a0 INTEL_SIP_SMC_STATUS_OK +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 +#define INTEL_SIP_SMC_RSU_UPDATE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) + +/* + * Request INTEL_SIP_SMC_ECC_DBE + * + * Sync call used by service driver at EL1 alert EL3 that a Double Bit + * ECC error has occurred. + * + * Call register usage: + * a0 INTEL_SIP_SMC_ECC_DBE + * a1 SysManager Double Bit Error value + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13 +#define INTEL_SIP_SMC_ECC_DBE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE) + +/* +* Request INTEL_SIP_SMC_RSU_NOTIFY +* +* Sync call used by service driver at EL1 to report HPS software execution stage +* +* Call register usage: +* a0 INTEL_SIP_SMC_RSU_NOTIFY +* a1 32bit HPS software execution stage +* a2-7 not used +* +* Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14 +#define INTEL_SIP_SMC_RSU_NOTIFY \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY) + +/* + * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER + * + * Sync call used by service driver at EL1 to query the RSU retry counter + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR. + * a1 retry counter +*/ +#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15 +#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER) + +/* + * Request INTEL_SIP_SMC_RSU_DCMF_VERSION + * + * Sync call used by service driver at EL1 to query DCMF version + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 dcmf1 version | dcmf0 version + * a2 dcmf3 version | dcmf2 version + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16 +#define INTEL_SIP_SMC_RSU_DCMF_VERSION \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION) + +/* + * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION + * + * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION + * a1 dcmf1 version | dcmf0 version + * a2 dcmf3 version | dcmf2 version + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17 +#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION) + +/* + * Request INTEL_SIP_SMC_RSU_MAX_RETRY + * + * Sync call used by service driver at EL1 to query max_retry parameter + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_MAX_RETRY + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 max_retry + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18 +#define INTEL_SIP_SMC_RSU_MAX_RETRY \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY) + +/* + * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY + * + * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY + * a1 max retry + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19 +#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY) + +/* + * Request INTEL_SIP_SMC_RSU_DCMF_STATUS + * + * Sync call used by service driver at EL1 to query DCMF status + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS + * a1-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status + * + * Or + * + * a0 INTEL_SIP_SMC_RSU_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20 +#define INTEL_SIP_SMC_RSU_DCMF_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS) + +/* + * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS + * + * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory + * + * Call register usage: + * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS + * a1 dcmf status + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21 +#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS) + +/* + * Request INTEL_SIP_SMC_HPS_SET_BRIDGES + * + * Enable/disable the SoC FPGA bridges + * + * Call register usage: + * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES + * a1 Set bridges status: + * 0 - Disable + * 1 - Enable + * a2-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50 +#define INTEL_SIP_SMC_HPS_SET_BRIDGES \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES) + +/* + * Request INTEL_SIP_SMC_MBOX_SEND_CMD + * + * Send mailbox command to SDM + * + * Call register usage: + * a0 INTEL_SIP_SMC_MBOX_SEND_CMD + * a1 Mailbox command + * a2 64bit physical address pointer to command's arguments + * a3 Length of the argument + * a4 Urgent command: + * 0 - Disable + * 1 - Enable + * a5 64bit physical address pointer to a buffer for receiving responses + * a6 Length of the buffer + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR + * a1 Status of mailbox response + * a2 Received length in the buffer + */ +#define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60 +#define INTEL_SIP_SMC_MBOX_SEND_CMD \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) + +/* + * Request INTEL_SIP_SMC_HPS_SET_PHYINTF + * + * Select EMACx PHY interface + * + * Call register usage: + * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF + * a1 EMAC number: + * 0 - EMAC0 + * 1 - EMAC1 + * 2 - EMAC2 + * a2 Type of PHY interface: + * 0 - GMII_MII + * 1 - RGMII + * 2 - RMII + * 3 - RESET + * a3-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR + */ +#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61 +#define INTEL_SIP_SMC_HPS_SET_PHYINTF \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF) + +/* + * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK + * + * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC + * + * Call register usage: + * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK + * a1 Select which phase shift of the clock for cclk_in_drv (drvsel): + * 0 - 0 degree + * 1 - 45 degrees + * 2 - 90 degrees + * 3 - 135 degrees + * 4 - 180 degrees + * 5 - 225 degrees + * 6 - 270 degrees + * 7 - 315 degrees + * a2 Select which phase shift of the clock for cclk_in_sample (smplsel): + * (Same as above) + * a3-7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + */ +#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62 +#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK) + +#endif
From: Chee Hong Ang chee.hong.ang@intel.com
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- drivers/mmc/socfpga_dw_mmc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 0022f943bd..e5f68fa7fb 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,6 +6,7 @@ #include <common.h> #include <log.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> #include <clk.h> #include <dm.h> @@ -13,6 +14,7 @@ #include <errno.h> #include <fdtdec.h> #include <dm/device_compat.h> +#include <linux/intel-smc.h> #include <linux/libfdt.h> #include <linux/err.h> #include <malloc.h> @@ -48,6 +50,10 @@ static void socfpga_dwmci_reset(struct udevice *dev)
static void socfpga_dwmci_clksel(struct dwmci_host *host) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 args[2]; +#endif + struct dwmci_socfpga_priv_data *priv = host->priv; u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); @@ -58,10 +64,21 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + /* drvsel */ + args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7; + /* smplsel */ + args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7; + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0)) + dev_err(host->mmc->dev, "SMC call failed in %s\n", __func__); + +#else writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); +#endif
/* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
From: Chee Hong Ang chee.hong.ang@intel.com
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- drivers/net/dwmac_socfpga.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index e93561dffa..a2d09d5c4a 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -17,7 +17,9 @@ #include <dm/device_compat.h> #include <linux/err.h>
+#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <linux/intel-smc.h>
struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; @@ -64,6 +66,27 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); }
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 args[2]; + + args[0] = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() - + SYSMGR_SOC64_EMAC0) >> 2; + args[1] = modereg; + + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0)) + return -EIO; +#else + clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << + pdata->reg_shift, modereg << pdata->reg_shift); +#endif + + return 0; +} + static int dwmac_socfpga_probe(struct udevice *dev) { struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); @@ -71,7 +94,6 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct reset_ctl_bulk reset_bulk; int ret; u32 modereg; - u32 modemask;
switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: @@ -97,9 +119,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; - clrsetbits_le32(pdata->phy_intf, modemask, - modereg << pdata->reg_shift); + ret = dwmac_socfpga_do_setphy(dev, modereg); + if (ret) + return ret;
reset_release_bulk(&reset_bulk);
From: Chee Hong Ang chee.hong.ang@intel.com
In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service provided by ATF to enable/disable the SOCFPGA bridges.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- arch/arm/mach-socfpga/reset_manager_s10.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 3746e6a60c..af8f2c0873 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -5,11 +5,14 @@ */
#include <common.h> +#include <hang.h> #include <asm/io.h> #include <asm/arch/reset_manager.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> #include <linux/iopoll.h> +#include <linux/intel-smc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 arg = enable; + + int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); + if (ret) { + printf("SMC call failed with error %d in %s.\n", ret, __func__); + return; + } +#else u32 reg;
if (enable) { @@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable) /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } +#endif }
/*
From: Chee Hong Ang chee.hong.ang@intel.com
In non-secure mode (EL2), FPGA reconfiguration driver calls the SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- drivers/fpga/intel_sdm_mb.c | 139 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 9a1dc2c0c8..f5fd9a14c2 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -8,11 +8,149 @@ #include <log.h> #include <watchdog.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <linux/delay.h> +#include <linux/intel-smc.h>
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + +#define BITSTREAM_CHUNK_SIZE 0xFFFF0 +#define RECONFIG_STATUS_POLL_RETRY_MAX 100 + +/* + * Polling the FPGA configuration status. + * Return 0 for success, non-zero for error. + */ +static int reconfig_status_polling_resp(void) +{ + int ret; + unsigned long start = get_timer(0); + + while (1) { + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0, + NULL, 0); + + if (!ret) + return 0; /* configuration success */ + + if (ret != INTEL_SIP_SMC_STATUS_BUSY) + return ret; + + if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS) + return -ETIMEDOUT; /* time out */ + + puts("."); + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + WATCHDOG_RESET(); + } + + return -ETIMEDOUT; +} + +static int send_bitstream(const void *rbf_data, size_t rbf_size) +{ + int i; + u64 res_buf[3]; + u64 args[2]; + u32 xfer_count = 0; + int ret, wr_ret = 0, retry = 0; + size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ? + BITSTREAM_CHUNK_SIZE : rbf_size; + + while (rbf_size || xfer_count) { + if (!wr_ret && rbf_size) { + args[0] = (u64)rbf_data; + args[1] = buf_size; + wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE, + args, 2, NULL, 0); + + debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n", + wr_ret, rbf_data, buf_size); + + if (wr_ret) + continue; + + rbf_size -= buf_size; + rbf_data += buf_size; + + if (buf_size >= rbf_size) + buf_size = rbf_size; + + xfer_count++; + puts("."); + } else { + ret = invoke_smc( + INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE, + NULL, 0, res_buf, ARRAY_SIZE(res_buf)); + if (!ret) { + for (i = 0; i < ARRAY_SIZE(res_buf); i++) { + if (!res_buf[i]) + break; + xfer_count--; + wr_ret = 0; + retry = 0; + } + } else if (ret != + INTEL_SIP_SMC_STATUS_BUSY) + return ret; + else if (!xfer_count) + return INTEL_SIP_SMC_STATUS_ERROR; + + if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX) + return -ETIMEDOUT; + + udelay(20000); + } + WATCHDOG_RESET(); + } + + return 0; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for success, non-zero for error. + */ +int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + int ret; + u64 arg = 1; + + debug("Invoking FPGA_CONFIG_START...\n"); + + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0); + + if (ret) { + puts("Failure in RECONFIG mailbox command!\n"); + return ret; + } + + ret = send_bitstream(rbf_data, rbf_size); + if (ret) { + puts("Error sending bitstream!\n"); + return ret; + } + + /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + + debug("Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(); + if (ret) { + puts("FPGA reconfiguration failed!"); + return ret; + } + + puts("FPGA reconfiguration OK!\n"); + + return ret; +} + +#else + static const struct mbox_cfgstat_state { int err_no; const char *error_name; @@ -286,3 +424,4 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
return ret; } +#endif
From: Chee Hong Ang chee.hong.ang@intel.com
mbox_reset_cold() will invoke ATF's PSCI service when running in non-secure mode (EL2).
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/mailbox_s10.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 18d44924e6..429444f069 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -11,6 +11,7 @@ #include <asm/arch/mailbox_s10.h> #include <asm/arch/system_manager.h> #include <asm/secure.h> +#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + psci_system_reset(); +#else int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT, @@ -406,6 +410,7 @@ int mbox_reset_cold(void) /* mailbox sent failure, wait for watchdog to kick in */ hang(); } +#endif return 0; }
From: Chee Hong Ang chee.hong.ang@intel.com
Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- include/configs/socfpga_soc64_common.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 990f879b07..fdcd7d3e9a 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ + + 0x100000) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
From: Chee Hong Ang chee.hong.ang@intel.com
SPL already setup the Clock Manager with the handoff data from OCRAM. When the Clock Manager's driver get probed again in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index 3da85791a1..049c5711a8 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void) { +#ifdef CONFIG_SPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; @@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void) } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { return cm_handoff_cfg; } - +#endif return NULL; }
Add binman node to device tree to generate the FIT image for u-boot (u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 +++++++++++++++++++++++ arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++ arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- 4 files changed, 134 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index f0528a9ad9..08f7cf7f7a 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -2,9 +2,11 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> */
+#include "socfpga_soc64_fit-u-boot.dtsi" + /{ memory { #address-cells = <2>; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi new file mode 100644 index 0000000000..2d4d56a6df --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020 Intel Corporation <www.intel.com> + */ + +#if defined(CONFIG_FIT) + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + u-boot { + filename = "u-boot.itb"; + fit { + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + description = "FIT with firmware and bootloader"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot SoC64"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <0x00200000>; + + uboot_blob: blob { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = <0x00001000>; + entry = <0x00001000>; + + atf_blob: blob { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "U-Boot SoC64 flat device-tree"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Intel SoC64 FPGA"; + firmware = "atf"; + loadables = "uboot"; + fdt = "fdt"; + }; + }; + }; + }; + + kernel { + filename = "kernel.itb"; + fit { + description = "FIT with Linux kernel image and FDT blob"; + #address-cells = <1>; + + images { + kernel { + description = "Linux Kernel"; + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "none"; + load = <0x4080000>; + entry = <0x4080000>; + + kernel_blob: blob { + filename = "Image"; + }; + }; + + fdt { + description = "Linux DTB"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + + kernel_fdt_blob: blob { + filename = "linux.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Intel SoC64 FPGA"; + kernel = "kernel"; + fdt = "fdt"; + }; + }; + }; + }; +}; + +#endif diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi new file mode 100644 index 0000000000..3e3a378046 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020 Intel Corporation <www.intel.com> + */ + +#include "socfpga_soc64_fit-u-boot.dtsi" diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 2669abb383..61df425f14 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -2,9 +2,11 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> */
+#include "socfpga_stratix10-u-boot.dtsi" + /{ aliases { spi0 = &qspi;
Add new build target "fit-itb" for FIT image generation.
In preparation to support Vendor Authorized Boot (VAB) for Intel SOC64 device in near future. With VAB, u-boot proper, dtb and arm trusted firmware need to be signed before FIT image generation.
To align user experience for ATF boot with and without VAB feature, we skip binman for ARCH_SOCFPGA in default Makefile flow. User always use 'make fit-itb' to generate FIT image after successfully compile u-boot.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- Makefile | 7 +++++++ arch/arm/mach-socfpga/Kconfig | 2 ++ 2 files changed, 9 insertions(+)
diff --git a/Makefile b/Makefile index 59ba3330cd..b37aaa9561 100644 --- a/Makefile +++ b/Makefile @@ -1021,8 +1021,10 @@ inputs: $(INPUTS-y)
all: .binman_stamp inputs ifeq ($(CONFIG_BINMAN),y) +ifneq ($(CONFIG_ARCH_SOCFPGA),y) $(call if_changed,binman) endif +endif
# Timestamp file to make sure that binman always runs .binman_stamp: FORCE @@ -1608,6 +1610,11 @@ cmd_socnandboot = cat u-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@ u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE $(call if_changed,socnandboot)
+ifeq ($(CONFIG_FIT),y) +fit-itb: + $(call if_changed,binman) +endif + endif
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 01f5a1fc41..7fdb52dd83 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -37,6 +37,7 @@ config TARGET_SOCFPGA_AGILEX select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_CLK if SPL + select BINMAN
config TARGET_SOCFPGA_ARRIA5 bool @@ -79,6 +80,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select FPGA_INTEL_SDM_MAILBOX + select BINMAN
choice prompt "Altera SOCFPGA board select"
From: Chee Hong Ang chee.hong.ang@intel.com
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x200000 (CONFIG_SYS_TEXT_BASE). ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com --- configs/socfpga_agilex_atf_defconfig | 72 ++++++++++++++++++++++++++++++++ configs/socfpga_stratix10_atf_defconfig | 74 +++++++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+) create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig new file mode 100644 index 0000000000..ad87a8098f --- /dev/null +++ b/configs/socfpga_agilex_atf_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig new file mode 100644 index 0000000000..1005ba979e --- /dev/null +++ b/configs/socfpga_stratix10_atf_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y
Hi Siew,
On Tue, Nov 10, 2020 at 1:56 PM Siew Chin Lim elly.siew.chin.lim@intel.com wrote:
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Diamond Mesa are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex.
Patch status: Have changes: Patch 20, 22 Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 20:
- Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in socfpga_dm-u-boot.dtsi
Patch 22:
- Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to socfpga_dm_atf_defconfig. Use binman to generate FIT image instead of local script.
History:
These patchsets have dependency on:
Enable ARM Trusted Firmware for U-Boot https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly...
Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
Pali Rohár (1): Makefile: Fix calling make with V=1
Siew Chin Lim (2): arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman
Simon Glass (5): odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings x86: Provide default SMBIOS manufacturer/product smbios: Drop the unused Kconfig options
The above patches are already in u-boot/master now. You can drop these patches.
Regards, Bin
Hi All,
Kindly ignore "[v2,00/22] Add Intel Diamond Mesa SoC support" series of patches. Sorry that I make some mistake when send for review. I will resend this series. I sincerely apologize for the inconvenience caused
Thanks, Siew Chin
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Tuesday, November 10, 2020 1:55 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v2 00/22] Add Intel Diamond Mesa SoC support
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Diamond Mesa are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex.
Patch status: Have changes: Patch 20, 22 Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 20:
- Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in
socfpga_dm-u-boot.dtsi
Patch 22:
- Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to
socfpga_dm_atf_defconfig. Use binman to generate FIT image instead of local script.
History:
1-elly.siew.chin.lim@intel.com/
These patchsets have dependency on:
Enable ARM Trusted Firmware for U-Boot https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259- 1-elly.siew.chin.lim@intel.com/
c-devices/diamond-mesa-soc-devices.html
Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
Pali Rohár (1): Makefile: Fix calling make with V=1
Siew Chin Lim (2): arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman
Simon Glass (5): odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings x86: Provide default SMBIOS manufacturer/product smbios: Drop the unused Kconfig options
-- 2.13.0
participants (3)
-
Bin Meng -
Lim, Elly Siew Chin -
Siew Chin Lim