Currently fdt_fixup_stdout() is using hard-coded CONFIG_CONS_INDEX constant. With multi-serial support, the CONS_INDEX may no longer represent actual console, so we should try to extract port number from the current stdio device name instead of always hard-coding the constant value.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com Acked-by: Gerald Van Baren vanbaren@cideas.com --- common/fdt_support.c | 22 +++++++++++++++++++++- 1 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c index 89164a1..e01303a 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -22,6 +22,7 @@ */

#include <common.h> +#include <stdio_dev.h> #include <linux/ctype.h> #include <linux/types.h> #include <asm/global_data.h> @@ -90,6 +91,23 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, }

#ifdef CONFIG_OF_STDOUT_VIA_ALIAS + +#ifdef CONFIG_SERIAL_MULTI +static void fdt_fill_multisername(char *sername, size_t maxlen) +{ + const char *outname = stdio_devices[stdout]->name; + + if (strcmp(outname, "serial") > 0) + strncpy(sername, outname, maxlen); + + /* eserial? */ + if (strcmp(outname + 1, "serial") > 0) + strncpy(sername, outname + 1, maxlen); +} +#else +static inline void fdt_fill_multisername(char *sername, size_t maxlen) {} +#endif /* CONFIG_SERIAL_MULTI */ + static int fdt_fixup_stdout(void *fdt, int chosenoff) { int err = 0; @@ -98,7 +116,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff) char sername[9] = { 0 }; const char *path;

- sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1); + fdt_fill_multisername(sername, sizeof(sername) - 1); + if (!sername[0]) + sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);

err = node = fdt_path_offset(fdt, "/aliases"); if (node >= 0) {

eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups.

Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger).

So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8569mds/bcsr.h | 3 +- board/freescale/mpc8569mds/mpc8569mds.c | 116 +++++++++++++++++++++++++++++++ cpu/mpc85xx/speed.c | 4 + include/configs/MPC8569MDS.h | 16 ++++ 4 files changed, 138 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h index c4738d7..2ed57d8 100644 --- a/board/freescale/mpc8569mds/bcsr.h +++ b/board/freescale/mpc8569mds/bcsr.h @@ -33,7 +33,8 @@ #define BCSR6_UPC1_POS_EN 0x40 #define BCSR6_UPC1_ADDR_EN 0x20 #define BCSR6_UPC1_DEV2 0x10 -#define BCSR6_SD_ENABLE 0x04 +#define BCSR6_SD_CARD_1BIT 0x08 +#define BCSR6_SD_CARD_4BITS 0x04 #define BCSR6_TDM2G_EN 0x02 #define BCSR6_UCC7_RMII_EN 0x01

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index cc88731..2d07922 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -23,6 +23,7 @@ */

#include <common.h> +#include <hwconfig.h> #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> @@ -35,6 +36,7 @@ #include <ioports.h> #include <libfdt.h> #include <fdt_support.h> +#include <fsl_esdhc.h>

#include "bcsr.h"

@@ -303,6 +305,119 @@ local_bus_init(void) out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); }

+#ifdef CONFIG_FSL_ESDHC + +/* + * Because of an erratum in prototype boards it is impossible to use eSDHC + * without disabling UART0 (which makes it quite easy to 'brick' the board + * by simply issung 'setenv hwconfig esdhc', and not able to interact with + * U-Boot anylonger). + * + * So, but default we assume that the board is a prototype, which is a most + * safe assumption. There is no way to determine board revision from a + * register, so we use hwconfig. + */ + +static int prototype_board(void) +{ + if (hwconfig_subarg("board", "rev", NULL)) + return hwconfig_subarg_cmp("board", "rev", "prototype"); + return 1; +} + +static int esdhc_disables_uart0(void) +{ + return prototype_board() || + hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); +} + +int board_mmc_init(bd_t *bd) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; + u8 bcsr6 = BCSR6_SD_CARD_1BIT; + + if (!hwconfig("esdhc")) + return 0; + + printf("Enabling eSDHC...\n" + " For eSDHC to function, I2C2 "); + if (esdhc_disables_uart0()) { + printf("and UART0 should be disabled.\n"); + printf(" Redirecting stderr, stdout and stdin to UART1...\n"); + console_assign(stderr, "eserial1"); + console_assign(stdout, "eserial1"); + console_assign(stdin, "eserial1"); + printf("Switched to UART1 (initial log has been printed to " + "UART0).\n"); + bcsr6 |= BCSR6_SD_CARD_4BITS; + } else { + printf("should be disabled.\n"); + } + + /* Assign I2C2 signals to eSDHC. */ + clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, + PLPPAR1_ESDHC_VAL); + clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, + PLPDIR1_ESDHC_VAL); + + /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ + setbits_8(&bcsr[6], bcsr6); + + return fsl_esdhc_mmc_init(bd); +} + +static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) +{ + const char *status = "disabled"; + int off; + int err; + + if (!hwconfig("esdhc")) + return; + + if (!esdhc_disables_uart0()) + goto disable_i2c2; + + off = fdt_path_offset(blob, "serial0"); + if (off < 0) { + printf("WARNING: could not find serial0 alias: %s.\n", + fdt_strerror(off)); + goto disable_i2c2; + } + + err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); + if (err) { + printf("WARNING: could not set status for serial0: %s.\n", + fdt_strerror(err)); + return; + } + +disable_i2c2: + off = -1; + while (1) { + const u32 *idx; + int len; + + off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); + if (off < 0) + break; + + idx = fdt_getprop(blob, off, "cell-index", &len); + if (!idx || len != sizeof(*idx)) + continue; + + if (*idx == 1) { + fdt_setprop(blob, off, "status", status, + strlen(status) + 1); + break; + } + } +} +#else +static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} +#endif + #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ @@ -444,5 +559,6 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif + fdt_board_fixup_esdhc(blob, bd); } #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 0244b5c..7959082 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -240,8 +240,12 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk;

#if defined(CONFIG_FSL_ESDHC) +#ifdef CONFIG_MPC8569 + gd->sdhc_clk = gd->bus_clk; +#else gd->sdhc_clk = gd->bus_clk / 2; #endif +#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 32e747e..3d07a5b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -70,6 +70,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS 1

#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_HWCONFIG

#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 @@ -206,6 +207,7 @@ extern unsigned long get_clock_freq(void);

/* Serial Port */ #define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -258,8 +260,10 @@ extern unsigned long get_clock_freq(void);

#define PLPPAR1_I2C_BIT_MASK 0x0000000F #define PLPPAR1_I2C2_VAL 0x00000000 +#define PLPPAR1_ESDHC_VAL 0x0000000A #define PLPDIR1_I2C_BIT_MASK 0x0000000F #define PLPDIR1_I2C2_VAL 0x0000000F +#define PLPDIR1_ESDHC_VAL 0x00000006

/* * General PCI @@ -450,6 +454,18 @@ extern unsigned long get_clock_freq(void);

#undef CONFIG_WATCHDOG /* watchdog disabled */

+#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */

Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8569mds/tlb.c | 30 +++++++++++------------------- include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++ 2 files changed, 34 insertions(+), 19 deletions(-)

diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index d3b251e..3b8ee05 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = {

/* TLB 1 Initializations */ /* - * TLBe 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH (upper half) + * TLBe 0: 64M Non-cacheable, guarded * Out of reset this entry is only 4K. + * 0xfc000000 256K NAND FLASH (CS3) + * 0xfe000000 32M NOR FLASH (CS0) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_64M, 1),

/* - * TLBe 1: 16M Non-cacheable, guarded - * 0xfe000000 16M FLASH (lower half) + * TLBe 1: 256KB Non-cacheable, guarded + * 0xf8000000 32K BCSR + * 0xf8008000 32K PIB (CS4) + * 0xf8010000 32K PIB (CS5) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), + 0, 1, BOOKE_PAGESZ_256K, 1),

/* * TLBe 2: 256M Non-cacheable, guarded @@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), - - /* - * TLBe 5: 256K Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), };

int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3d07a5b..17ea3bb 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO

+/* Chip select 3 - NAND */ +#define CONFIG_SYS_NAND_BASE 0xFC000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) +#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */

/* * SDRAM on the LocalBus

This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8569mds/law.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c index e7381aa..60eea45 100644 --- a/board/freescale/mpc8569mds/law.c +++ b/board/freescale/mpc8569mds/law.c @@ -54,6 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), };

int num_law_entries = ARRAY_SIZE(law_table);

SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8569mds/mpc8569mds.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 2d07922..7d1d02e 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -154,6 +154,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 10, 2, 0, 3}, /* UART1_CTS_B */ {5, 11, 1, 0, 2}, /* UART1_RTS_B */

+ /* SPI Flash, M25P40 */ + {4, 27, 3, 0, 1}, /* SPI_MOSI */ + {4, 28, 3, 0, 1}, /* SPI_MISO */ + {4, 29, 3, 0, 1}, /* SPI_CLK */ + {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */ + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ };

To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node.

Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8569mds/bcsr.h | 1 + board/freescale/mpc8569mds/mpc8569mds.c | 98 ++++++++++++++++++++++++------- 2 files changed, 78 insertions(+), 21 deletions(-)

diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h index 2ed57d8..179a54c 100644 --- a/board/freescale/mpc8569mds/bcsr.h +++ b/board/freescale/mpc8569mds/bcsr.h @@ -68,6 +68,7 @@

#define BCSR15_SMII6_DIS 0x08 #define BCSR15_SMII8_DIS 0x04 +#define BCSR15_QEUART_EN 0x01

#define BCSR16_UPC1_DEV2 0x02

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 7d1d02e..ef99a75 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -154,6 +154,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 10, 2, 0, 3}, /* UART1_CTS_B */ {5, 11, 1, 0, 2}, /* UART1_RTS_B */

+ /* QE UART */ + {0, 19, 1, 0, 2}, /* QEUART_TX */ + {1, 17, 2, 0, 3}, /* QEUART_RX */ + {0, 25, 1, 0, 1}, /* QEUART_RTS */ + {1, 23, 2, 0, 1}, /* QEUART_CTS */ + /* SPI Flash, M25P40 */ {4, 27, 3, 0, 1}, /* SPI_MOSI */ {4, 28, 3, 0, 1}, /* SPI_MISO */ @@ -311,7 +317,26 @@ local_bus_init(void) out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); }

-#ifdef CONFIG_FSL_ESDHC +static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias) +{ + const char *status = "disabled"; + int off; + int err; + + off = fdt_path_offset(blob, alias); + if (off < 0) { + printf("WARNING: could not find %s alias: %s.\n", alias, + fdt_strerror(off)); + return; + } + + err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); + if (err) { + printf("WARNING: could not set status for serial0: %s.\n", + fdt_strerror(err)); + return; + } +}

/* * Because of an erratum in prototype boards it is impossible to use eSDHC @@ -337,6 +362,53 @@ static int esdhc_disables_uart0(void) hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); }

+static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd) +{ + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; + const char *devtype = "serial"; + const char *compat = "ucc_uart"; + const char *clk = "brg9"; + u32 portnum = 0; + int off = -1; + + if (!hwconfig("qe_uart")) + return; + + if (hwconfig("esdhc") && esdhc_disables_uart0()) { + printf("QE UART: won't enable with esdhc.\n"); + return; + } + + fdt_board_disable_serial(blob, bd, "serial1"); + + while (1) { + const u32 *idx; + int len; + + off = fdt_node_offset_by_compatible(blob, off, "ucc_geth"); + if (off < 0) { + printf("WARNING: unable to fixup device tree for " + "QE UART\n"); + return; + } + + idx = fdt_getprop(blob, off, "cell-index", &len); + if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) + continue; + break; + } + + fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1); + fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1); + fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); + fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); + fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); + + setbits_8(&bcsr[15], BCSR15_QEUART_EN); +} + +#ifdef CONFIG_FSL_ESDHC + int board_mmc_init(bd_t *bd) { struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; @@ -376,31 +448,14 @@ int board_mmc_init(bd_t *bd) static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) { const char *status = "disabled"; - int off; - int err; + int off = -1;

if (!hwconfig("esdhc")) return;

- if (!esdhc_disables_uart0()) - goto disable_i2c2; - - off = fdt_path_offset(blob, "serial0"); - if (off < 0) { - printf("WARNING: could not find serial0 alias: %s.\n", - fdt_strerror(off)); - goto disable_i2c2; - } - - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); - if (err) { - printf("WARNING: could not set status for serial0: %s.\n", - fdt_strerror(err)); - return; - } + if (esdhc_disables_uart0()) + fdt_board_disable_serial(blob, bd, "serial0");

-disable_i2c2: - off = -1; while (1) { const u32 *idx; int len; @@ -566,5 +621,6 @@ void ft_board_setup(void *blob, bd_t *bd) ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif fdt_board_fixup_esdhc(blob, bd); + fdt_board_fixup_qe_uart(blob, bd); } #endif

Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8569mds/bcsr.h | 4 +++ board/freescale/mpc8569mds/mpc8569mds.c | 32 +++++++++++++++++++++++++++++++ drivers/qe/fdt.c | 2 + 3 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h index 179a54c..091b69c 100644 --- a/board/freescale/mpc8569mds/bcsr.h +++ b/board/freescale/mpc8569mds/bcsr.h @@ -72,6 +72,10 @@

#define BCSR16_UPC1_DEV2 0x02

+#define BCSR17_nUSBEN 0x80 +#define BCSR17_nUSBLOWSPD 0x40 +#define BCSR17_USBVCC 0x20 +#define BCSR17_USBMODE 0x10 #define BCSR17_FLASH_nWP 0x01

/*BCSR Utils functions*/ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index ef99a75..cdd7813 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -160,6 +160,15 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 25, 1, 0, 1}, /* QEUART_RTS */ {1, 23, 2, 0, 1}, /* QEUART_CTS */

+ /* QE USB */ + {5, 3, 1, 0, 1}, /* USB_OE */ + {5, 4, 1, 0, 2}, /* USB_TP */ + {5, 5, 1, 0, 2}, /* USB_TN */ + {5, 6, 2, 0, 2}, /* USB_RP */ + {5, 7, 2, 0, 1}, /* USB_RX */ + {5, 8, 2, 0, 1}, /* USB_RN */ + {2, 4, 2, 0, 2}, /* CLK5 */ + /* SPI Flash, M25P40 */ {4, 27, 3, 0, 1}, /* SPI_MOSI */ {4, 28, 3, 0, 1}, /* SPI_MISO */ @@ -479,6 +488,28 @@ static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} #endif

+static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) +{ + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; + + if (hwconfig_subarg_cmp("qe_usb", "speed", "low")) + clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); + else + setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); + + if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { + clrbits_8(&bcsr[17], BCSR17_USBVCC); + clrbits_8(&bcsr[17], BCSR17_USBMODE); + do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", + "peripheral", sizeof("peripheral"), 1); + } else { + setbits_8(&bcsr[17], BCSR17_USBVCC); + setbits_8(&bcsr[17], BCSR17_USBMODE); + } + + clrbits_8(&bcsr[17], BCSR17_nUSBEN); +} + #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ @@ -622,5 +653,6 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_board_fixup_esdhc(blob, bd); fdt_board_fixup_qe_uart(blob, bd); + fdt_board_fixup_qe_usb(blob, bd); } #endif diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index 5307488..d7c7d13 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -85,6 +85,8 @@ void ft_qe_setup(void *blob) "bus-frequency", gd->qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "brg-frequency", gd->brg_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe-gtm", + "clock-frequency", gd->qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); #endif }