[U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?
Hi, I ran into problems when i enabled D cache. But later i found out that cache flush was required before enabling D Cache. What i dont understand is why is it required?. Since earlier D cache is never enabled and so nothing should be present in the cache. Flushing is only required during context switch/may be interrupts?. I tried with omap3 board with Arm cortex A8 on it, it worked without a cache flush. I tried with C110 with Arm cortex A8 on it, i had to do a cache flush to make D cache work. Also if possible please tell me what is a GP device, OMAP3 (CONTROL_STATUS register) seems to be a GP device and hence they are skipping cache flush. I dont know what is this.
Warm Regards, Akshay
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akshay ts wrote:
Hi, I ran into problems when i enabled D cache. But later i found out that cache flush was required before enabling D Cache.
Flush or invalidate? See below...
What i dont understand is why is it required?. Since earlier D cache is never enabled and so nothing should be present in the cache. Flushing is only required during context switch/may be interrupts?. I tried with omap3 board with Arm cortex A8 on it, it worked without a cache flush. I tried with C110 with Arm cortex A8 on it, i had to do a cache flush to make D cache work.
There was some info on this at Linux ARM kernel mailing list:
http://www.spinics.net/lists/arm-kernel/msg71406.html
Seems that it depends on how silicon (reset?) is implemented.
Also if possible please tell me what is a GP device, OMAP3 (CONTROL_STATUS register) seems to be a GP device and hence they are skipping cache flush. I dont know what is this.
GP is "general purpose". Anybody might correct me, but I think these are OMAPs where (HW) security features you might need in mobile applications are disabled. So depending if you buy low quantity OMAPs for general purpose use (I think called "catalog products") or in large OEM quantities you might get OMAPs with different (security) features enabled in HW or not. BeagleBoard uses GP devices.
Best regards
Dirk
Hi Dirk,
Thanks i got some useful information.
Warm Regards, Akshay
--- On Thu, 10/9/09, Dirk Behme dirk.behme@googlemail.com wrote:
From: Dirk Behme dirk.behme@googlemail.com Subject: Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache? To: "akshay ts" takshays@yahoo.co.in Cc: u-boot@lists.denx.de Date: Thursday, 10 September, 2009, 12:14 AM akshay ts wrote:
Hi, I ran into problems when i enabled D cache. But later
i found out that cache flush was required before enabling D Cache.
Flush or invalidate? See below...
What i dont understand is why is it required?. Since
earlier D cache is never enabled and so nothing should be present in the cache. Flushing is only required during context switch/may be interrupts?. I tried with omap3 board with Arm cortex A8 on it, it worked without a cache flush. I tried with C110 with Arm cortex A8 on it, i had to do a cache flush to make D cache work.
There was some info on this at Linux ARM kernel mailing list:
http://www.spinics.net/lists/arm-kernel/msg71406.html
Seems that it depends on how silicon (reset?) is implemented.
Also if possible please tell me what is a GP device,
OMAP3 (CONTROL_STATUS register) seems to be a GP device and hence they are skipping cache flush. I dont know what is this.
GP is "general purpose". Anybody might correct me, but I think these are OMAPs where (HW) security features you might need in mobile applications are disabled. So depending if you buy low quantity OMAPs for general purpose use (I think called "catalog products") or in large OEM quantities you might get OMAPs with different (security) features enabled in HW or not. BeagleBoard uses GP devices.
Best regards
Dirk
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participants (2)
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akshay ts -
Dirk Behme