[U-Boot] [PATCH v3 0/9] mmc: sunxi: Enable DM_MMC
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3: - Handle clock via CLK framework. Changes for v2: - update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
arch/arm/Kconfig | 1 + arch/arm/dts/sunxi-u-boot.dtsi | 4 ++ arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - drivers/clk/sunxi/clk_a10.c | 4 ++ drivers/clk/sunxi/clk_a10s.c | 3 + drivers/clk/sunxi/clk_a23.c | 6 ++ drivers/clk/sunxi/clk_a31.c | 8 +++ drivers/clk/sunxi/clk_a64.c | 6 ++ drivers/clk/sunxi/clk_a80.c | 28 ++++++++- drivers/clk/sunxi/clk_a83t.c | 6 ++ drivers/clk/sunxi/clk_h3.c | 6 ++ drivers/clk/sunxi/clk_h6.c | 6 ++ drivers/clk/sunxi/clk_r40.c | 8 +++ drivers/clk/sunxi/clk_v3s.c | 6 ++ drivers/mmc/sunxi_mmc.c | 84 +++++++++++++++++++++++++-- 16 files changed, 170 insertions(+), 8 deletions(-)
From: Andre Przywara andre.przywara@arm.com
Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the MMC driver.
Signed-off-by: Andre Przywara andre.przywara@arm.com [jagan: add V3S gates/resets, fix CLK_AHB1_MMC3 bit] Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 4 ++++ drivers/clk/sunxi/clk_a10s.c | 3 +++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 8 ++++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ drivers/clk/sunxi/clk_h6.c | 6 ++++++ drivers/clk/sunxi/clk_r40.c | 8 ++++++++ drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 10 files changed, 59 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index b00f51af8b..2aa41efe17 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index aa904ce067..87b74e52dc 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_OTG] = GATE(0x060, BIT(0)), [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 854259bf81..1ef2359286 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
static struct ccu_clk_gate a23_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), @@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a38d76cb7c..fa81f9a710 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -13,6 +13,10 @@ #include <dt-bindings/reset/sun6i-a31-ccu.h>
static struct ccu_clk_gate a31_gates[] = { + [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB1_MMC3] = GATE(0x060, BIT(12)), [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)), @@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
+ [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)), + [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), + [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), + [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index a2ba6eefc5..910275fbce 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun50i-a64-ccu.h>
static const struct ccu_clk_gate a64_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), @@ -38,6 +41,9 @@ static const struct ccu_reset a64_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 1ef6ac5b25..b5a555da36 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-a83t-ccu.h>
static struct ccu_clk_gate a83t_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), @@ -36,6 +39,9 @@ static struct ccu_reset a83t_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f82949b3b6..98af372ec5 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-h3-ccu.h>
static struct ccu_clk_gate h3_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), @@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = { [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 0da3a40e3d..902612da91 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun50i-h6-ccu.h>
static struct ccu_clk_gate h6_gates[] = { + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), @@ -20,6 +23,9 @@ static struct ccu_clk_gate h6_gates[] = { };
static struct ccu_reset h6_resets[] = { + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), [RST_BUS_UART0] = RESET(0x90c, BIT(16)), [RST_BUS_UART1] = RESET(0x90c, BIT(17)), [RST_BUS_UART2] = RESET(0x90c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index fd7aae97ea..b9457e1971 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -13,6 +13,10 @@ #include <dt-bindings/reset/sun8i-r40-ccu.h>
static struct ccu_clk_gate r40_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), [CLK_BUS_OTG] = GATE(0x060, BIT(25)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), @@ -43,6 +47,10 @@ static struct ccu_reset r40_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), [RST_BUS_OTG] = RESET(0x2c0, BIT(25)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 25ad87500e..c8a9027889 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-v3s-ccu.h>
static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)), @@ -25,6 +28,9 @@ static struct ccu_clk_gate v3s_gates[] = { static struct ccu_reset v3s_resets[] = { [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
On 21/01/2019 10:31, Jagan Teki wrote:
From: Andre Przywara andre.przywara@arm.com
Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the MMC driver.
Signed-off-by: Andre Przywara andre.przywara@arm.com [jagan: add V3S gates/resets, fix CLK_AHB1_MMC3 bit]
Thanks for adding the V3S (looks correct to me), but the CLK_AHB1_MMC3 for the A31 smells like a Linux bug copied: According to the manual this is bit 11, and Linux seems to be off-by-one here (check the next bit!). Sent a fix for Linux. Please set this back to bit 11 here.
Cheers, Andre.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/clk/sunxi/clk_a10.c | 4 ++++ drivers/clk/sunxi/clk_a10s.c | 3 +++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 8 ++++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ drivers/clk/sunxi/clk_h6.c | 6 ++++++ drivers/clk/sunxi/clk_r40.c | 8 ++++++++ drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 10 files changed, 59 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index b00f51af8b..2aa41efe17 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index aa904ce067..87b74e52dc 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_OTG] = GATE(0x060, BIT(0)), [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)),
[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 854259bf81..1ef2359286 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
static struct ccu_clk_gate a23_gates[] = {
- [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
- [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
- [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
@@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
- [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
- [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a38d76cb7c..fa81f9a710 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -13,6 +13,10 @@ #include <dt-bindings/reset/sun6i-a31-ccu.h>
static struct ccu_clk_gate a31_gates[] = {
- [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
- [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
- [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
- [CLK_AHB1_MMC3] = GATE(0x060, BIT(12)), [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
@@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
- [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
- [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
- [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
- [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index a2ba6eefc5..910275fbce 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun50i-a64-ccu.h>
static const struct ccu_clk_gate a64_gates[] = {
- [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
- [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
- [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
@@ -38,6 +41,9 @@ static const struct ccu_reset a64_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
- [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
- [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 1ef6ac5b25..b5a555da36 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-a83t-ccu.h>
static struct ccu_clk_gate a83t_gates[] = {
- [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
- [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
- [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
@@ -36,6 +39,9 @@ static struct ccu_reset a83t_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
- [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
- [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f82949b3b6..98af372ec5 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-h3-ccu.h>
static struct ccu_clk_gate h3_gates[] = {
- [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
- [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
- [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
@@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = { [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(9)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 0da3a40e3d..902612da91 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun50i-h6-ccu.h>
static struct ccu_clk_gate h6_gates[] = {
- [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
- [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
- [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
@@ -20,6 +23,9 @@ static struct ccu_clk_gate h6_gates[] = { };
static struct ccu_reset h6_resets[] = {
- [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
- [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
- [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), [RST_BUS_UART0] = RESET(0x90c, BIT(16)), [RST_BUS_UART1] = RESET(0x90c, BIT(17)), [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index fd7aae97ea..b9457e1971 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -13,6 +13,10 @@ #include <dt-bindings/reset/sun8i-r40-ccu.h>
static struct ccu_clk_gate r40_gates[] = {
- [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
- [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
- [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
- [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), [CLK_BUS_OTG] = GATE(0x060, BIT(25)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
@@ -43,6 +47,10 @@ static struct ccu_reset r40_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
- [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
- [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
- [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
- [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), [RST_BUS_OTG] = RESET(0x2c0, BIT(25)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 25ad87500e..c8a9027889 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-v3s-ccu.h>
static struct ccu_clk_gate v3s_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
@@ -25,6 +28,9 @@ static struct ccu_clk_gate v3s_gates[] = { static struct ccu_reset v3s_resets[] = { [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
From: Andre Przywara andre.przywara@arm.com
The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that.
Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game.
Signed-off-by: Andre Przywara andre.przywara@arm.com [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a80.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index d6dd6a1fa1..efcc7a433d 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -30,19 +30,45 @@ static const struct ccu_reset a80_resets[] = { [RST_BUS_UART5] = RESET(0x5b4, BIT(21)), };
+static const struct ccu_clk_gate a80_mmc_gates[] = { + [0] = GATE(0x0, BIT(16)), + [1] = GATE(0x4, BIT(16)), + [2] = GATE(0x8, BIT(16)), + [3] = GATE(0xc, BIT(16)), +}; + +static const struct ccu_reset a80_mmc_resets[] = { + [0] = GATE(0x0, BIT(18)), + [1] = GATE(0x4, BIT(18)), + [2] = GATE(0x8, BIT(18)), + [3] = GATE(0xc, BIT(18)), +}; + static const struct ccu_desc a80_ccu_desc = { .gates = a80_gates, .resets = a80_resets, };
+static const struct ccu_desc a80_mmc_clk_desc = { + .gates = a80_mmc_gates, + .resets = a80_mmc_resets, +}; + static int a80_clk_bind(struct udevice *dev) { - return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets)); + ulong count = ARRAY_SIZE(a80_resets); + + if (device_is_compatible(dev, "allwinner,allwinner,sun9i-a80-mmc")) + count = ARRAY_SIZE(a80_mmc_resets); + + return sunxi_reset_bind(dev, count); }
static const struct udevice_id a80_ccu_ids[] = { { .compatible = "allwinner,sun9i-a80-ccu", .data = (ulong)&a80_ccu_desc }, + { .compatible = "allwinner,sun9i-a80-mmc-config-clk", + .data = (ulong)&a80_mmc_clk_desc }, { } };
Add emmc compatible for A83T SoC.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 302332bf97..ec4f227130 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -693,6 +693,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun7i-a20-mmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun8i-a83t-emmc", + .data = (ulong)&sun4i_a10_variant, + }, { /* sentinel */ } };
On 21/01/2019 10:31, Jagan Teki wrote:
Add emmc compatible for A83T SoC.
You could merge this one with the next patch.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre.
drivers/mmc/sunxi_mmc.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 302332bf97..ec4f227130 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -693,6 +693,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun7i-a20-mmc", .data = (ulong)&sun4i_a10_variant, },
- {
.compatible = "allwinner,sun8i-a83t-emmc",.data = (ulong)&sun4i_a10_variant,- }, { /* sentinel */ }
};
Added H5, A64 compatible for mmc and emmc.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index ec4f227130..1259e627cc 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -697,6 +697,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun50i-a64-mmc", + .data = (ulong)&sun4i_a10_variant, + }, + { + .compatible = "allwinner,sun50i-a64-emmc", + .data = (ulong)&sun4i_a10_variant, + }, { /* sentinel */ } };
On 21/01/2019 10:31, Jagan Teki wrote:
Added H5, A64 compatible for mmc and emmc.
As mentioned, could be merged with the previous patch.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre
drivers/mmc/sunxi_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index ec4f227130..1259e627cc 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -697,6 +697,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun4i_a10_variant, },
- {
.compatible = "allwinner,sun50i-a64-mmc",.data = (ulong)&sun4i_a10_variant,- },
- {
.compatible = "allwinner,sun50i-a64-emmc",.data = (ulong)&sun4i_a10_variant,- }, { /* sentinel */ }
};
Unlike other Allwinner SoC's, H6 comes with different clock and reset control offset values. So support them via driver data.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1259e627cc..1e13a0665d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, };
+static const struct sunxi_mmc_variant sun50i_h6_variant = { + .mclk_offset = 0x830, +}; + static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc", @@ -705,6 +709,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun50i-a64-emmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun50i-h6-mmc", + .data = (ulong)&sun50i_h6_variant, + }, + { + .compatible = "allwinner,sun50i-h6-emmc", + .data = (ulong)&sun50i_h6_variant, + }, { /* sentinel */ } };
On 21/01/2019 10:31, Jagan Teki wrote:
Unlike other Allwinner SoC's, H6 comes with different clock and reset control offset values. So support them via driver data.
Nit: It's just the mod clock offset we care about here, the rest is already handled by the new clock driver.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre.
drivers/mmc/sunxi_mmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1259e627cc..1e13a0665d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, };
+static const struct sunxi_mmc_variant sun50i_h6_variant = {
- .mclk_offset = 0x830,
+};
static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc", @@ -705,6 +709,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun50i-a64-emmc", .data = (ulong)&sun4i_a10_variant, },
- {
.compatible = "allwinner,sun50i-h6-mmc",.data = (ulong)&sun50i_h6_variant,- },
- {
.compatible = "allwinner,sun50i-h6-emmc",.data = (ulong)&sun50i_h6_variant,- }, { /* sentinel */ }
};
Unlike other Allwinner SoC's, A80 comes with different ahb gate clock offset values and also has mmc common controller. So support them via driver data.
Cc: Rask Ingemann Lambertsen rask@formelder.dk Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1e13a0665d..0c443a732d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, };
+static const struct sunxi_mmc_variant sun9i_a80_variant = { + .mclk_offset = 0x410, +}; + static const struct sunxi_mmc_variant sun50i_h6_variant = { .mclk_offset = 0x830, }; @@ -701,6 +705,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun9i-a80-mmc", + .data = (ulong)&sun9i_a80_variant, + }, { .compatible = "allwinner,sun50i-a64-mmc", .data = (ulong)&sun4i_a10_variant,
On 21/01/2019 10:31, Jagan Teki wrote:
Unlike other Allwinner SoC's, A80 comes with different ahb gate clock offset values and also has mmc common controller. So support them via driver data.
As mentioned in the fix I sent, this requires the clock and reset support for CCU devices themselves before it can work.
With that fix applied before that patch in a series:
Cc: Rask Ingemann Lambertsen rask@formelder.dk Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre.
drivers/mmc/sunxi_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1e13a0665d..0c443a732d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, };
+static const struct sunxi_mmc_variant sun9i_a80_variant = {
- .mclk_offset = 0x410,
+};
static const struct sunxi_mmc_variant sun50i_h6_variant = { .mclk_offset = 0x830, }; @@ -701,6 +705,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun4i_a10_variant, },
- {
.compatible = "allwinner,sun9i-a80-mmc",.data = (ulong)&sun9i_a80_variant,- }, { .compatible = "allwinner,sun50i-a64-mmc", .data = (ulong)&sun4i_a10_variant,
Now CLK and RESET driver for Allwinner SoC are available, so add the relevant operations on mmc sunxi driver.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Changes for v3: - Grab changes for ML
drivers/mmc/sunxi_mmc.c | 52 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 0c443a732d..3c17958c95 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -8,10 +8,12 @@ */
#include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> #include <mmc.h> +#include <reset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cpu.h> @@ -21,7 +23,6 @@
#ifdef CONFIG_DM_MMC struct sunxi_mmc_variant { - u16 gate_offset; u16 mclk_offset; }; #endif @@ -41,6 +42,8 @@ struct sunxi_mmc_priv { struct mmc_config cfg; #ifdef CONFIG_DM_MMC const struct sunxi_mmc_variant *variant; + struct clk clk_ahb; + struct reset_ctl reset; #endif };
@@ -602,6 +605,32 @@ static const struct dm_mmc_ops sunxi_mmc_ops = { .get_cd = sunxi_mmc_getcd, };
+static int sunxi_mmc_enable(struct udevice *dev) +{ + struct sunxi_mmc_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_enable(&priv->clk_ahb); + if (ret) { + dev_err(dev, "failed to enable AHB clock\n"); + return ret; + } + + if (reset_valid(&priv->reset)) { + ret = reset_deassert(&priv->reset); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + goto err_clk_ahb; + } + } + + return 0; + +err_clk_ahb: + clk_disable(&priv->clk_ahb); + return ret; +} + static int sunxi_mmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -609,7 +638,7 @@ static int sunxi_mmc_probe(struct udevice *dev) struct sunxi_mmc_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; struct ofnode_phandle_args args; - u32 *gate_reg, *ccu_reg; + u32 *ccu_reg; int bus_width, ret;
cfg->name = dev->name; @@ -641,8 +670,22 @@ static int sunxi_mmc_probe(struct udevice *dev) priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; priv->mclkreg = (void *)ccu_reg + (priv->variant->mclk_offset + (priv->mmc_no * 4)); - gate_reg = (void *)ccu_reg + priv->variant->gate_offset; - setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no))); + + ret = clk_get_by_name(dev, "ahb", &priv->clk_ahb); + if (ret) { + dev_err(dev, "failed to get AHB clock\n"); + return ret; + } + + ret = reset_get_by_name(dev, "ahb", &priv->reset); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get reset\n"); + return ret; + } + + ret = sunxi_mmc_enable(dev); + if (ret) + return ret;
ret = mmc_set_mod_clk(priv, 24000000); if (ret) @@ -676,7 +719,6 @@ static int sunxi_mmc_bind(struct udevice *dev) }
static const struct sunxi_mmc_variant sun4i_a10_variant = { - .gate_offset = 0x60, .mclk_offset = 0x88, };
On 21/01/2019 10:31, Jagan Teki wrote:
Now CLK and RESET driver for Allwinner SoC are available, so add the relevant operations on mmc sunxi driver.
Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Changes for v3:
- Grab changes for ML
drivers/mmc/sunxi_mmc.c | 52 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 0c443a732d..3c17958c95 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -8,10 +8,12 @@ */
#include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> #include <mmc.h> +#include <reset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cpu.h> @@ -21,7 +23,6 @@
#ifdef CONFIG_DM_MMC struct sunxi_mmc_variant {
- u16 gate_offset; u16 mclk_offset;
}; #endif @@ -41,6 +42,8 @@ struct sunxi_mmc_priv { struct mmc_config cfg; #ifdef CONFIG_DM_MMC const struct sunxi_mmc_variant *variant;
- struct clk clk_ahb;
- struct reset_ctl reset;
Where is that used again outside of the probe() function?
#endif };
@@ -602,6 +605,32 @@ static const struct dm_mmc_ops sunxi_mmc_ops = { .get_cd = sunxi_mmc_getcd, };
+static int sunxi_mmc_enable(struct udevice *dev) +{
- struct sunxi_mmc_priv *priv = dev_get_priv(dev);
- int ret;
- ret = clk_enable(&priv->clk_ahb);
- if (ret) {
dev_err(dev, "failed to enable AHB clock\n");return ret;- }
- if (reset_valid(&priv->reset)) {
ret = reset_deassert(&priv->reset);if (ret) {dev_err(dev, "failed to deassert reset\n");goto err_clk_ahb;}- }
- return 0;
+err_clk_ahb:
- clk_disable(&priv->clk_ahb);
- return ret;
+}
Frankly, that's a lots of lines for very little effect. Why not just use the much smaller version I had and add an "else dev_err(...)" to it, if you are keen about error reports? Saves you the variables, saves you the reset_valid() call, saves you the extra function. Less code to read, smaller image, less bugs.
Cheers, Andre.
static int sunxi_mmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -609,7 +638,7 @@ static int sunxi_mmc_probe(struct udevice *dev) struct sunxi_mmc_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; struct ofnode_phandle_args args;
- u32 *gate_reg, *ccu_reg;
u32 *ccu_reg; int bus_width, ret;
cfg->name = dev->name;
@@ -641,8 +670,22 @@ static int sunxi_mmc_probe(struct udevice *dev) priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; priv->mclkreg = (void *)ccu_reg + (priv->variant->mclk_offset + (priv->mmc_no * 4));
- gate_reg = (void *)ccu_reg + priv->variant->gate_offset;
- setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
ret = clk_get_by_name(dev, "ahb", &priv->clk_ahb);
if (ret) {
dev_err(dev, "failed to get AHB clock\n");return ret;}
ret = reset_get_by_name(dev, "ahb", &priv->reset);
if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get reset\n");return ret;}
ret = sunxi_mmc_enable(dev);
if (ret)
return ret;ret = mmc_set_mod_clk(priv, 24000000); if (ret)
@@ -676,7 +719,6 @@ static int sunxi_mmc_bind(struct udevice *dev) }
static const struct sunxi_mmc_variant sun4i_a10_variant = {
- .gate_offset = 0x60, .mclk_offset = 0x88,
};
Enable DM_MMC for all Allwinner SoCs, this will eventually enable BLK.
Also removed DM_MMC enablement in few parts of sunxi configurations.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a23cbd5719..075c3dfe81 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -851,6 +851,7 @@ config ARCH_SUNXI select DM_ETH select DM_GPIO select DM_KEYBOARD + select DM_MMC if MMC select DM_SERIAL select DM_USB if DISTRO_DEFAULTS select OF_BOARD_SETUP diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3c54f5106d..74e234cded 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -154,7 +154,6 @@ config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A select ARM_CORTEX_CPU_IS_UP - select DM_MMC if MMC select DM_SCSI if SCSI select PHY_SUN4I_USB select DRAM_SUN4I diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 9156f132d1..18f658e96b 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_SCSI_AHCI=y -CONFIG_DM_MMC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y
On 21/01/2019 10:31, Jagan Teki wrote:
Enable DM_MMC for all Allwinner SoCs, this will eventually enable BLK.
Also removed DM_MMC enablement in few parts of sunxi configurations.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre
arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a23cbd5719..075c3dfe81 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -851,6 +851,7 @@ config ARCH_SUNXI select DM_ETH select DM_GPIO select DM_KEYBOARD
- select DM_MMC if MMC select DM_SERIAL select DM_USB if DISTRO_DEFAULTS select OF_BOARD_SETUP
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3c54f5106d..74e234cded 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -154,7 +154,6 @@ config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A select ARM_CORTEX_CPU_IS_UP
- select DM_MMC if MMC select DM_SCSI if SCSI select PHY_SUN4I_USB select DRAM_SUN4I
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 9156f132d1..18f658e96b 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_SCSI_AHCI=y -CONFIG_DM_MMC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ { + aliases { + mmc1 = &mmc2; + }; + binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;
On Mon, Jan 21, 2019 at 6:32 PM Jagan Teki jagan@amarulasolutions.com wrote:
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ {
aliases {mmc1 = &mmc2;};binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;-- 2.18.0.321.gffc6fa0e3
Slightly curious. What happens when mmc1 (the real mmc1) is enabled and probes before mmc2 does? Does it take mmc1? What happens then when mmc2 probes and wants mmc1?
Also, on the A31, we use mmc3 instead of mmc2 for eMMC. Only mmc3 supports DDR transfer modes.
ChenYu
On Mon, Jan 21, 2019 at 4:12 PM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:32 PM Jagan Teki jagan@amarulasolutions.com wrote:
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ {
aliases {mmc1 = &mmc2;};binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;-- 2.18.0.321.gffc6fa0e3
Slightly curious. What happens when mmc1 (the real mmc1) is enabled and probes before mmc2 does? Does it take mmc1? What happens then when mmc2 probes and wants mmc1?
Existing sunxi code has MMC_SUNXI_SLOT_EXTRA if the board has second MMC device, like eMMC which make default env or fastboot device as 1. But with DT definitions eMMC can be probed as mmc2 which can fail to get env and fastboot setups.
This override mmc2 to as mmc1 can satisfy the existing code identification. I did many code changes to get rid of DT changes but it became hard to get via those[1], patch 27 to 31
Also, on the A31, we use mmc3 instead of mmc2 for eMMC. Only mmc3 supports DDR transfer modes.
Yes, but as per current usage no board is using all together, if some board is using then, it's their duty to enable the same via defconfig in future.
On Mon, Jan 21, 2019 at 7:07 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Mon, Jan 21, 2019 at 4:12 PM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:32 PM Jagan Teki jagan@amarulasolutions.com wrote:
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ {
aliases {mmc1 = &mmc2;};binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;-- 2.18.0.321.gffc6fa0e3
Slightly curious. What happens when mmc1 (the real mmc1) is enabled and probes before mmc2 does? Does it take mmc1? What happens then when mmc2 probes and wants mmc1?
Existing sunxi code has MMC_SUNXI_SLOT_EXTRA if the board has second MMC device, like eMMC which make default env or fastboot device as 1. But with DT definitions eMMC can be probed as mmc2 which can fail to get env and fastboot setups.
This override mmc2 to as mmc1 can satisfy the existing code identification. I did many code changes to get rid of DT changes but it became hard to get via those[1], patch 27 to 31
So it looks like aliases take precedence over auto-numbering, even if an auto-numbered device is already probed. See
https://elixir.bootlin.com/u-boot/latest/source/drivers/block/blk-uclass.c#L...
That was the bit of detail that I was asking about. My question was what happens to the original mmc1 when mmc2 probes/binds with the mmc1 alias. So the result should be that mmc0 is still mmc0, mmc2 becomes mmc1, and mmc1 becomes mmc2. It would've been nice to see it in the commit log. It would explain why and how it works, and more importantly, why it doesn't screw up the system.
Also, on the A31, we use mmc3 instead of mmc2 for eMMC. Only mmc3 supports DDR transfer modes.
Yes, but as per current usage no board is using all together, if some board is using then, it's their duty to enable the same via defconfig in future.
I see. Looks like we got lucky.
I realize now that everything was explained in the commit log. However it lacks a bit of underlying knowledge or context, as I mentioned above. IMO these details are important, as they are basically your assumptions when doing the changes.
ChenYu
On Mon, Jan 21, 2019 at 2:32 AM Jagan Teki jagan@amarulasolutions.com wrote:
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
It doesn't work on Pinebook - where we have mmc0 (SD card), mmc1 (SDIO), mmc2 (eMMC). It still enumerates mmc2 as mmc2.
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ {
aliases {mmc1 = &mmc2;};binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;-- 2.18.0.321.gffc6fa0e3
On Mon, Jan 21, 2019 at 9:08 PM Vasily Khoruzhick anarsoul@gmail.com wrote:
On Mon, Jan 21, 2019 at 2:32 AM Jagan Teki jagan@amarulasolutions.com wrote:
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
It doesn't work on Pinebook - where we have mmc0 (SD card), mmc1 (SDIO), mmc2 (eMMC). It still enumerates mmc2 as mmc2.
BPI-M64 has same, here is log
U-Boot 2019.01-00171-g1fa1610a2a-dirty (Jan 21 2019 - 21:12:21 +0530) Allwinner Technology
CPU: Allwinner A64 (SUN50I) Model: BananaPi-M64 DRAM: 2 GiB MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c10000' mmc@1c0f000: 0, mmc@1c10000: 2, mmc@1c11000: 1 Loading Environment from FAT... OK In: serial Out: serial Err: serial Allwinner mUSB OTG (Peripheral) Net: phy interface7 eth0: ethernet@1c30000, eth1: usb_ether starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 USB2: USB EHCI 1.00 USB3: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found scanning bus 1 for devices... 1 USB Device(s) found scanning bus 2 for devices... 2 USB Device(s) found scanning bus 3 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0 => => => mmc list mmc@1c0f000: 0 mmc@1c10000: 2 mmc@1c11000: 1 (eMMC) => mmc dev 0 switch to partitions #0, OK mmc0 is current device => mmc list mmc@1c0f000: 0 (SD) mmc@1c10000: 2 mmc@1c11000: 1 (eMMC)
On Mon, Jan 21, 2019 at 7:46 AM Jagan Teki jagan@amarulasolutions.com wrote:
On Mon, Jan 21, 2019 at 9:08 PM Vasily Khoruzhick anarsoul@gmail.com wrote: scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0 => => => mmc list mmc@1c0f000: 0 mmc@1c10000: 2 mmc@1c11000: 1 (eMMC) => mmc dev 0 switch to partitions #0, OK mmc0 is current device => mmc list mmc@1c0f000: 0 (SD) mmc@1c10000: 2 mmc@1c11000: 1 (eMMC)
For me it shows:
=> mmc list mmc@1c0f000: 0 (SD) mmc@1c10000: 1 mmc@1c11000: 2
I'm testing this patches applied onto u-boot-sunxi/master on Pinebook. I tried 'distclean', and it doesn't help.
On Mon, Jan 21, 2019 at 8:24 PM Vasily Khoruzhick anarsoul@gmail.com wrote:
For me it shows:
=> mmc list mmc@1c0f000: 0 (SD) mmc@1c10000: 1 mmc@1c11000: 2
I'm testing this patches applied onto u-boot-sunxi/master on Pinebook. I tried 'distclean', and it doesn't help.
Looks like eMMC is here but it doesn't get renumbered:
=> mmc dev 2 switch to partitions #0, OK mmc2(part 0) is current device => mmc info Device: mmc@1c11000 Manufacturer ID: 15 OEM: 100 Name: AJTD4 Bus Speed: 52000000 Mode : MMC High Speed (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.6 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.6 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH => mmc list mmc@1c0f000: 0 mmc@1c10000: 1 mmc@1c11000: 2 (eMMC)
On Mon, Jan 21, 2019 at 11:38 PM Vasily Khoruzhick anarsoul@gmail.com wrote:
On Mon, Jan 21, 2019 at 2:32 AM Jagan Teki jagan@amarulasolutions.com wrote:
Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform.
If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device.
If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition.
So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.
It doesn't work on Pinebook - where we have mmc0 (SD card), mmc1 (SDIO), mmc2 (eMMC). It still enumerates mmc2 as mmc2.
Try doing a clean build (i.e., do make distclean beforehand)?
It worked for me once I did that.
ChenYu
Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include <config.h>
/ {
aliases {mmc1 = &mmc2;};binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;-- 2.18.0.321.gffc6fa0e3
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote:
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Also I had to do a clean build after applying the patches. It might be the config did not get updated properly or there's some missing dependency in the build system.
ChenYu
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote:
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Also I had to do a clean build after applying the patches. It might be the config did not get updated properly or there's some missing dependency in the build system.
How did you reproduce this?
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote:
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
That is what Andre and I are referring to.
Also I had to do a clean build after applying the patches. It might be the config did not get updated properly or there's some missing dependency in the build system.
How did you reproduce this?
Not sure. I suppose it might be that I had an existing build prior to applying the patches. Or it might be that I fat fingered something and didn't actually install the newly built image.
Either way I'll yell if I run into this again.
ChenYu
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote:
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
Yes, that same has been included with v3.1 patch which I linked above.
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote:
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
Yes, that same has been included with v3.1 patch which I linked above.
The gates/resets are added in that patch. No one is using them. The device tree node for the MMC controllers do _not_ reference this clock and reset, only the individual ones in the MMC config clock block.
Unless you are expecting BROM or SPL to have set that up for you, which IMO is quite fragile. You could very well boot from SPI or even FEL, and it wouldn't be correctly setup, in which case MMC would be completely broken.
FYI the clk-sun9i-mmc driver in Linux deasserts the reset at probe:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-m...
And enables the bus gate when it needs to toggle bits in its register space:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-m...
This is what is missing. Andre's patch doesn't have them. He specifically mentioned this.
Regards ChenYu
On Fri, 25 Jan 2019 19:01:12 +0800 Chen-Yu Tsai wens@csie.org wrote:
Hi,
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote:
Compared to previous version changes[1] this version do manage ahb clocks/resets via CLK framework.
This version created changes along with Andre patches to support clock/resets[2]
Tested A64, SD, eMMC and respective changes available at u-boot-sunxi/next
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do required SoC's
[1] https://patchwork.ozlabs.org/cover/1026828/ [2] https://patchwork.ozlabs.org/cover/1027850/
Andre Przywara (2): sunxi: clk: add MMC gates/resets sunxi: clk: A80: add MMC clock support
Jagan Teki (7): mmc: sunxi: Add A83T emmc compatible mmc: sunxi: Add mmc, emmc H5/A64 compatible mmc: sunxi: Add DM_MMC support for H6 mmc: sunxi: Add DM_MMC support for A80 dm: mmc: sunxi: Add CLK and RESET support arm: sunxi: Enable DM_MMC arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
Yes, that same has been included with v3.1 patch which I linked above.
The gates/resets are added in that patch. No one is using them. The device tree node for the MMC controllers do _not_ reference this clock and reset, only the individual ones in the MMC config clock block.
Unless you are expecting BROM or SPL to have set that up for you, which IMO is quite fragile. You could very well boot from SPI or even FEL, and it wouldn't be correctly setup, in which case MMC would be completely broken.
FYI the clk-sun9i-mmc driver in Linux deasserts the reset at probe:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L145And enables the bus gate when it needs to toggle bits in its register space:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L53This is what is missing. Andre's patch doesn't have them. He specifically mentioned this.
But this is addressed by this, isn't it? https://lists.denx.de/pipermail/u-boot/2019-January/355856.html (combined with Jagan's addition of the shared gates in v3.1)
Btw.: Somehow I managed to send it from the wrong branch (doesn't even compile), will send a fix later.
Jagan, we need this patch for A80, and also the pinmux setup patch (1/2 in this series) for it to work. That together with the H3 reset hiccup should be enough to justify a v4, I believe. Also I had some comments on your v3 (commit messages outdated, 7/9 too complicated), are you going to address them?
Meanwhile I prepared a branch to have everything we need: https://github.com/apritzel/u-boot/commits/sunxi-dm-gates Please ignore the top 4 commits for now (adding SPI flash support).
Cheers, Andre.
On Fri, Jan 25, 2019 at 5:07 PM Andre Przywara andre.przywara@arm.com wrote:
On Fri, 25 Jan 2019 19:01:12 +0800 Chen-Yu Tsai wens@csie.org wrote:
Hi,
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote: > > Compared to previous version changes[1] this version do > manage ahb clocks/resets via CLK framework. > > This version created changes along with Andre patches to > support clock/resets[2] > > Tested A64, SD, eMMC and respective changes available at > u-boot-sunxi/next > > Changes for v3: > - Handle clock via CLK framework. > Changes for v2: > - update the 'reset enablement' logic to do > required SoC's > > [1] https://patchwork.ozlabs.org/cover/1026828/ > [2] https://patchwork.ozlabs.org/cover/1027850/ > > Andre Przywara (2): > sunxi: clk: add MMC gates/resets > sunxi: clk: A80: add MMC clock support > > Jagan Teki (7): > mmc: sunxi: Add A83T emmc compatible > mmc: sunxi: Add mmc, emmc H5/A64 compatible > mmc: sunxi: Add DM_MMC support for H6 > mmc: sunxi: Add DM_MMC support for A80 > dm: mmc: sunxi: Add CLK and RESET support > arm: sunxi: Enable DM_MMC > arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
Yes, that same has been included with v3.1 patch which I linked above.
The gates/resets are added in that patch. No one is using them. The device tree node for the MMC controllers do _not_ reference this clock and reset, only the individual ones in the MMC config clock block.
Unless you are expecting BROM or SPL to have set that up for you, which IMO is quite fragile. You could very well boot from SPI or even FEL, and it wouldn't be correctly setup, in which case MMC would be completely broken.
FYI the clk-sun9i-mmc driver in Linux deasserts the reset at probe:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L145And enables the bus gate when it needs to toggle bits in its register space:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L53This is what is missing. Andre's patch doesn't have them. He specifically mentioned this.
But this is addressed by this, isn't it? https://lists.denx.de/pipermail/u-boot/2019-January/355856.html (combined with Jagan's addition of the shared gates in v3.1)
Btw.: Somehow I managed to send it from the wrong branch (doesn't even compile), will send a fix later.
Jagan, we need this patch for A80, and also the pinmux setup patch (1/2 in this series) for it to work. That together with the H3 reset hiccup should be enough to justify a v4, I believe. Also I had some comments on your v3 (commit messages outdated, 7/9 too complicated), are you going to address them?
Meanwhile I prepared a branch to have everything we need: https://github.com/apritzel/u-boot/commits/sunxi-dm-gates Please ignore the top 4 commits for now (adding SPI flash support).
Add on top of this branch[2], will send all together in next version for final version probably.
[2] https://github.com/amarula/u-boot-amarula/tree/sun-dm-mmc
On Fri, Jan 25, 2019 at 7:37 PM Andre Przywara andre.przywara@arm.com wrote:
On Fri, 25 Jan 2019 19:01:12 +0800 Chen-Yu Tsai wens@csie.org wrote:
Hi,
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote:
On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki jagan@amarulasolutions.com wrote: > > Compared to previous version changes[1] this version do > manage ahb clocks/resets via CLK framework. > > This version created changes along with Andre patches to > support clock/resets[2] > > Tested A64, SD, eMMC and respective changes available at > u-boot-sunxi/next > > Changes for v3: > - Handle clock via CLK framework. > Changes for v2: > - update the 'reset enablement' logic to do > required SoC's > > [1] https://patchwork.ozlabs.org/cover/1026828/ > [2] https://patchwork.ozlabs.org/cover/1027850/ > > Andre Przywara (2): > sunxi: clk: add MMC gates/resets > sunxi: clk: A80: add MMC clock support > > Jagan Teki (7): > mmc: sunxi: Add A83T emmc compatible > mmc: sunxi: Add mmc, emmc H5/A64 compatible > mmc: sunxi: Add DM_MMC support for H6 > mmc: sunxi: Add DM_MMC support for A80 > dm: mmc: sunxi: Add CLK and RESET support > arm: sunxi: Enable DM_MMC > arm: dts: sunxi: Enumerate MMC2 as MMC1
Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi M2M
However, the A80 MMC clock patch is still missing code to toggle the upstream bus clock gate and reset control in the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
Yes, that same has been included with v3.1 patch which I linked above.
The gates/resets are added in that patch. No one is using them. The device tree node for the MMC controllers do _not_ reference this clock and reset, only the individual ones in the MMC config clock block.
Unless you are expecting BROM or SPL to have set that up for you, which IMO is quite fragile. You could very well boot from SPI or even FEL, and it wouldn't be correctly setup, in which case MMC would be completely broken.
FYI the clk-sun9i-mmc driver in Linux deasserts the reset at probe:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L145And enables the bus gate when it needs to toggle bits in its register space:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L53This is what is missing. Andre's patch doesn't have them. He specifically mentioned this.
But this is addressed by this, isn't it? https://lists.denx.de/pipermail/u-boot/2019-January/355856.html (combined with Jagan's addition of the shared gates in v3.1)
Yes it does, however nowhere is it mentioned in the cover letter. That and I managed to purge it from my short term memory.
So with the two series combined it should work properly on the A80.
BTW, Jagan, vN.M patches are very hard to track...
ChenYu
Btw.: Somehow I managed to send it from the wrong branch (doesn't even compile), will send a fix later.
Jagan, we need this patch for A80, and also the pinmux setup patch (1/2 in this series) for it to work. That together with the H3 reset hiccup should be enough to justify a v4, I believe. Also I had some comments on your v3 (commit messages outdated, 7/9 too complicated), are you going to address them?
Meanwhile I prepared a branch to have everything we need: https://github.com/apritzel/u-boot/commits/sunxi-dm-gates Please ignore the top 4 commits for now (adding SPI flash support).
Cheers, Andre.
On Fri, 25 Jan 2019 19:42:22 +0800 Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 7:37 PM Andre Przywara andre.przywara@arm.com wrote:
On Fri, 25 Jan 2019 19:01:12 +0800 Chen-Yu Tsai wens@csie.org wrote:
Hi,
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wens@csie.org wrote:
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wens@csie.org wrote: > > On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki > jagan@amarulasolutions.com wrote: > > > > Compared to previous version changes[1] this version do > > manage ahb clocks/resets via CLK framework. > > > > This version created changes along with Andre patches to > > support clock/resets[2] > > > > Tested A64, SD, eMMC and respective changes available at > > u-boot-sunxi/next > > > > Changes for v3: > > - Handle clock via CLK framework. > > Changes for v2: > > - update the 'reset enablement' logic to do > > required SoC's > > > > [1] https://patchwork.ozlabs.org/cover/1026828/ > > [2] https://patchwork.ozlabs.org/cover/1027850/ > > > > Andre Przywara (2): > > sunxi: clk: add MMC gates/resets > > sunxi: clk: A80: add MMC clock support > > > > Jagan Teki (7): > > mmc: sunxi: Add A83T emmc compatible > > mmc: sunxi: Add mmc, emmc H5/A64 compatible > > mmc: sunxi: Add DM_MMC support for H6 > > mmc: sunxi: Add DM_MMC support for A80 > > dm: mmc: sunxi: Add CLK and RESET support > > arm: sunxi: Enable DM_MMC > > arm: dts: sunxi: Enumerate MMC2 as MMC1 > > Tested-by: Chen-Yu Tsai wens@csie.org # on the Bananapi > M2M > > However, the A80 MMC clock patch is still missing code to > toggle the upstream bus clock gate and reset control in > the CCU.
Sent it with original mmc clock and reset patch[1], let me know your comments.
Right. The problem is nowhere in this series are those enabled / deasserted. The A80 CCU only has one gate & reset for the whole MMC subsystem, including the MMC config clocks block. Ideally the driver for that block should enable the gate and deassert the reset control.
Yes, that same has been included with v3.1 patch which I linked above.
The gates/resets are added in that patch. No one is using them. The device tree node for the MMC controllers do _not_ reference this clock and reset, only the individual ones in the MMC config clock block.
Unless you are expecting BROM or SPL to have set that up for you, which IMO is quite fragile. You could very well boot from SPI or even FEL, and it wouldn't be correctly setup, in which case MMC would be completely broken.
FYI the clk-sun9i-mmc driver in Linux deasserts the reset at probe:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L145And enables the bus gate when it needs to toggle bits in its register space:
https://elixir.bootlin.com/linux/latest/source/drivers/clk/sunxi/clk-sun9i-mmc.c#L53This is what is missing. Andre's patch doesn't have them. He specifically mentioned this.
But this is addressed by this, isn't it? https://lists.denx.de/pipermail/u-boot/2019-January/355856.html (combined with Jagan's addition of the shared gates in v3.1)
Yes it does, however nowhere is it mentioned in the cover letter.
True, I realised this myself while searching for it in the archive ;-)
Will fix that in v2.
That and I managed to purge it from my short term memory.
So with the two series combined it should work properly on the A80.
Cool. We need some serious testing of this, once we have settled on something ;-) Fortunately we now have more than two months until the release.
Cheers, Andre.
BTW, Jagan, vN.M patches are very hard to track...
ChenYu
Btw.: Somehow I managed to send it from the wrong branch (doesn't even compile), will send a fix later.
Jagan, we need this patch for A80, and also the pinmux setup patch (1/2 in this series) for it to work. That together with the H3 reset hiccup should be enough to justify a v4, I believe. Also I had some comments on your v3 (commit messages outdated, 7/9 too complicated), are you going to address them?
Meanwhile I prepared a branch to have everything we need: https://github.com/apritzel/u-boot/commits/sunxi-dm-gates Please ignore the top 4 commits for now (adding SPI flash support).
Cheers, Andre.
participants (5)
-
Andre Przywara -
André Przywara
-
Chen-Yu Tsai -
Jagan Teki -
Vasily Khoruzhick