From: Shaohui Xie Shaohui.Xie@freescale.com

TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- drivers/net/phy/teranetics.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index 78447b7..84ce736 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -34,9 +34,21 @@ int tn2020_config(struct phy_device *phydev) unsigned short restart_an = (MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_XNP); + u8 phy_hwversion;

- phy_write(phydev, 30, 93, 2); - phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); + /* + * bit 15:12 of register 30.32 indicates PHY hardware + * version. It can be used to distinguish TN80xx from + * TN2020. TN2020 needs write 0x2 to 30.93, but TN80xx + * needs 0x1. + */ + phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; + if (phy_hwversion <= 3) { + phy_write(phydev, 30, 93, 2); + phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); + } else { + phy_write(phydev, 30, 93, 1); + } }

return 0;

Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example

vdd_override <voltage in mV, eg. 1050>

The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored.

In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot:

setenv t4240qds_vdd_mv <voltage in mV> saveenv

Signed-off-by: York Sun yorksun@freescale.com --- board/freescale/t4qds/t4qds.c | 39 +++++++++++++++++++++++++++++++++++++-- doc/README.t4240qds | 24 ++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index d521008..26539db 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -234,7 +234,7 @@ static inline int set_voltage(u8 vid) }

-static int adjust_vdd(void) +static int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); ccsr_gur_t __iomem *gur = @@ -243,6 +243,8 @@ static int adjust_vdd(void) u8 vid, vid_current; int vdd_target, vdd_current, vdd_last; int ret; + unsigned long vdd_string_override; + char *vdd_string; static const uint16_t vdd[32] = { 0, /* unused */ 9875, /* 0.9875V */ @@ -292,6 +294,19 @@ static int adjust_vdd(void) FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; } vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv("t4240qds_vdd_mv"); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= 819 && vdd_override <= 1212) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + if (vdd_target == 0) { debug("VID: VID not used\n"); ret = 0; @@ -511,7 +526,7 @@ int board_early_init_r(void) * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. */ - if (adjust_vdd()) + if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n");

/* Configure board SERDES ports crossbar */ @@ -801,3 +816,23 @@ void qixis_dump_switch(void) i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); } } + +static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong override; + + if (argc < 2) + return CMD_RET_USAGE; + if (!strict_strtoul(argv[1], 10, &override)) + adjust_vdd(override); /* the value is checked by callee */ + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + vdd_override, 2, 0, do_vdd_adjust, + "Override VDD", + "- override with the voltage specified in mV, eg. 1050" +); diff --git a/doc/README.t4240qds b/doc/README.t4240qds index 677d120..19e8a8a 100644 --- a/doc/README.t4240qds +++ b/doc/README.t4240qds @@ -96,3 +96,27 @@ The addresses in brackets are physical addresses. 0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores

The physical address of the last (boot page translation) varies with the actual DDR size. + +Voltage ID and VDD override +-------------------- +T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage +accordingly. The voltage can also be override by command vdd_override. The +syntax is + +vdd_override <voltage in mV>, eg. 1050 is for 1.050v. + +Upon success, the actual voltage will be read back. The value is checked +for safety and any invalid value will not adjust the voltage. + +Another way to override VDD is to use environmental variable, in case of using +command is too late for some debugging. The syntax is + +setenv t4240qds_vdd_mv <voltage in mV> +saveenv +reset + +The override voltage takes effect when booting. + +Note: voltage adjustment needs to be done step by step. Changing voltage too +rapidly may cause current surge. The voltage stepping is done by software. +Users can set the final voltage directly.

From: James Yang James.Yang@freescale.com

Add e6500 L2 replacement policy selection. This is compile-time config.

Signed-off-by: James Yang James.Yang@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 1 + arch/powerpc/include/asm/processor.h | 9 +++++++++ 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f697c3d..29346d9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -337,7 +337,7 @@ int enable_cluster_l2(void) while ((in_be32(&l2cache->l2csr0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) ; - out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE); + out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); } i++; } while (!(cluster & TP_CLUSTER_EOC)); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 87168e2..e413e4a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -735,6 +735,7 @@ enable_l2_cluster_l2: and. r1, r0, r4 bne 1b lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2REP_MODE)@l sync stw r4, 0(r3) /* enable L2 */ delete_ccsr_l2_tlb: diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 5c0c438..1760aa1 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -507,6 +507,15 @@ #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ + +/* e6500 */ +#define L2CSR0_L2REP_SPLRUAGE 0x00000000 /* L2REP Streaming PLRU with Aging */ +#define L2CSR0_L2REP_FIFO 0x00001000 /* L2REP FIFO */ +#define L2CSR0_L2REP_SPLRU 0x00002000 /* L2REP Streaming PLRU */ +#define L2CSR0_L2REP_PLRU 0x00003000 /* L2REP PLRU */ + +#define L2CSR0_L2REP_MODE L2CSR0_L2REP_SPLRUAGE + #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */

T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.

Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h | 44 +++++++---------------------- include/configs/t4qds.h | 1 - 2 files changed, 10 insertions(+), 35 deletions(-)

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7a1cdc7..d9b8db4 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -514,57 +514,33 @@ #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"

-#elif defined(CONFIG_PPC_T4240) +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SRDS_3 -#define CONFIG_SYS_FSL_SRDS_4 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_A004468 -#define CONFIG_SYS_FSL_ERRATUM_A_004934 -#define CONFIG_SYS_FSL_ERRATUM_A005871 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_PCI_VER_3_X - -#elif defined(CONFIG_PPC_T4160) -#define CONFIG_SYS_PPC64 /* 64-bit core */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ -#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#else #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 7 -#define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 943bf67..fa1dcc3 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -37,7 +37,6 @@

/* High Level Configuration Options */ #define CONFIG_BOOKE -#define CONFIG_E6500 #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */

To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc85xx/release.S | 41 +++++++++++----------- arch/powerpc/cpu/mpc85xx/speed.c | 20 +++++------ arch/powerpc/cpu/mpc8xxx/cpu.c | 53 ++++++++++++++++++++++++----- arch/powerpc/include/asm/config_mpc85xx.h | 10 ++++++ arch/powerpc/include/asm/immap_85xx.h | 24 +++++-------- arch/powerpc/include/asm/processor.h | 2 ++ 6 files changed, 92 insertions(+), 58 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 467ea10..a4a21b0 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -154,16 +154,12 @@ __secondary_start_page: ori r3,r3,toreset(__spin_table_addr)@l lwz r3,0(r3)

- /* - * r10 has the base address for the entry. - * we cannot access it yet before setting up a new TLB - */ mfspr r0,SPRN_PIR #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * PIR definition for Chassis 2 * 0-17 Reserved (logic 0s) - * 8-19 CHIP_ID, 2'b00 - SoC 1 + * 18-19 CHIP_ID, 2'b00 - SoC 1 * all others - reserved * 20-24 CLUSTER_ID 5'b00000 - CCM 1 * all others - reserved @@ -177,32 +173,33 @@ __secondary_start_page: * 2'b11 - core 3 * 29-31 THREAD_ID 3'b000 - thread 0 * 3'b001 - thread 1 + * + * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08 + * and clusters by 0x20. + * + * We renumber PIR so that all threads in the system are consecutive. */ - rlwinm r4,r0,29,25,31 + + rlwinm r8,r0,29,0x03 /* r8 = core within cluster */ + srwi r10,r0,5 /* r10 = cluster */ + + mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER + add r5,r5,r8 /* for spin table index */ + mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */ #elif defined(CONFIG_E500MC) rlwinm r4,r0,27,27,31 + mr r5,r4 #else mr r4,r0 + mr r5,r4 #endif - slwi r8,r4,6 /* spin table is padded to 64 byte */ - add r10,r3,r8

-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 - mfspr r0,SPRN_PIR /* - * core 0 thread 0: pir reset value 0x00, new pir 0 - * core 0 thread 1: pir reset value 0x01, new pir 1 - * core 1 thread 0: pir reset value 0x08, new pir 2 - * core 1 thread 1: pir reset value 0x09, new pir 3 - * core 2 thread 0: pir reset value 0x10, new pir 4 - * core 2 thread 1: pir reset value 0x11, new pir 5 - * etc. - * - * Only thread 0 of each core will be running, updating PIR doesn't - * need to deal with the thread bits. + * r10 has the base address for the entry. + * we cannot access it yet before setting up a new TLB */ - rlwinm r4,r0,30,24,30 -#endif + slwi r8,r5,6 /* spin table is padded to 64 byte */ + add r10,r3,r8

mtspr SPRN_PIR,r4 /* write to PIR register */

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f00b1ab..a4d6e9c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -112,23 +112,20 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * Each cluster has up to 4 cores, sharing the same PLL selection. - * The cluster assignment is fixed per SoC. There is no way identify the - * assignment so far, presuming the "first configuration" which is to - * fill the lower cluster group first before moving up to next group. - * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1 - * and core 4~7 on cluster 2 - * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3 - * and core 12~15 on cluster 4 if existing + * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are + * cluster group A, feeding cores on cluster 1 and cluster 2. + * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3 + * and cluster 4 if existing. */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27) + int cluster = fsl_qoriq_core_to_cluster(cpu); + u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; if (cplx_pll > 3) printf("Unsupported architecture configuration" " in function %s\n", __func__); - cplx_pll += (cpu / 8) * 3; - + cplx_pll += (cluster / 2) * 3; sysInfo->freqProcessor[cpu] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; } @@ -240,7 +237,8 @@ void get_sys_info (sys_info_t * sysInfo) #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; + u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel];

sysInfo->freqProcessor[cpu] = diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 23e008e..bc26855 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -103,35 +103,70 @@ static struct cpu_type cpu_type_list[] = { };

#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +static inline u32 init_type(u32 cluster, int init_id) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; + u32 type = in_be32(&gur->tp_ityp[idx]); + + if (type & TP_ITYP_AV) + return type; + + return 0; +} + u32 compute_ppc_cpumask(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int i = 0, count = 0; - u32 cluster, mask = 0; + u32 cluster, type, mask = 0;

do { int j; - cluster = in_be32(&gur->tp_cluster[i++].lower); - for (j = 0; j < 4; j++) { - u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; - u32 type = in_be32(&gur->tp_ityp[idx]); - - if (type & TP_ITYP_AV) { + cluster = in_be32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = init_type(cluster, j); + if (type) { if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) mask |= 1 << count; + count++; } - count++; } + i++; } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);

return mask; } + +int fsl_qoriq_core_to_cluster(unsigned int core) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster; + + do { + int j; + cluster = in_be32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + if (init_type(cluster, j)) { + if (count == core) + return i; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return -1; /* cannot identify the cluster */ +} + #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ /* * Before chassis genenration 2, the cpumask should be hard-coded. * In case of cpu type unknown or cpumask unset, use 1 as fail save. */ #define compute_ppc_cpumask() 1 +#define fsl_qoriq_core_to_cluster(x) x #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1f06835..c03b0af 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -519,6 +519,7 @@ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 @@ -562,6 +563,7 @@ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 @@ -584,6 +586,7 @@ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 @@ -610,6 +613,7 @@ #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 @@ -640,4 +644,10 @@ #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." #endif

+#ifdef CONFIG_E6500 +#define CONFIG_SYS_FSL_THREADS_PER_CORE 2 +#else +#define CONFIG_SYS_FSL_THREADS_PER_CORE 1 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 17f16cf..d1ea0f7 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1996,6 +1996,7 @@ typedef struct ccsr_gur {

#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4

#define FSL_CORENET_DCSR_SZ_MASK 0x00000003 #define FSL_CORENET_DCSR_SZ_4M 0x0 @@ -2008,22 +2009,13 @@ typedef struct ccsr_gur { #define rmuliodnr rio1maintliodnr

typedef struct ccsr_clk { - u32 clkc0csr; /* 0x000 Core 0 Clock control/status */ - u8 res1[0x1c]; - u32 clkc1csr; /* 0x020 Core 1 Clock control/status */ - u8 res2[0x1c]; - u32 clkc2csr; /* 0x040 Core 2 Clock control/status */ - u8 res3[0x1c]; - u32 clkc3csr; /* 0x060 Core 3 Clock control/status */ - u8 res4[0x1c]; - u32 clkc4csr; /* 0x080 Core 4 Clock control/status */ - u8 res5[0x1c]; - u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */ - u8 res6[0x1c]; - u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */ - u8 res7[0x1c]; - u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */ - u8 res8[0x71c]; + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x0c]; + u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ + u8 res_014[0x0c]; + } clkcsr[8]; + u8 res_100[0x700]; /* 0x100 */ u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */ u8 res10[0x1c]; u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 5799386..56b22d8 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1200,6 +1200,8 @@ struct cpu_type { struct cpu_type *identify_cpu(u32 ver); int fixup_cpu(void);

+int fsl_qoriq_core_to_cluster(unsigned int core); + #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \

From: Ed Swarthout Ed.Swarthout@freescale.com

QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency.

Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com Signed-off-by: York Sun yorksun@freescale.com --- board/freescale/common/qixis.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 8d914d5..2cf8738 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -78,7 +78,11 @@ struct qixis { u8 trig_stat; u8 res12[3]; u8 trig_ctr[4]; - u8 res13[48]; + u8 res13[16]; + u8 clk_freq[6]; /* Clock Measurement Registers */ + u8 res_c6[8]; + u8 clk_base[2]; /* Clock Frequency Base Reg */ + u8 res_d0[16]; u8 aux2[4]; /* Auxiliary Registers,0xE0 */ u8 res14[10]; u8 aux_ad;

From: Shaohui Xie Shaohui.Xie@freescale.com

Provided a default RCW for P5040, then it can use PBL to build ramboot image.

Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 +++++++++++ include/configs/corenet_ds.h | 2 ++ 2 files changed, 13 insertions(+) create mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg

diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg new file mode 100644 index 0000000..82fa741 --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P5040DS. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +0c580000 00000000 22121200 00000000 +089c4400 00283000 58000000 61000000 +00000000 00000000 00000000 10070000 +00000000 00000000 00000000 00000000 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5cc9b5a..2e2d439 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -38,6 +38,8 @@ #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg #elif defined(CONFIG_P5020DS) #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#elif defined(CONFIG_P5040DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif

From: Suresh Gupta suresh.gupta@freescale.com

- Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta suresh.gupta@freescale.com --- board/freescale/b4860qds/eth_b4860qds.c | 35 +++++++++++++++++++++++++++++++ drivers/net/fm/b4860.c | 6 ++++-- include/configs/B4860QDS.h | 6 +++++- 3 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 68e2725..3bcda6d 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -275,6 +275,24 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); break; + case 0x98: + /* XAUI in Slot1 and Slot2 */ + debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n", + CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, + CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + break; + case 0x9E: + /* XAUI in Slot2 */ + debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + break; default: printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); @@ -300,6 +318,23 @@ int board_eth_init(bd_t *bis) } }

+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + int idx = i - FM1_10GEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + break; + default: + printf("Fman1: 10GSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + cpu_eth_init(bis); #endif

diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 8cde7af..3b5defe 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -55,8 +55,10 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE;

- if ((port == FM1_10GEC1 || port == FM1_10GEC2) - && (is_serdes_configured(XAUI_FM1))) + /*B4860 has two 10Gig Mac*/ + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && + ((is_serdes_configured(XAUI_FM1_MAC9)) || + (is_serdes_configured(XAUI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII;

/* Fix me need to handle RGMII here first */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b09119a..cfab1e8 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -623,7 +623,11 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 + +/*B4860 QDS AMC2PEX-2S default PHY_ADDR */ +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ +#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ +

#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d

From: Shengzhou Liu Shengzhou.Liu@freescale.com

QSGMII card has different PHY address against previous SGMII card. We check the type of card in slots and set correct PHY address to avoid complainning "PHY reset timed out" during u-boot booting up.

Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- board/freescale/t4qds/eth.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index b649df0..7103a0d 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -365,24 +365,40 @@ static void initialize_qsgmiiphy_fix(void) qsgmiiphy_fix[FM1_DTSEC6] = 1; qsgmiiphy_fix[FM1_DTSEC9] = 1; qsgmiiphy_fix[FM1_DTSEC10] = 1; + slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR; break; case 2: qsgmiiphy_fix[FM1_DTSEC1] = 1; qsgmiiphy_fix[FM1_DTSEC2] = 1; qsgmiiphy_fix[FM1_DTSEC3] = 1; qsgmiiphy_fix[FM1_DTSEC4] = 1; + slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR; break; case 3: qsgmiiphy_fix[FM2_DTSEC5] = 1; qsgmiiphy_fix[FM2_DTSEC6] = 1; qsgmiiphy_fix[FM2_DTSEC9] = 1; qsgmiiphy_fix[FM2_DTSEC10] = 1; + slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR; break; case 4: qsgmiiphy_fix[FM2_DTSEC1] = 1; qsgmiiphy_fix[FM2_DTSEC2] = 1; qsgmiiphy_fix[FM2_DTSEC3] = 1; qsgmiiphy_fix[FM2_DTSEC4] = 1; + slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR; break; default: break; @@ -435,6 +451,7 @@ int board_eth_init(bd_t *bis) t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);

+ initialize_qsgmiiphy_fix();

switch (srds_prtcl_s1) { case 1: @@ -702,8 +719,6 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_SYS_NUM_FMAN */

- initialize_qsgmiiphy_fix(); - cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */

From: Shaveta Leekha shaveta@freescale.com

Crossbar switches were wrongly programmed to route the CPRI lanes to SFP as the connectivity table was not correct. Modified it correctly for SFPs connections.

Signed-off-by: Shaveta Leekha shaveta@freescale.com --- arch/powerpc/cpu/mpc85xx/fdt.c | 5 ++++ board/freescale/b4860qds/b4860qds.c | 6 +++-- board/freescale/b4860qds/b4860qds_crossbar_con.h | 31 +++++++++++++++------- 3 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c7ab146..c706b9b 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -665,6 +665,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,mpic", + "clock-frequency", get_bus_freq(0)/2, 1); +#else + do_fixup_by_compat_u32(blob, "fsl,mpic", + "clock-frequency", get_bus_freq(0), 1); #endif

fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 41887c2..a39c17a 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -166,11 +166,13 @@ int configure_vsc3316_3308(void) ret = select_i2c_ch_pca(I2C_CH_VSC3316); if (!ret) { ret = vsc3316_config(VSC3316_TX_ADDRESS, - vsc16_tx_sgmii_lane_ab, num_vsc16_con); + vsc16_tx_4sfp_sgmii_12_56, + num_vsc16_con); if (ret) return ret; ret = vsc3316_config(VSC3316_RX_ADDRESS, - vsc16_rx_sgmii_lane_ab, num_vsc16_con); + vsc16_rx_4sfp_sgmii_12_56, + num_vsc16_con); if (ret) return ret; } else { diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index 994dec5..c2b6c44 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -26,42 +26,53 @@ static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, {5, 11}, {4, 5}, {2, 6}, {12, 9} };

-static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1}, - {5, 15}, {4, 14}, {2, 12}, {12, 13} }; +static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };

-static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {2, 14}, {12, 15}, + {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {5, 14}, {4, 15}, + {-1, -1}, {-1, -1} };

#ifdef CONFIG_PPC_B4420 static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif + static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };

static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, {11, 11}, {5, 10}, {6, 3}, {9, 12} };

-static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9}, +static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };

-static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 3}, {15, 12}, + {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 11}, {15, 10}, + {-1, -1}, {-1, -1} };

#ifdef CONFIG_PPC_B4420 static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif

-static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1}, +static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };

static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };

-static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} }; +static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };

static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };

-static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} }; +static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };

#endif

From: Xie Xiaobo X.Xie@freescale.com

SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters.

Signed-off-by: Xie Xiaobo X.Xie@freescale.com --- drivers/mtd/spi/spansion.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 9288672..a2bfd86 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -94,7 +94,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .idcode2 = 0x4d01, .pages_per_sector = 256, .nr_sectors = 256, - .name = "S25FL129P_64K", + .name = "S25FL129P_64K/S25FL128S", }, { .idcode1 = 0x0219,

From: Shaohui Xie Shaohui.Xie@freescale.com

Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in eth port enum structure, it will assign mdio mux depend on this assumption. This is not true with Fman V3, which added more 1G ports after port DTSEC5 in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux. So we use dynamic index for 10G ports instead of hardcoded enum value when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- board/freescale/corenet_ds/eth_superhydra.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index ef9de25..ae07073 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -605,8 +605,8 @@ int board_eth_init(bd_t *bis) lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; + mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } @@ -704,8 +704,8 @@ int board_eth_init(bd_t *bis) lane = serdes_get_first_lane(XAUI_FM2); if (lane >= 0) { debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; + mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); }

From: Roy ZANG tie-fei.zang@freescale.com

Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY.

Signed-off-by: Roy Zang tie-fei.zang@freescale.com Reported-by: John Traill john.traill@freescale.com --- arch/powerpc/include/asm/fsl_memac.h | 4 ++++ drivers/net/fm/memac.c | 15 +++++++++++++++ 2 files changed, 19 insertions(+)

diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h index d6b60e6..69f95d1 100644 --- a/arch/powerpc/include/asm/fsl_memac.h +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -222,6 +222,10 @@ struct memac {

/* IF_MODE - Interface Mode Register */ #define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */ +#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */ +#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */ +#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */ +#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */ #define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */ #define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */ #define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */ diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 32c7054..fa14113 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -112,6 +112,21 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, /* Enable automatic speed selection */ if_mode |= IF_MODE_EN_AUTO;

+ if (type == PHY_INTERFACE_MODE_RGMII) { + if_mode &= ~IF_MODE_EN_AUTO; + if_mode &= ~IF_MODE_SETSP_MASK; + switch (speed) { + case SPEED_1000: + if_mode |= IF_MODE_SETSP_1000M; + case SPEED_100: + if_mode |= IF_MODE_SETSP_100M; + case SPEED_10: + if_mode |= IF_MODE_SETSP_10M; + default: + break; + } + } + debug(" %s, if_mode = %x\n", __func__, if_mode); debug(" %s, if_status = %x\n", __func__, if_status); out_be32(&regs->if_mode, if_mode);

From: Ruchika Gupta ruchika.gupta@freescale.com

Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required.

Signed-off-by: Ruchika Gupta ruchika.gupta@freescale.com Acked-by: Matthew McClintock msm@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 7 ------- arch/powerpc/include/asm/fsl_secure_boot.h | 10 ---------- 2 files changed, 17 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index dacfdd1..234fde4 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -180,12 +180,5 @@ void cpu_init_early_f(void)

invalidate_tlb(1);

-#if defined(CONFIG_SECURE_BOOT) - /* Disable the TLBs created by ISBC */ - for (i = CONFIG_SYS_ISBC_START_TLB; - i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++) - disable_tlb(i); -#endif - init_tlbs(); } diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index d1c1967..2bc6ed1 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -23,16 +23,6 @@ #ifndef __FSL_SECURE_BOOT_H #define __FSL_SECURE_BOOT_H

-/* Starting TLB number for the TLB entried for 3.5 G space created by ISBC */ -#if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_ISBC_START_TLB 3 -#else -#define CONFIG_SYS_ISBC_START_TLB 0 -#endif - -/* Number fo TLB's created by ISBC */ -#define CONFIG_SYS_ISBC_NUM_TLBS 5 - #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #else