From: David Brownell dbrownell@users.sourceforge.net

Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports:

Device 0: 2x nand0, sector size 128 KiB

Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...)

Signed-off-by: David Brownell dbrownell@users.sourceforge.net --- NOTE: probably depends on the two previous NAND patches (now queued in nand-next). I don't think this depends on anything in the arm-next tree, which doesn't have those patches.

board/davinci/sonata/sonata.c | 28 ++++++++++++++++++++++++++++ drivers/mtd/nand/davinci_nand.c | 28 ++++++++-------------------- include/asm-arm/arch-davinci/nand_defs.h | 2 ++ 3 files changed, 38 insertions(+), 20 deletions(-)

--- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -25,6 +25,8 @@ */

#include <common.h> +#include <nand.h> +#include <asm/arch/nand_defs.h> #include <asm/arch/hardware.h> #include "../common/misc.h"

@@ -75,3 +77,29 @@ int misc_init_r(void)

return(0); } + +#ifdef CONFIG_NAND_DAVINCI + +/* Set WP on deselect, write enable on select */ +static void nand_sonata_select_chip(struct mtd_info *mtd, int chip) +{ +#define GPIO_SET_DATA01 0x01c67018 +#define GPIO_CLR_DATA01 0x01c6701c +#define GPIO_NAND_WP (1 << 4) +#ifdef SONATA_BOARD_GPIOWP + if (chip < 0) { + REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; + } else { + REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; + } +#endif +} + +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + nand->select_chip = nand_sonata_select_chip; + return 0; +} + +#endif /* CONFIG_NAND_DAVINCI */ --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -47,8 +47,6 @@ #include <asm/arch/nand_defs.h> #include <asm/arch/emif_defs.h>

-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) @@ -70,21 +68,6 @@ static void nand_davinci_hwcontrol(struc writeb(cmd, this->IO_ADDR_W); }

-/* Set WP on deselect, write enable on select */ -static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) -{ -#define GPIO_SET_DATA01 0x01c67018 -#define GPIO_CLR_DATA01 0x01c6701c -#define GPIO_NAND_WP (1 << 4) -#ifdef SONATA_BOARD_GPIOWP - if (chip < 0) { - REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; - } else { - REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; - } -#endif -} - #ifdef CONFIG_SYS_NAND_HW_ECC

static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) @@ -234,10 +217,9 @@ static void nand_flash_init(void) #endif }

-int board_nand_init(struct nand_chip *nand) +void davinci_nand_init(struct nand_chip *nand) { nand->chip_delay = 0; - nand->select_chip = nand_davinci_select_chip; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->options = NAND_USE_FLASH_BBT; #endif @@ -258,6 +240,12 @@ int board_nand_init(struct nand_chip *na nand->dev_ready = nand_davinci_dev_ready;

nand_flash_init(); +}

- return(0); +int board_nand_init(struct nand_chip *chip) __attribute__((weak)); + +int board_nand_init(struct nand_chip *chip) +{ + davinci_nand_init(chip); + return 0; } --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -35,4 +35,6 @@ #define NAND_READ_END 0x30 #define NAND_STATUS 0x70

+extern void davinci_nand_init(struct nand_chip *nand); + #endif