[U-Boot] [PATCH v3 0/15] samsung: Use common config files with Samsung boards
This series tries to unify the Samsung board configs into a few header files for exynos5 and exynos4.
The purpose is to make it easier to move to driver model. In that case I would like things like the GPIO drivers and serial drivers to work in a standard way, and not need to support device tree and platform data at the same time. That would be quite painful.
Another reason is that the Chrome OS EC drivers are currently included in boards that don't have a Chrome OS EC. This concern was raised by the Samsung maintainer (Minkyu) a while back.
There are still a few boards that don't use CONFIG_OF_CONTROL so I have updated these with the most rudimentary of device tree files and updated them based on feedback.
This series has the side-effect of getting the EC interface working properly on Pit, so the keyboard works. It also provides access to the TPS65090 PMIC, which means that the backlight is enabled.
Changes in v3: - Adjust device tree file based on Robert Baldyga's example
Changes in v2: - Add new patch to enable keyboard on pit - Add new patch to split out cros_ec drivers - Add new patch to use 900MHz ARM frequeny in SPL for peach_pit - Avoid using a common file, and just add a device tree - Don't enable the cros_ec on smdk5420 - Fix 'cashe' typo in commit subject - Fix device tree base addresses - Leave CONFIG_SERIAL3 in the individual board files - Leave in a few configs which are not in fact common to all boards - Reduce the number of common elements to avoid needing #undefs later - Slightly reword the commit message
Simon Glass (15): Exynos: Use 900MHz ARM frequency in SPL for peach_pit exynos5: Enable data cache cros_ec: power: Add a tunnelled version of the tps65090 driver cros_ec: exynos: Use the correct tps65090 driver in each case dm: exynos: Split out the cros_ec drivers exynos: dts: Add device tree node for cros_ec keyboard exynos: Rename -dt config files to -common exynos: Move common exynos settings into a common file exynos: Move common smdk5420 things to common file exynos: config: Move cros_ec and tps65090 out of smdk boards config: Move arndale to use common exynos5250 file config: Move smdkv310 to use common exynos4 file samsung: Enable device tree for s5p_goni samsung: Enable device tree for smdkc100 exynos: Enable pre-relocation malloc()
arch/arm/dts/Makefile | 3 + arch/arm/dts/exynos4210-smdkv310.dts | 21 ++ arch/arm/dts/exynos5420-peach-pit.dts | 57 +++++- arch/arm/dts/s5pc1xx-goni.dts | 28 +++ arch/arm/dts/s5pc1xx-smdkc100.dts | 29 +++ arch/arm/include/asm/arch-s5pc1xx/periph.h | 61 ++++++ arch/arm/include/asm/arch-s5pc1xx/pinmux.h | 50 +++++ drivers/mmc/s5p_sdhci.c | 2 - drivers/power/pmic/Makefile | 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 212 +++++++++++++++++++++ include/configs/arndale.h | 197 +------------------ include/configs/{exynos4-dt.h => exynos-common.h} | 108 +++-------- include/configs/exynos4-common.h | 68 +++++++ include/configs/{exynos5-dt.h => exynos5-common.h} | 130 ++----------- include/configs/exynos5-dt-common.h | 35 ++++ .../{exynos5250-dt.h => exynos5250-common.h} | 7 +- .../configs/{exynos5420.h => exynos5420-common.h} | 22 ++- include/configs/odroid.h | 4 +- include/configs/origen.h | 5 +- include/configs/peach-pit.h | 17 +- include/configs/s5p_goni.h | 12 +- include/configs/s5pc210_universal.h | 5 +- include/configs/smdk5250.h | 23 ++- include/configs/smdk5420.h | 5 +- include/configs/smdkc100.h | 9 + include/configs/smdkv310.h | 64 ++----- include/configs/snow.h | 25 ++- include/configs/trats.h | 6 +- include/configs/trats2.h | 6 +- include/power/tps65090_pmic.h | 6 + 30 files changed, 732 insertions(+), 488 deletions(-) create mode 100644 arch/arm/dts/exynos4210-smdkv310.dts create mode 100644 arch/arm/dts/s5pc1xx-goni.dts create mode 100644 arch/arm/dts/s5pc1xx-smdkc100.dts create mode 100644 arch/arm/include/asm/arch-s5pc1xx/periph.h create mode 100644 arch/arm/include/asm/arch-s5pc1xx/pinmux.h create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c rename include/configs/{exynos4-dt.h => exynos-common.h} (52%) create mode 100644 include/configs/exynos4-common.h rename include/configs/{exynos5-dt.h => exynos5-common.h} (64%) create mode 100644 include/configs/exynos5-dt-common.h rename include/configs/{exynos5250-dt.h => exynos5250-common.h} (88%) rename include/configs/{exynos5420.h => exynos5420-common.h} (71%)
The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Add new patch to use 900MHz ARM frequeny in SPL for peach_pit
arch/arm/dts/exynos5420-peach-pit.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 3ed70a8..207782e 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -32,7 +32,7 @@ mem-manuf = "samsung"; mem-type = "ddr3"; clock-frequency = <800000000>; - arm-frequency = <1700000000>; + arm-frequency = <900000000>; };
tmu@10060000 {
Things run faster when the data cache is enabled, so turn it on along with the 'dcache' command.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Ajay Kumar ajaykumar.rs@samsung.com ---
Changes in v3: None Changes in v2: - Fix 'cashe' typo in commit subject
include/configs/exynos5-dt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index a7c6292..8ee5268 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -37,8 +37,8 @@ #define CONFIG_TRACE_EARLY_ADDR 0x50000000
/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE
/* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA
Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus.
When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Ajay Kumar ajaykumar.rs@samsung.com ---
Changes in v3: None Changes in v2: None
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++++++++++++ include/power/tps65090_pmic.h | 6 + 3 files changed, 219 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61..0b76611 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000..93b7923 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + */ + +#include <common.h> +#include <cros_ec.h> +#include <errno.h> +#include <power/tps65090_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_ADDR 0x48 + +static struct tps65090 { + struct cros_ec_dev *dev; /* The CROS_EC device */ +} config; + +/* TPS65090 register addresses */ +enum { + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * tps65090_read - read a byte from tps6090 + * + * @param reg The register address to read from. + * @param val We'll return value value read here. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_read(u32 reg, u8 *val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); +} + +/** + * tps65090_write - write a byte to tps6090 + * + * @param reg The register address to write to. + * @param val The value to write. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_write(u32 reg, u8 val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); +} + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -1 if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -1; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return FET_ERR_COMMS if we got a comms error, FET_ERR_NOT_READY if the + * FET failed to change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(int fet_id, int set) +{ + int retry; + u8 reg = 0, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) + return FET_ERR_COMMS; + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) + return FET_ERR_COMMS; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return FET_ERR_NOT_READY; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + int loops; + ulong start; + int ret = 0; + + if (tps65090_check_fet(fet_id)) + return -1; + + start = get_timer(0); + for (loops = 0; ; loops++) { + ret = tps65090_fet_set(fet_id, 1); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(fet_id, 0); + } + + if (ret) { + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } else if (loops) { + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == FET_ERR_NOT_READY) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + int ret; + + if (tps65090_check_fet(fet_id)) + return -1; + + ret = tps65090_fet_set(fet_id, 0); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + u8 reg = 0; + int ret; + + if (tps65090_check_fet(fet_id)) + return -1; + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -2; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_init(void) +{ + puts("TPS65090 PMIC EC init\n"); + + config.dev = board_get_cros_ec_dev(); + if (!config.dev) { + debug("%s: no cros_ec device: cannot init tps65090\n", + __func__); + return -1; + } + + return 0; +} diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h index dcf99c9..531751d 100644 --- a/include/power/tps65090_pmic.h +++ b/include/power/tps65090_pmic.h @@ -18,6 +18,12 @@ enum { TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, };
+/* FET errors */ +enum { + FET_ERR_COMMS = -1, /* FET comms error */ + FET_ERR_NOT_READY = -2, /* FET is not yet ready - retry */ +}; + /** * Enable FET *
Dear Simon Glass,
On 24 September 2014 03:59, Simon Glass sjg@chromium.org wrote:
Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus.
When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Ajay Kumar ajaykumar.rs@samsung.com
Changes in v3: None Changes in v2: None
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++++++++++++ include/power/tps65090_pmic.h | 6 + 3 files changed, 219 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61..0b76611 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000..93b7923 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,212 @@ +/*
- Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
- Use of this source code is governed by a BSD-style license that can be
- found in the LICENSE file.
- Alternatively, this software may be distributed under the terms of the
- GNU General Public License ("GPL") version 2 as published by the Free
- Software Foundation.
- */
+#include <common.h> +#include <cros_ec.h> +#include <errno.h> +#include <power/tps65090_pmic.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define TPS65090_ADDR 0x48
+static struct tps65090 {
struct cros_ec_dev *dev; /* The CROS_EC device */+} config;
+/* TPS65090 register addresses */ +enum {
REG_FET1_CTRL = 0x0f,REG_FET2_CTRL,REG_FET3_CTRL,REG_FET4_CTRL,REG_FET5_CTRL,REG_FET6_CTRL,REG_FET7_CTRL,TPS65090_NUM_REGS,+};
+enum {
MAX_FET_NUM = 7,MAX_CTRL_READ_TRIES = 5,/* TPS65090 FET_CTRL register values */FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge*/
FET_CTRL_ENFET = 1 << 0, /* Enable FET */+};
+/**
- tps65090_read - read a byte from tps6090
- @param reg The register address to read from.
- @param val We'll return value value read here.
- @return 0 if ok; error if EC returns failure.
- */
+static int tps65090_read(u32 reg, u8 *val) +{
return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,val, 1, true);+}
+/**
- tps65090_write - write a byte to tps6090
- @param reg The register address to write to.
- @param val The value to write.
- @return 0 if ok; error if EC returns failure.
- */
+static int tps65090_write(u32 reg, u8 val) +{
return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,&val, 1, false);+}
+/**
- Checks for a valid FET number
- @param fet_id FET number to check
- @return 0 if ok, -1 if FET value is out of range
- */
+static int tps65090_check_fet(unsigned int fet_id) +{
if (fet_id == 0 || fet_id > MAX_FET_NUM) {debug("parameter fet_id is out of range, %u not in 1 ~%u\n",
fet_id, MAX_FET_NUM);return -1;}return 0;+}
+/**
- Set the power state for a FET
- @param fet_id Fet number to set (1..MAX_FET_NUM)
- @param set 1 to power on FET, 0 to power off
- @return FET_ERR_COMMS if we got a comms error, FET_ERR_NOT_READY if the
- FET failed to change state. If all is ok, returns 0.
- */
+static int tps65090_fet_set(int fet_id, int set) +{
int retry;u8 reg = 0, value;value = FET_CTRL_ADENFET | FET_CTRL_WAIT;if (set)value |= FET_CTRL_ENFET;if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value))return FET_ERR_COMMS;/* Try reading until we get a result */for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®))return FET_ERR_COMMS;/* Check that the fet went into the expected state */if (!!(reg & FET_CTRL_PGFET) == set)return 0;/* If we got a timeout, there is no point in waitinglonger */
if (reg & FET_CTRL_TOFET)break;mdelay(1);}debug("FET %d: Power good should have set to %d but reg=%#02x\n",fet_id, set, reg);return FET_ERR_NOT_READY;+}
+int tps65090_fet_enable(unsigned int fet_id) +{
int loops;ulong start;int ret = 0;if (tps65090_check_fet(fet_id))return -1;start = get_timer(0);for (loops = 0; ; loops++) {ret = tps65090_fet_set(fet_id, 1);if (!ret)break;if (get_timer(start) > 100)break;/* Turn it off and try again until we time out */tps65090_fet_set(fet_id, 0);}if (ret) {debug("%s: FET%d failed to power on: time=%lums,loops=%d\n",
__func__, fet_id, get_timer(start), loops);} else if (loops) {debug("%s: FET%d powered on after %lums, loops=%d\n",__func__, fet_id, get_timer(start), loops);}/** Unfortunately, there are some conditions where the power* good bit will be 0, but the fet still comes up. One such* case occurs with the lcd backlight. We'll just return 0 here* and assume that the fet will eventually come up.*/if (ret == FET_ERR_NOT_READY)ret = 0;return ret;+}
+int tps65090_fet_disable(unsigned int fet_id) +{
int ret;if (tps65090_check_fet(fet_id))return -1;
+
ret = tps65090_fet_set(fet_id, 0);return ret;+}
+int tps65090_fet_is_enabled(unsigned int fet_id) +{
u8 reg = 0;int ret;if (tps65090_check_fet(fet_id))return -1;
FET_ERR_COMMS?
ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®);if (ret) {debug("fail to read FET%u_CTRL register over I2C", fet_id);return -2;
FET_ERR_NOT_READY?
}return reg & FET_CTRL_ENFET;+}
+int tps65090_init(void) +{
puts("TPS65090 PMIC EC init\n");config.dev = board_get_cros_ec_dev();if (!config.dev) {debug("%s: no cros_ec device: cannot init tps65090\n",__func__);return -1;}return 0;+} diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h index dcf99c9..531751d 100644 --- a/include/power/tps65090_pmic.h +++ b/include/power/tps65090_pmic.h @@ -18,6 +18,12 @@ enum { TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, };
+/* FET errors */ +enum {
FET_ERR_COMMS = -1, /* FET comms error */FET_ERR_NOT_READY = -2, /* FET is not yet ready - retry */+};
/**
- Enable FET
-- 2.1.0.rc2.206.gedb03e5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Thanks, Minkyu Kang.
Hi Minkyu,
On 28 September 2014 05:58, Minkyu Kang promsoft@gmail.com wrote:
Dear Simon Glass,
On 24 September 2014 03:59, Simon Glass sjg@chromium.org wrote:
Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus.
When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Ajay Kumar ajaykumar.rs@samsung.com
Changes in v3: None Changes in v2: None
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++++++++++++ include/power/tps65090_pmic.h | 6 + 3 files changed, 219 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61..0b76611 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000..93b7923 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,212 @@ +/*
- Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
- Use of this source code is governed by a BSD-style license that can be
- found in the LICENSE file.
- Alternatively, this software may be distributed under the terms of the
- GNU General Public License ("GPL") version 2 as published by the Free
- Software Foundation.
- */
+#include <common.h> +#include <cros_ec.h> +#include <errno.h> +#include <power/tps65090_pmic.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define TPS65090_ADDR 0x48
+static struct tps65090 {
struct cros_ec_dev *dev; /* The CROS_EC device */+} config;
+/* TPS65090 register addresses */ +enum {
REG_FET1_CTRL = 0x0f,REG_FET2_CTRL,REG_FET3_CTRL,REG_FET4_CTRL,REG_FET5_CTRL,REG_FET6_CTRL,REG_FET7_CTRL,TPS65090_NUM_REGS,+};
+enum {
MAX_FET_NUM = 7,MAX_CTRL_READ_TRIES = 5,/* TPS65090 FET_CTRL register values */FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload*/
FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge*/
FET_CTRL_ENFET = 1 << 0, /* Enable FET */+};
+/**
- tps65090_read - read a byte from tps6090
- @param reg The register address to read from.
- @param val We'll return value value read here.
- @return 0 if ok; error if EC returns failure.
- */
+static int tps65090_read(u32 reg, u8 *val) +{
return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,val, 1, true);+}
+/**
- tps65090_write - write a byte to tps6090
- @param reg The register address to write to.
- @param val The value to write.
- @return 0 if ok; error if EC returns failure.
- */
+static int tps65090_write(u32 reg, u8 val) +{
return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,&val, 1, false);+}
+/**
- Checks for a valid FET number
- @param fet_id FET number to check
- @return 0 if ok, -1 if FET value is out of range
- */
+static int tps65090_check_fet(unsigned int fet_id) +{
if (fet_id == 0 || fet_id > MAX_FET_NUM) {debug("parameter fet_id is out of range, %u not in 1 ~%u\n",
fet_id, MAX_FET_NUM);return -1;}return 0;+}
+/**
- Set the power state for a FET
- @param fet_id Fet number to set (1..MAX_FET_NUM)
- @param set 1 to power on FET, 0 to power off
- @return FET_ERR_COMMS if we got a comms error, FET_ERR_NOT_READY if
the
- FET failed to change state. If all is ok, returns 0.
- */
+static int tps65090_fet_set(int fet_id, int set) +{
int retry;u8 reg = 0, value;value = FET_CTRL_ADENFET | FET_CTRL_WAIT;if (set)value |= FET_CTRL_ENFET;if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value))return FET_ERR_COMMS;/* Try reading until we get a result */for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®))return FET_ERR_COMMS;/* Check that the fet went into the expected state */if (!!(reg & FET_CTRL_PGFET) == set)return 0;/* If we got a timeout, there is no point in waitinglonger */
if (reg & FET_CTRL_TOFET)break;mdelay(1);}debug("FET %d: Power good should have set to %d but reg=%#02x\n",fet_id, set, reg);return FET_ERR_NOT_READY;+}
+int tps65090_fet_enable(unsigned int fet_id) +{
int loops;ulong start;int ret = 0;if (tps65090_check_fet(fet_id))return -1;start = get_timer(0);for (loops = 0; ; loops++) {ret = tps65090_fet_set(fet_id, 1);if (!ret)break;if (get_timer(start) > 100)break;/* Turn it off and try again until we time out */tps65090_fet_set(fet_id, 0);}if (ret) {debug("%s: FET%d failed to power on: time=%lums,loops=%d\n",
__func__, fet_id, get_timer(start), loops);} else if (loops) {debug("%s: FET%d powered on after %lums, loops=%d\n",__func__, fet_id, get_timer(start), loops);}/** Unfortunately, there are some conditions where the power* good bit will be 0, but the fet still comes up. One such* case occurs with the lcd backlight. We'll just return 0 here* and assume that the fet will eventually come up.*/if (ret == FET_ERR_NOT_READY)ret = 0;return ret;+}
+int tps65090_fet_disable(unsigned int fet_id) +{
int ret;if (tps65090_check_fet(fet_id))return -1;ret = tps65090_fet_set(fet_id, 0);return ret;+}
+int tps65090_fet_is_enabled(unsigned int fet_id) +{
u8 reg = 0;int ret;if (tps65090_check_fet(fet_id))return -1;FET_ERR_COMMS?
ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®);if (ret) {debug("fail to read FET%u_CTRL register over I2C",fet_id);
return -2;FET_ERR_NOT_READY?
Actually I've moved to using standard errors for these. I'll fix it up, deal with the required Kconfig changes in mainline, and repost v4. Hoping this can be applied soon as so much depends on it it, and the Kconfig stuff is in flux.
Regards, Simon
Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards cannot due to a hardware design decision. Select the correct driver to use in each case.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Ajay Kumar ajaykumar.rs@samsung.com ---
Changes in v3: None Changes in v2: - Don't enable the cros_ec on smdk5420 - Slightly reword the commit message
drivers/power/pmic/Makefile | 2 +- include/configs/exynos5250-dt.h | 1 + include/configs/peach-pit.h | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 0b76611..e7b07eb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index c24984b..5504515 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -42,6 +42,7 @@
/* PMIC */ #define CONFIG_POWER_MAX77686 +#define CONFIG_POWER_TPS65090_I2C
/* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 88c093f..0892bd0 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -32,4 +32,6 @@ #define LCD_BPP LCD_COLOR16 #endif
+#define CONFIG_POWER_TPS65090_EC + #endif /* __CONFIG_PEACH_PIT_H */
With the driver model conversion we are going to be using driver model for SPI and not for I2C. This works OK so long as a board doesn't need both dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow uses I2C we need to split the configs so that only one driver is compiled for each platform.
We can fix this later when driver model supports I2C.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Add new patch to split out cros_ec drivers - Don't enable the cros_ec on smdk5420
include/configs/exynos5-dt.h | 2 -- include/configs/exynos5250-dt.h | 2 ++ include/configs/peach-pit.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 8ee5268..89de989 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -73,8 +73,6 @@
/* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ #define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 5504515..05d33a7 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -22,6 +22,8 @@
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
+#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ + /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 0892bd0..d93bf46 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -33,5 +33,6 @@ #endif
#define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
#endif /* __CONFIG_PEACH_PIT_H */
Add a keyboard definition so that the keyboard can be used on pit.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Add new patch to enable keyboard on pit
arch/arm/dts/exynos5420-peach-pit.dts | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 207782e..995e62b 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -28,6 +28,61 @@ pmic = "/i2c@12ca0000"; };
+ cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + google,key-rows = <8>; + google,key-columns = <13>; + google,repeat-delay-ms = <240>; + google,repeat-rate-ms = <30>; + google,ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; + }; + dmc { mem-manuf = "samsung"; mem-type = "ddr3";
We want exynos5250-dt.h to be a board which can support any exynos5250 device. This matches the naming used by Linux. As a first step, rename the existing -dt files to -common to make it clear they are common files, and not specific boards.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: None
include/configs/{exynos4-dt.h => exynos4-common.h} | 6 +++--- include/configs/{exynos5-dt.h => exynos5-common.h} | 6 +++--- include/configs/{exynos5250-dt.h => exynos5250-common.h} | 2 +- include/configs/odroid.h | 2 +- include/configs/origen.h | 2 +- include/configs/peach-pit.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/smdk5250.h | 2 +- include/configs/smdk5420.h | 2 +- include/configs/snow.h | 2 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- 12 files changed, 16 insertions(+), 16 deletions(-) rename include/configs/{exynos4-dt.h => exynos4-common.h} (97%) rename include/configs/{exynos5-dt.h => exynos5-common.h} (98%) rename include/configs/{exynos5250-dt.h => exynos5250-common.h} (97%)
diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-common.h similarity index 97% rename from include/configs/exynos4-dt.h rename to include/configs/exynos4-common.h index 7dac1a3..ef0df9c 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-common.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_EXYNOS4_COMMON_H +#define __CONFIG_EXYNOS4_COMMON_H
/* High Level Configuration Options */ #define CONFIG_SAMSUNG /* in a SAMSUNG core */ @@ -140,4 +140,4 @@ /* Enable devicetree support */ #define CONFIG_OF_LIBFDT
-#endif /* __CONFIG_H */ +#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-common.h similarity index 98% rename from include/configs/exynos5-dt.h rename to include/configs/exynos5-common.h index 89de989..91c0f00 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-common.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_EXYNOS5_COMMON_H +#define __CONFIG_EXYNOS5_COMMON_H
/* High Level Configuration Options */ #define CONFIG_SAMSUNG /* in a SAMSUNG core */ @@ -293,4 +293,4 @@ #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
-#endif /* __CONFIG_H */ +#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-common.h similarity index 97% rename from include/configs/exynos5250-dt.h rename to include/configs/exynos5250-common.h index 05d33a7..b4c1ccf 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-common.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H
-#include <configs/exynos5-dt.h> +#include <configs/exynos5-common.h> #define CONFIG_EXYNOS5250
#define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 29dcc4a..3309469 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -12,7 +12,7 @@ #ifndef __CONFIG_ODROID_U3_H #define __CONFIG_ODROID_U3_H
-#include <configs/exynos4-dt.h> +#include <configs/exynos4-common.h>
#define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */
diff --git a/include/configs/origen.h b/include/configs/origen.h index 5d24916..469183e 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_ORIGEN_H #define __CONFIG_ORIGEN_H
-#include <configs/exynos4-dt.h> +#include <configs/exynos4-common.h>
#define CONFIG_SYS_PROMPT "ORIGEN # "
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index d93bf46..a652ec1 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H
-#include <configs/exynos5-dt.h> +#include <configs/exynos5-common.h>
#include <configs/exynos5420.h>
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 20985da..066fc02 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_UNIVERSAL_H #define __CONFIG_UNIVERSAL_H
-#include <configs/exynos4-dt.h> +#include <configs/exynos4-common.h>
#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 66fa179..751b5eb 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H
-#include <configs/exynos5250-dt.h> +#include <configs/exynos5250-common.h>
#undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250 diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 606739b..43c9808 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H
-#include <configs/exynos5-dt.h> +#include <configs/exynos5-common.h>
#include <configs/exynos5420.h>
diff --git a/include/configs/snow.h b/include/configs/snow.h index 673fa14..78adca8 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H
-#include <configs/exynos5250-dt.h> +#include <configs/exynos5250-common.h>
#undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow diff --git a/include/configs/trats.h b/include/configs/trats.h index 6fa646b..ec9cf6f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_TRATS_H #define __CONFIG_TRATS_H
-#include <configs/exynos4-dt.h> +#include <configs/exynos4-common.h>
#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 1450865..b3ad718 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_TRATS2_H #define __CONFIG_TRATS2_H
-#include <configs/exynos4-dt.h> +#include <configs/exynos4-common.h>
#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
Since exynos4 and exyno5 share many settings, we should move these into a common file to avoid duplication.
In effect the changes are that all exynos boards now have EXT4 and FAT write support. This affects exynos5250 and exynos5420 which previously did not. This also disables the ext2 commands which are equivalent to ext4 anyway.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Reduce the number of common elements to avoid needing #undefs later
include/configs/exynos-common.h | 93 +++++++++++++++++++++++++++++++++++++ include/configs/exynos4-common.h | 81 +------------------------------- include/configs/exynos5-common.h | 90 +++++------------------------------ include/configs/origen.h | 3 -- include/configs/s5pc210_universal.h | 3 -- include/configs/smdk5250.h | 4 -- include/configs/snow.h | 4 -- include/configs/trats.h | 4 -- include/configs/trats2.h | 4 -- 9 files changed, 107 insertions(+), 179 deletions(-) create mode 100644 include/configs/exynos-common.h
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h new file mode 100644 index 0000000..0308b88 --- /dev/null +++ b/include/configs/exynos-common.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Common configuration settings for the SAMSUNG EXYNOS boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EXYNOS_COMMON_H +#define __EXYNOS_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <linux/sizes.h> + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* Enable fdt support */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_OF_LIBFDT + +/* Keep L2 Cache Disabled */ +#define CONFIG_CMD_CACHE + +/* input clock of PLL: 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ENV_OVERWRITE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* PWM */ +#define CONFIG_PWM + +/* Command definition*/ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index ef0df9c..972add4 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -9,85 +9,29 @@ #ifndef __CONFIG_EXYNOS4_COMMON_H #define __CONFIG_EXYNOS4_COMMON_H
-/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ +#define CONFIG_EXYNOS4 /* Exynos4 Family */
-#include <asm/arch/cpu.h> /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_SYS_GENERIC_BOARD - -/* Enable fdt support */ -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE +#include "exynos-common.h"
#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#include <linux/sizes.h>
/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI #define CONFIG_MMC_SDMA -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0
-/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include <config_cmd_default.h> - #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MISC #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS #undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE #undef CONFIG_CMD_ONENAND #undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC #define CONFIG_CMD_DFU #define CONFIG_CMD_GPT #define CONFIG_CMD_PMIC #define CONFIG_CMD_SETEXPR
-#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - /* USB Composite download gadget - g_dnl */ #define CONFIG_USBDOWNLOAD_GADGET
@@ -109,26 +53,8 @@ #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #define CONFIG_G_DNL_MANUFACTURER "Samsung"
-/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED @@ -137,7 +63,4 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE
-/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 91c0f00..380a46f 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -9,25 +9,14 @@ #ifndef __CONFIG_EXYNOS5_COMMON_H #define __CONFIG_EXYNOS5_COMMON_H
-/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON +#define CONFIG_EXYNOS5 /* Exynos5 Family */ + +#include "exynos-common.h" + +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_EXYNOS_SPL
-/* Enable fdt support for Exynos5250 */ -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* Allow tracing to be enabled */ #define CONFIG_TRACE #define CONFIG_CMD_TRACE @@ -36,22 +25,11 @@ #define CONFIG_TRACE_EARLY #define CONFIG_TRACE_EARLY_ADDR 0x50000000
-/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE
/* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA #define CONFIG_SHA_HW_ACCEL
-/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -63,13 +41,12 @@ #define INFORM2_OFFSET 0x808 #define INFORM3_OFFSET 0x80c
-/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - /* select serial console configuration */ #define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 #define CONFIG_SILENT_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX
/* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ @@ -78,8 +55,6 @@ #define CONFIG_KEYBOARD
/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define EXYNOS_DEVICE_SETTINGS \ "stdin=serial,cros-ec-keyb\0" \ "stdout=serial,lcd\0" \ @@ -88,39 +63,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS
-/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include <config_cmd_default.h> - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_NET #define CONFIG_CMD_HASH
-#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - /* Thermal Management Unit */ #define CONFIG_EXYNOS_TMU #define CONFIG_CMD_DTT @@ -135,6 +82,7 @@
/* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 +#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT @@ -143,14 +91,8 @@ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) @@ -177,10 +119,6 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SECURE_BL1_ONLY @@ -213,11 +151,6 @@ #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - /* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C @@ -271,9 +204,6 @@ #define CONFIG_MENU #endif
-/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -293,4 +223,8 @@ #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
+/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index 469183e..e24d5b6 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -37,9 +37,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
-/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 066fc02..cd4cdfe 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -29,9 +29,6 @@
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 751b5eb..37dc092 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -14,8 +14,4 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250
-/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 78adca8..58b011d 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -14,8 +14,4 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow
-/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index ec9cf6f..80ab96c 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -41,10 +41,6 @@
#define CONFIG_SYS_TEXT_BASE 0x63300000
-#include <linux/sizes.h> -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/trats2.h b/include/configs/trats2.h index b3ad718..998dabf 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -38,10 +38,6 @@
#define CONFIG_SYS_TEXT_BASE 0x43e00000
-#include <linux/sizes.h> -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200
A few things are common but are not in the common file. Fix this and rename the file to fit with the other exynos*-common files.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Leave CONFIG_SERIAL3 in the individual board files - Reduce the number of common elements to avoid needing #undefs later
include/configs/{exynos5420.h => exynos5420-common.h} | 8 +++----- include/configs/peach-pit.h | 4 +--- include/configs/smdk5420.h | 4 +--- 3 files changed, 5 insertions(+), 11 deletions(-) rename include/configs/{exynos5420.h => exynos5420-common.h} (88%)
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420-common.h similarity index 88% rename from include/configs/exynos5420.h rename to include/configs/exynos5420-common.h index d2a9556..27e7edc 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420-common.h @@ -9,7 +9,9 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H
-#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ +#define CONFIG_EXYNOS5420 + +#include <configs/exynos5-common.h>
#define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 @@ -31,10 +33,6 @@
#define CONFIG_MAX_I2C_NUM 11
-/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #define CONFIG_BOARD_REV_GPIO_COUNT 2
#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index a652ec1..455c03a 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,9 +9,7 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H
-#include <configs/exynos5-common.h> - -#include <configs/exynos5420.h> +#include <configs/exynos5420-common.h>
#undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5420-peach-pit diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 43c9808..2eaff21 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,9 +9,7 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H
-#include <configs/exynos5-common.h> - -#include <configs/exynos5420.h> +#include <configs/exynos5420-common.h>
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so move the settings into a separate common file to be used by those that need it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: None
include/configs/exynos5-common.h | 18 +++--------------- include/configs/exynos5-dt-common.h | 35 +++++++++++++++++++++++++++++++++++ include/configs/exynos5250-common.h | 3 --- include/configs/peach-pit.h | 1 + include/configs/snow.h | 4 ++++ 5 files changed, 43 insertions(+), 18 deletions(-) create mode 100644 include/configs/exynos5-dt-common.h
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 380a46f..3581a38 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -48,17 +48,10 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CONSOLE_MUX
-/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ #define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0"
#define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS @@ -185,11 +178,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 50000000 #endif
-/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h new file mode 100644 index 0000000..66547fa --- /dev/null +++ b/include/configs/exynos5-dt-common.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * Configuration settings for generic Exynos 5 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H +#define __CONFIG_EXYNOS5_DT_COMMON_H + +#include "exynos5-common.h" + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +#endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index b4c1ccf..987eb15 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -22,8 +22,6 @@
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
-#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ - /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI @@ -44,7 +42,6 @@
/* PMIC */ #define CONFIG_POWER_MAX77686 -#define CONFIG_POWER_TPS65090_I2C
/* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 455c03a..6cf8c74 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -10,6 +10,7 @@ #define __CONFIG_PEACH_PIT_H
#include <configs/exynos5420-common.h> +#include <configs/exynos5-dt-common.h>
#undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5420-peach-pit diff --git a/include/configs/snow.h b/include/configs/snow.h index 58b011d..93a03b1 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -10,8 +10,12 @@ #define __CONFIG_SNOW_H
#include <configs/exynos5250-common.h> +#include <configs/exynos5-dt-common.h>
#undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow
+#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_POWER_TPS65090_I2C + #endif /* __CONFIG_SNOW_H */
Most of the arndale features are common with other exynos5250 boards. To permit easier addition of driver model support, use the common file.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Reduce the number of common elements to avoid needing #undefs later
include/configs/arndale.h | 197 +----------------------------------- include/configs/exynos-common.h | 1 - include/configs/exynos4-common.h | 2 + include/configs/exynos5-common.h | 12 --- include/configs/exynos5250-common.h | 5 - include/configs/exynos5420-common.h | 14 +++ include/configs/peach-pit.h | 11 ++ include/configs/smdk5250.h | 19 ++++ include/configs/smdk5420.h | 3 + include/configs/snow.h | 17 ++++ 10 files changed, 67 insertions(+), 214 deletions(-)
diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 75f9933..d1a26f1 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -9,111 +9,19 @@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H
-/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ -#define CONFIG_EXYNOS5250 - -#include <asm/arch/cpu.h> /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS +#include "exynos5250-common.h"
/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC #define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-/* Command definition*/ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC #define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK
/* USB */ -#define CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS -#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER @@ -121,106 +29,23 @@
/* MMC SPL */ #define CONFIG_EXYNOS_SPL -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -#define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "ARNDALE # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL
#define CONFIG_NR_DRAM_BANKS 8 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
-#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ARNDALE"
-#define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
-/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - - #define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
-/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C @@ -230,26 +55,6 @@
#define CONFIG_PREBOOT
-/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 0308b88..1e0ceab 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -20,7 +20,6 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 972add4..89ba14e 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -13,6 +13,8 @@
#include "exynos-common.h"
+#define CONFIG_BOARD_COMMON + #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_REVISION_TAG
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 3581a38..ba591e7 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -14,7 +14,6 @@ #include "exynos-common.h"
#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_EXYNOS_SPL
/* Allow tracing to be enabled */ @@ -83,8 +82,6 @@ /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
-/* Miscellaneous configurable options */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -132,15 +129,10 @@ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-/* Store environment at the end of a 4 MB SPI flash */ -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) - /* U-boot copy size from boot Media to DRAM.*/ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
-#define CONFIG_SPI_BOOTING #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
@@ -155,10 +147,6 @@ #define CONFIG_I2C_EDID
/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI #define CONFIG_CMD_SF diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 987eb15..713614f 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -24,8 +24,6 @@
/* USB */ #define CONFIG_CMD_USB -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE
@@ -33,9 +31,6 @@
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
-#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_IDENT_STRING " for SMDK5250" - #define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 27e7edc..b0f940c 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -11,8 +11,17 @@
#define CONFIG_EXYNOS5420
+#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include <configs/exynos5-common.h>
+#define CONFIG_ARCH_EARLY_INIT_R + #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
@@ -37,6 +46,8 @@
#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + /* * Put the initial stack pointer 1KB below this to allow room for the * SPL marker. This value is arbitrary, but gd_t is placed starting here. @@ -47,4 +58,7 @@ #define CONFIG_NR_DRAM_BANKS 7 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 6cf8c74..0bf9e53 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,9 +9,17 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H
+#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + #include <configs/exynos5420-common.h> #include <configs/exynos5-dt-common.h>
+#define CONFIG_BOARD_COMMON + #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5420-peach-pit
@@ -34,4 +42,7 @@ #define CONFIG_POWER_TPS65090_EC #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
+#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 37dc092..71d8480 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,9 +9,28 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H
+#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include <configs/exynos5250-common.h>
#undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250
+#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 2eaff21..56f3c02 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -11,6 +11,8 @@
#include <configs/exynos5420-common.h>
+#define CONFIG_BOARD_COMMON + #define CONFIG_SMDK5420 /* which is in a SMDK5420 */
#undef CONFIG_DEFAULT_DEVICE_TREE @@ -21,5 +23,6 @@
#define CONFIG_SYS_PROMPT "SMDK5420 # " #define CONFIG_IDENT_STRING " for SMDK5420" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 93a03b1..246e958 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,6 +9,13 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H
+#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include <configs/exynos5250-common.h> #include <configs/exynos5-dt-common.h>
@@ -18,4 +25,14 @@ #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C
+#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "snow # " +#define CONFIG_IDENT_STRING " for snow" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_SNOW_H */
Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Leave in a few configs which are not in fact common to all boards
arch/arm/dts/Makefile | 1 + arch/arm/dts/exynos4210-smdkv310.dts | 21 ++++++++++++ include/configs/smdkv310.h | 64 ++++++++---------------------------- 3 files changed, 35 insertions(+), 51 deletions(-) create mode 100644 arch/arm/dts/exynos4210-smdkv310.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f2b946..43a70e4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ exynos4412-trats2.dtb \ diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts new file mode 100644 index 0000000..c390c8f --- /dev/null +++ b/arch/arm/dts/exynos4210-smdkv310.dts @@ -0,0 +1,21 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung SMDKV310 on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + }; + +}; diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 048c178..871d7b9 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -9,71 +9,42 @@ #ifndef __CONFIG_H #define __CONFIG_H
+#include "exynos4-common.h" + +#undef CONFIG_BOARD_COMMON +#undef CONFIG_USB_GADGET +#undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_REVISION_TAG +#undef CONFIG_CMD_THOR_DOWNLOAD +#undef CONFIG_CMD_DFU + /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ -#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/
-#include <asm/arch/cpu.h> /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - /* Mach Type */ #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
#define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000
-/* input clock of PLL: SMDKV310 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 #define S5P_CHECK_LPA 0xABAD0000
-/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* select serial console configuration */ #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
-/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-/* Command definition*/ -#include <config_cmd_default.h> - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC #define CONFIG_CMD_NET -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK
/* MMC SPL */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -84,15 +55,8 @@ #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "SMDKV310 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) @@ -111,8 +75,6 @@ #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for SMDKC210/V310"
#define CONFIG_CLK_1000_400_200 @@ -126,7 +88,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1
#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -146,6 +107,7 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/
-/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-smdkv310 + #endif /* __CONFIG_H */
Change this board to add a device tree.
This also adds a pinmux header file although it is not used as yet.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: - Adjust device tree file based on Robert Baldyga's example
Changes in v2: - Avoid using a common file, and just add a device tree - Fix device tree base addresses
arch/arm/dts/Makefile | 1 + arch/arm/dts/s5pc1xx-goni.dts | 28 ++++++++++++++ arch/arm/include/asm/arch-s5pc1xx/periph.h | 61 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-s5pc1xx/pinmux.h | 50 ++++++++++++++++++++++++ drivers/mmc/s5p_sdhci.c | 2 - include/configs/s5p_goni.h | 7 +++- 6 files changed, 146 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/s5pc1xx-goni.dts create mode 100644 arch/arm/include/asm/arch-s5pc1xx/periph.h create mode 100644 arch/arm/include/asm/arch-s5pc1xx/pinmux.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 43a70e4..076e0f7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts new file mode 100644 index 0000000..2e671bb --- /dev/null +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -0,0 +1,28 @@ +/* + * Samsung's S5PC110-based Goni board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung Goni based on S5PC110"; + compatible = "samsung,goni", "samsung,s5pc110"; + + aliases { + serial2 = "/serial@e2900800"; + console = "/serial@e2900800"; + }; + + serial@e2900800 { + compatible = "samsung,exynos4210-uart"; + reg = <0xe2900800 0x400>; + id = <2>; + }; + +}; diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/include/asm/arch-s5pc1xx/periph.h new file mode 100644 index 0000000..5c1c3d4 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/periph.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde rajeshwari.s@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2S0 = 98, + PERIPH_ID_I2S1 = 99, + + /* Since following peripherals do + * not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum + * SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, + + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h new file mode 100644 index 0000000..0b91ef6 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan a.kesavan@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blob + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); +#endif diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 2ff0ec2..637dd97 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -14,9 +14,7 @@ #include <asm/arch/mmc.h> #include <asm/arch/clk.h> #include <errno.h> -#ifdef CONFIG_OF_CONTROL #include <asm/arch/pinmux.h> -#endif
static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index a51215d..b22ac18 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -53,6 +53,7 @@ #define CONFIG_MMC #define CONFIG_SDHCI #define CONFIG_S5P_SDHCI +#define SDHCI_MAX_HOSTS 4
/* PWM */ #define CONFIG_PWM 1 @@ -106,7 +107,6 @@ ",12m(modem)"\ ",60m(qboot)\0"
-#define CONFIG_BOOTDELAY 1 #define CONFIG_ZERO_BOOTDELAY_CHECK
/* partitions definitions */ @@ -283,4 +283,9 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_DEFAULT_DEVICE_TREE s5pc1xx-goni +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */
Change this board to add a device tree.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Avoid using a common file, and just add a device tree - Fix device tree base addresses
arch/arm/dts/Makefile | 1 + arch/arm/dts/s5pc1xx-smdkc100.dts | 29 +++++++++++++++++++++++++++++ include/configs/smdkc100.h | 5 +++++ 3 files changed, 35 insertions(+) create mode 100644 arch/arm/dts/s5pc1xx-smdkc100.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 076e0f7..c37580e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts new file mode 100644 index 0000000..42754ce --- /dev/null +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -0,0 +1,29 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung SMDKC100 based on S5PC100"; + compatible = "samsung,smdkc100", "samsung,s5pc100"; + + aliases { + serial0 = "/serial@ec000000"; + console = "/serial@ec000000"; + }; + + serial@ec000000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xec000000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + +}; diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index c9a2e15..1623963 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -217,4 +217,9 @@ #define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */
+#define CONFIG_DEFAULT_DEVICE_TREE s5pc1xx-smdkc100 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */
Enable this feature to support driver model before relocation.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: None
include/configs/exynos-common.h | 5 +++-- include/configs/odroid.h | 2 -- include/configs/s5p_goni.h | 5 +++-- include/configs/smdkc100.h | 4 ++++ 4 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 1e0ceab..98ea46f 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -40,8 +40,9 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_ENV_OVERWRITE
-/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
/* select serial console configuration */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 3309469..cecee68 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -39,8 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000
#include <linux/sizes.h> -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */ #define CONFIG_SERIAL1 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index b22ac18..ec78b6e 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -39,8 +39,9 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING
-/* Size of malloc() pool.*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
/* * select serial console configuration diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 1623963..2ccae5c 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -47,6 +47,10 @@ * 1MB = 0x100000, 0x100000 = 1024 * 1024 */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* Small malloc pool before relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* * select serial console configuration */
Hi Minkyu,
On 23 September 2014 12:59, Simon Glass sjg@chromium.org wrote:
This series tries to unify the Samsung board configs into a few header files for exynos5 and exynos4.
The purpose is to make it easier to move to driver model. In that case I would like things like the GPIO drivers and serial drivers to work in a standard way, and not need to support device tree and platform data at the same time. That would be quite painful.
Another reason is that the Chrome OS EC drivers are currently included in boards that don't have a Chrome OS EC. This concern was raised by the Samsung maintainer (Minkyu) a while back.
There are still a few boards that don't use CONFIG_OF_CONTROL so I have updated these with the most rudimentary of device tree files and updated them based on feedback.
This series has the side-effect of getting the EC interface working properly on Pit, so the keyboard works. It also provides access to the TPS65090 PMIC, which means that the backlight is enabled.
Please let me know if this series looks OK and can be applied soon.
Regards, Simon
participants (2)
-
Minkyu Kang -
Simon Glass