[U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

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Peng Fan

11 Sep 2014 11 Sep '14

3:55 a.m.

Configure the pad setting and enable qspi clock to support qspi flashes access.

This patch has been tested on mx6sxsabresd board.

Signed-off-by: Peng Fan Peng.Fan@freescale.com ---

Changelog v2: Take Fabio's suggestion, split soc code and board code into two patches. This patch needs 'ARM:MX6SX Add QSPI support' patch.

board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++++++++++++++++++++++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++++ 2 files changed, 54 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5eaec1b..f9cad5a 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }

+#ifdef CONFIG_FSL_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; }

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eda65e..00031ec 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -201,6 +201,20 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH

+#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI2_ARB_BASE_ADDR +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif + #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC

-- 1.8.4

Show replies by date

Peng.Fan＠freescale.com

11 Sep 11 Sep

4:30 a.m.

Just CC Stefano Babic sbabic@denx.de

Regards, Peng.

-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Peng Fan Sent: Thursday, September 11, 2014 9:56 AM To: Estevam Fabio-R49496; Li Ye-B37916 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

Configure the pad setting and enable qspi clock to support qspi flashes access.

This patch has been tested on mx6sxsabresd board.

Signed-off-by: Peng Fan Peng.Fan@freescale.com ---

Changelog v2: Take Fabio's suggestion, split soc code and board code into two patches. This patch needs 'ARM:MX6SX Add QSPI support' patch.

board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++++++++++++++++++++++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++++ 2 files changed, 54 insertions(+)

+#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; }

_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Peng Fan

9 Oct 9 Oct

11:07 a.m.

Hi,

Any reply about this patch? It is long time since this patch was sent out.

Regards, Peng. On 09/11/2014 10:30 AM, Fan Peng-B51431 wrote:

...

Just CC Stefano Babic sbabic@denx.de

Regards, Peng.

-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Peng Fan Sent: Thursday, September 11, 2014 9:56 AM To: Estevam Fabio-R49496; Li Ye-B37916 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

Configure the pad setting and enable qspi clock to support qspi flashes access.

This patch has been tested on mx6sxsabresd board.

Signed-off-by: Peng Fan Peng.Fan@freescale.com

Changelog v2: Take Fabio's suggestion, split soc code and board code into two patches. This patch needs 'ARM:MX6SX Add QSPI support' patch.

board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++++++++++++++++++++++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++++ 2 files changed, 54 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5eaec1b..f9cad5a 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }

+#ifdef CONFIG_FSL_QSPI

+#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+static iomux_v3_cfg_t const quadspi_pads[] = {

MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),

+};

+int board_qspi_init(void) +{
/* Set the iomux */

imx_iomux_v3_setup_multiple_pads(quadspi_pads,
			 ARRAY_SIZE(quadspi_pads));
/* Set the clock */

enable_qspi_clk(1);

return 0;
+} +#endif

int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+#ifdef CONFIG_FSL_QSPI

board_qspi_init();

+#endif

return 0;

}

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eda65e..00031ec 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -201,6 +201,20 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH

+#define CONFIG_FSL_QSPI

+#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI2_ARB_BASE_ADDR +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif

#define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K

#define CONFIG_ENV_IS_IN_MMC

1.8.4

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Jagan Teki

12:37 p.m.

Hi Peng Fan,

Before reviewing these two patches, I'm requesting some sort work from your side like Can you update/fix the driver "drivers/spi/fsl_qspi.c" without using flash opcodes.

Using flash opcode's with in the (q)spi driver is not recommended please think on that direction.

On 9 October 2014 14:37, Peng Fan B51431@freescale.com wrote:

...

Hi,

Any reply about this patch? It is long time since this patch was sent out.

Regards, Peng. On 09/11/2014 10:30 AM, Fan Peng-B51431 wrote:

...
Just CC Stefano Babic sbabic@denx.de

Regards, Peng.

-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Peng Fan Sent: Thursday, September 11, 2014 9:56 AM To: Estevam Fabio-R49496; Li Ye-B37916 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

Configure the pad setting and enable qspi clock to support qspi flashes access.

This patch has been tested on mx6sxsabresd board.

Signed-off-by: Peng Fan Peng.Fan@freescale.com

Changelog v2: Take Fabio's suggestion, split soc code and board code into two patches. This patch needs 'ARM:MX6SX Add QSPI support' patch.

board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++++++++++++++++++++++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++++ 2 files changed, 54 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5eaec1b..f9cad5a 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }

+#ifdef CONFIG_FSL_QSPI

+#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1    | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_ALE__QSPI2_A_SS0_B         | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CLE__QSPI2_A_SCLK          | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA07__QSPI2_A_DQS        | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA05__QSPI2_B_DQS        | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};

+int board_qspi_init(void) +{
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
                                 ARRAY_SIZE(quadspi_pads));
/* Set the clock */
enable_qspi_clk(1);
return 0;
+} +#endif

int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+#ifdef CONFIG_FSL_QSPI
board_qspi_init();
+#endif
return 0;
}

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eda65e..00031ec 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -201,6 +201,20 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH

+#define CONFIG_FSL_QSPI

+#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI2_ARB_BASE_ADDR +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif

#define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K

#define CONFIG_ENV_IS_IN_MMC

1.8.4

thanks!

-- Jagan.

Peng Fan

10 Oct 10 Oct

3:56 a.m.

Hi,

On 10/09/2014 06:37 PM, Jagan Teki wrote:

...

Hi Peng Fan,

Before reviewing these two patches, I'm requesting some sort work from your side like Can you update/fix the driver "drivers/spi/fsl_qspi.c" without using flash opcodes.

Using flash opcode's with in the (q)spi driver is not recommended please think on that direction.

Yeah, many OPCODE_XX are used in this driver.

There is a LUT table containing 16 entries in the QSPI Controller. The Look-up-table or LUT consists of a number of pre-programmed sequences. Each sequence is basically a sequence of instruction-operand pairs which when executed sequentially generates a valid serial flash transaction. Each sequence can have a maximum of 8 instruction-operand pairs. The instruction holds the flash opcode that should be pre-programmed, and the qspi_set_lut in drivers/spi/fsl_qspi.c does this work.

It is not easy to program the lut dynamically in the driver without using the flash opcodes. So I wonder whether CMD_xxx in drivers/mtd/spi/sf_internal.h can be used or not. Or, can QSPI_CMD_xxx be used but not OPCODE_xx? Actually if QSPI_CMD_xx can be used, the value QSPI_CMD_xx is the same with OPCODE_xx, just different macro names.

Regards, Peng.

...

On 9 October 2014 14:37, Peng Fan B51431@freescale.com wrote:

...
Hi,

Any reply about this patch? It is long time since this patch was sent out.

Regards, Peng. On 09/11/2014 10:30 AM, Fan Peng-B51431 wrote:

...
Just CC Stefano Babic sbabic@denx.de

Regards, Peng.

-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Peng Fan Sent: Thursday, September 11, 2014 9:56 AM To: Estevam Fabio-R49496; Li Ye-B37916 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

Configure the pad setting and enable qspi clock to support qspi flashes access.

This patch has been tested on mx6sxsabresd board.

Signed-off-by: Peng Fan Peng.Fan@freescale.com

Changelog v2: Take Fabio's suggestion, split soc code and board code into two patches. This patch needs 'ARM:MX6SX Add QSPI support' patch.

board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++++++++++++++++++++++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++++ 2 files changed, 54 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5eaec1b..f9cad5a 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }

+#ifdef CONFIG_FSL_QSPI

+#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1    | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_ALE__QSPI2_A_SS0_B         | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CLE__QSPI2_A_SCLK          | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA07__QSPI2_A_DQS        | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA05__QSPI2_B_DQS        | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};

+int board_qspi_init(void) +{
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
                                 ARRAY_SIZE(quadspi_pads));
/* Set the clock */
enable_qspi_clk(1);
return 0;
+} +#endif

int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+#ifdef CONFIG_FSL_QSPI
board_qspi_init();
+#endif
return 0;
}

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eda65e..00031ec 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -201,6 +201,20 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH

+#define CONFIG_FSL_QSPI

+#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI2_ARB_BASE_ADDR +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif

#define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K

#define CONFIG_ENV_IS_IN_MMC

1.8.4
thanks!

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Jagan Teki
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Peng.Fan＠freescale.com