[U-Boot] [PATCH 1/9] gpio: renesas: Add RZ/A1 R7S72100 GPIO driver
Add GPIO driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/gpio/Kconfig | 6 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rza1.c | 134 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/gpio/gpio-rza1.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b3e4ecc50e..4e2095dcd6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -169,6 +169,12 @@ config RCAR_GPIO help This driver supports the GPIO banks on Renesas RCar SoCs.
+config RZA1_GPIO + bool "Renesas RZ/A1 GPIO driver" + depends on DM_GPIO && RZA1 + help + This driver supports the GPIO banks on Renesas RZ/A1 R7S72100 SoCs. + config ROCKCHIP_GPIO bool "Rockchip GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3be325044f..7337153e0e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PCA953X) += pca953x.o obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o +obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o obj-$(CONFIG_S5P) += s5p_gpio.o obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o diff --git a/drivers/gpio/gpio-rza1.c b/drivers/gpio/gpio-rza1.c new file mode 100644 index 0000000000..ce2453e2ba --- /dev/null +++ b/drivers/gpio/gpio-rza1.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marek Vasut marek.vasut@gmail.com + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#define P(bank) (0x0000 + (bank) * 4) +#define PSR(bank) (0x0100 + (bank) * 4) +#define PPR(bank) (0x0200 + (bank) * 4) +#define PM(bank) (0x0300 + (bank) * 4) +#define PMC(bank) (0x0400 + (bank) * 4) +#define PFC(bank) (0x0500 + (bank) * 4) +#define PFCE(bank) (0x0600 + (bank) * 4) +#define PNOT(bank) (0x0700 + (bank) * 4) +#define PMSR(bank) (0x0800 + (bank) * 4) +#define PMCSR(bank) (0x0900 + (bank) * 4) +#define PFCAE(bank) (0x0A00 + (bank) * 4) +#define PIBC(bank) (0x4000 + (bank) * 4) +#define PBDC(bank) (0x4100 + (bank) * 4) +#define PIPC(bank) (0x4200 + (bank) * 4) + +#define RZA1_MAX_GPIO_PER_BANK 16 + +DECLARE_GLOBAL_DATA_PTR; + +struct r7s72100_gpio_priv { + void __iomem *regs; + int bank; +}; + +static int r7s72100_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct r7s72100_gpio_priv *priv = dev_get_priv(dev); + + return !!(readw(priv->regs + PPR(priv->bank)) & BIT(offset)); +} + +static int r7s72100_gpio_set_value(struct udevice *dev, unsigned line, + int value) +{ + struct r7s72100_gpio_priv *priv = dev_get_priv(dev); + + writel(BIT(line + 16) | (value ? BIT(line) : 0), + priv->regs + PSR(priv->bank)); + + return 0; +} + +static void r7s72100_gpio_set_direction(struct udevice *dev, unsigned line, + bool output) +{ + struct r7s72100_gpio_priv *priv = dev_get_priv(dev); + + writel(BIT(line + 16), priv->regs + PMCSR(priv->bank)); + writel(BIT(line + 16) | (output ? 0 : BIT(line)), + priv->regs + PMSR(priv->bank)); + + clrsetbits_le16(priv->regs + PIBC(priv->bank), BIT(line), + output ? 0 : BIT(line)); +} + +static int r7s72100_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + r7s72100_gpio_set_direction(dev, offset, false); + return 0; +} + +static int r7s72100_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + /* write GPIO value to output before selecting output mode of pin */ + r7s72100_gpio_set_value(dev, offset, value); + r7s72100_gpio_set_direction(dev, offset, true); + + return 0; +} + +static int r7s72100_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct r7s72100_gpio_priv *priv = dev_get_priv(dev); + + if (readw(priv->regs + PM(priv->bank)) & BIT(offset)) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops r7s72100_gpio_ops = { + .direction_input = r7s72100_gpio_direction_input, + .direction_output = r7s72100_gpio_direction_output, + .get_value = r7s72100_gpio_get_value, + .set_value = r7s72100_gpio_set_value, + .get_function = r7s72100_gpio_get_function, +}; + +static int r7s72100_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct r7s72100_gpio_priv *priv = dev_get_priv(dev); + struct fdtdec_phandle_args args; + int node = dev_of_offset(dev); + int ret; + + fdt_addr_t addr_base; + + uc_priv->bank_name = dev->name; + dev = dev_get_parent(dev); + addr_base = devfdt_get_addr(dev); + if (addr_base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = (void __iomem *)addr_base; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", + NULL, 3, 0, &args); + priv->bank = ret == 0 ? (args.args[1] / RZA1_MAX_GPIO_PER_BANK) : -1; + uc_priv->gpio_count = ret == 0 ? args.args[2] : RZA1_MAX_GPIO_PER_BANK; + + return 0; +} + +U_BOOT_DRIVER(r7s72100_gpio) = { + .name = "r7s72100-gpio", + .id = UCLASS_GPIO, + .ops = &r7s72100_gpio_ops, + .priv_auto_alloc_size = sizeof(struct r7s72100_gpio_priv), + .probe = r7s72100_gpio_probe, +};
Add pin control driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/pinctrl/renesas/Kconfig | 12 ++ drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc-r7s72100.c | 146 +++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/pinctrl/renesas/pfc-r7s72100.c
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 152414ce31..0ffd7fcfd4 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -3,6 +3,7 @@ if ARCH_RMOBILE config PINCTRL_PFC bool "Renesas pin control drivers" depends on DM && ARCH_RMOBILE + default n if CPU_RZA1 help Enable support for clock present on Renesas RCar SoCs.
@@ -116,4 +117,15 @@ config PINCTRL_PFC_R8A77995 the GPIO definitions and pin control functions for each available multiplex function.
+config PINCTRL_PFC_R7S72100 + bool "Renesas RZ/A1 R7S72100 pin control driver" + depends on CPU_RZA1 + default y if CPU_RZA1 + help + Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + endif diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 596b0023a3..e8703f681e 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o +obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o diff --git a/drivers/pinctrl/renesas/pfc-r7s72100.c b/drivers/pinctrl/renesas/pfc-r7s72100.c new file mode 100644 index 0000000000..7e4530d684 --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r7s72100.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * R7S72100 processor support + * + * Copyright (C) 2019 Marek Vasut marek.vasut@gmail.com + */ + +#include <common.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <linux/io.h> +#include <linux/err.h> + +#define P(bank) (0x0000 + (bank) * 4) +#define PSR(bank) (0x0100 + (bank) * 4) +#define PPR(bank) (0x0200 + (bank) * 4) +#define PM(bank) (0x0300 + (bank) * 4) +#define PMC(bank) (0x0400 + (bank) * 4) +#define PFC(bank) (0x0500 + (bank) * 4) +#define PFCE(bank) (0x0600 + (bank) * 4) +#define PNOT(bank) (0x0700 + (bank) * 4) +#define PMSR(bank) (0x0800 + (bank) * 4) +#define PMCSR(bank) (0x0900 + (bank) * 4) +#define PFCAE(bank) (0x0A00 + (bank) * 4) +#define PIBC(bank) (0x4000 + (bank) * 4) +#define PBDC(bank) (0x4100 + (bank) * 4) +#define PIPC(bank) (0x4200 + (bank) * 4) + +#define RZA1_PINS_PER_PORT 16 + +DECLARE_GLOBAL_DATA_PTR; + +struct r7s72100_pfc_platdata { + void __iomem *base; +}; + +static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line, + u16 func, u16 inbuf, u16 bidir) +{ + struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev); + + clrsetbits_le16(plat->base + PFCAE(bank), BIT(line), + (func & BIT(2)) ? BIT(line) : 0); + clrsetbits_le16(plat->base + PFCE(bank), BIT(line), + (func & BIT(1)) ? BIT(line) : 0); + clrsetbits_le16(plat->base + PFC(bank), BIT(line), + (func & BIT(0)) ? BIT(line) : 0); + + clrsetbits_le16(plat->base + PIBC(bank), BIT(line), + inbuf ? BIT(line) : 0); + clrsetbits_le16(plat->base + PBDC(bank), BIT(line), + bidir ? BIT(line) : 0); + + setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line)); + + setbits_le16(plat->base + PIPC(bank), BIT(line)); +} + +static int r7s72100_pfc_set_state(struct udevice *dev, struct udevice *config) +{ + const void *blob = gd->fdt_blob; + int node = dev_of_offset(config); + u32 cells[32]; + u16 bank, line, func; + int i, count, bidir; + + count = fdtdec_get_int_array_count(blob, node, "pinmux", + cells, ARRAY_SIZE(cells)); + if (count < 0) { + printf("%s: bad pinmux array %d\n", __func__, count); + return -EINVAL; + } + + if (count > ARRAY_SIZE(cells)) { + printf("%s: unsupported pinmux array count %d\n", + __func__, count); + return -EINVAL; + } + + for (i = 0 ; i < count; i++) { + func = (cells[i] >> 16) & 0xf; + if (func == 0 || func > 8) { + printf("Invalid cell %i in node %s!\n", + count, ofnode_get_name(dev_ofnode(config))); + continue; + } + + func = (func - 1) & 0x7; + + bank = (cells[i] / RZA1_PINS_PER_PORT) & 0xff; + line = cells[i] % RZA1_PINS_PER_PORT; + + bidir = 0; + if (bank == 3 && line == 3 && func == 1) + bidir = 1; + + r7s72100_pfc_set_function(dev, bank, line, func, 0, bidir); + } + + return 0; +} + +const struct pinctrl_ops r7s72100_pfc_ops = { + .set_state = r7s72100_pfc_set_state, +}; + +static int r7s72100_pfc_probe(struct udevice *dev) +{ + struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr_base; + ofnode node; + + addr_base = devfdt_get_addr(dev); + if (addr_base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = (void __iomem *)addr_base; + + dev_for_each_subnode(node, dev) { + struct udevice *cdev; + + if (!ofnode_read_bool(node, "gpio-controller")) + continue; + + device_bind_driver_to_node(dev, "r7s72100-gpio", + ofnode_get_name(node), + node, &cdev); + } + + return 0; +} + +static const struct udevice_id r7s72100_pfc_match[] = { + { .compatible = "renesas,r7s72100-ports" }, + {} +}; + +U_BOOT_DRIVER(r7s72100_pfc) = { + .name = "r7s72100_pfc", + .id = UCLASS_PINCTRL, + .of_match = r7s72100_pfc_match, + .probe = r7s72100_pfc_probe, + .platdata_auto_alloc_size = sizeof(struct r7s72100_pfc_platdata), + .ops = &r7s72100_pfc_ops, +};
Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/ostm_timer.c | 92 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/timer/ostm_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index df37a798bd..5f4bc6edb6 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -110,6 +110,13 @@ config MPC83XX_TIMER Select this to enable support for the timer found on devices based on the MPC83xx family of SoCs.
+config RENESAS_OSTM_TIMER + bool "Renesas RZ/A1 R7S72100 OSTM Timer" + depends on TIMER + help + Enables support for the Renesas OSTM Timer driver. + This timer is present on Renesas RZ/A1 R7S72100 SoCs. + config X86_TSC_TIMER_EARLY_FREQ int "x86 TSC timer frequency in MHz when used as the early timer" depends on X86_TSC_TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index d0bf218b11..fa35bea6c5 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o +obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c new file mode 100644 index 0000000000..f0e25093ca --- /dev/null +++ b/drivers/timer/ostm_timer.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas RZ/A1 R7S72100 OSTM Timer driver + * + * Copyright (C) 2019 Marek Vasut marek.vasut@gmail.com + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <clk.h> +#include <timer.h> + +#define OSTM_CMP 0x00 +#define OSTM_CNT 0x04 +#define OSTM_TE 0x10 +#define OSTM_TS 0x14 +#define OSTM_TT 0x18 +#define OSTM_CTL 0x20 +#define OSTM_CTL_D BIT(1) + +DECLARE_GLOBAL_DATA_PTR; + +struct ostm_priv { + fdt_addr_t regs; +}; + +static int ostm_get_count(struct udevice *dev, u64 *count) +{ + struct ostm_priv *priv = dev_get_priv(dev); + + *count = timer_conv_64(readl(priv->regs + OSTM_CNT)); + + return 0; +} + +static int ostm_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct ostm_priv *priv = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + uc_priv->clock_rate = clk_get_rate(&clk); + + clk_free(&clk); +#else + uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2; +#endif + + readb(priv->regs + OSTM_CTL); + writeb(OSTM_CTL_D, priv->regs + OSTM_CTL); + + setbits_8(priv->regs + OSTM_TT, BIT(0)); + writel(0xffffffff, priv->regs + OSTM_CMP); + setbits_8(priv->regs + OSTM_TS, BIT(0)); + + return 0; +} + +static int ostm_ofdata_to_platdata(struct udevice *dev) +{ + struct ostm_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr(dev); + + return 0; +} + +static const struct timer_ops ostm_ops = { + .get_count = ostm_get_count, +}; + +static const struct udevice_id ostm_ids[] = { + { .compatible = "renesas,ostm" }, + {} +}; + +U_BOOT_DRIVER(ostm_timer) = { + .name = "ostm-timer", + .id = UCLASS_TIMER, + .ops = &ostm_ops, + .probe = ostm_probe, + .of_match = ostm_ids, + .ofdata_to_platdata = ostm_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct ostm_priv), +};
Add support for RZ/A1 SoC specifics.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/serial/serial_sh.c | 3 +++ drivers/serial/serial_sh.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e6fe5c7c67..8f52f9dce4 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -62,6 +62,9 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); sci_in(port, SCFCR); sci_out(port, SCFCR, 0); +#if defined(CONFIG_RZA1) + sci_out(port, SCSPTR, 0x0003); +#endif }
static void diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 887dd19ff5..8aa80d4a37 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -195,7 +195,7 @@ struct uart_port { # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ # endif # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_CPU_SH7269) +#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1) # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ @@ -205,6 +205,7 @@ struct uart_port { # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +# define SCIF_ORER 0x0001 /* overrun error bit */ #elif defined(CONFIG_CPU_SH7619) # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
Add support for RZ/A1 SoC specifics.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/net/sh_eth.h | 56 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index d8b4bda3ef..e1bbd4913f 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -228,6 +228,60 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { [RMII_MII] = 0x0790, };
+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PIR] = 0x0520, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; + static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [ECMR] = 0x0100, [RFLR] = 0x0108, @@ -603,6 +657,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port, const u16 *reg_offset = sh_eth_offset_gigabit; #elif defined(SH_ETH_TYPE_ETHER) const u16 *reg_offset = sh_eth_offset_fast_sh4; +#elif defined(SH_ETH_TYPE_RZ) + const u16 *reg_offset = sh_eth_offset_rz; #else #error #endif
On Sat, May 4, 2019 at 12:28 PM Marek Vasut marek.vasut@gmail.com wrote:
Add support for RZ/A1 SoC specifics.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org
Acked-by: Joe Hershberger joe.hershberger@ni.com
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/net/sh_eth.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index a2577e1e8f..8e54e7cc7a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -806,9 +806,11 @@ static int sh_ether_probe(struct udevice *udev)
priv->iobase = pdata->iobase;
+#if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(udev, 0, &priv->clk); if (ret < 0) return ret; +#endif
ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args); if (!ret) { @@ -843,9 +845,11 @@ static int sh_ether_probe(struct udevice *udev) eth->port_info[eth->port].iobase = (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
+#if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&priv->clk); if (ret) goto err_mdio_register; +#endif
ret = sh_eth_phy_config(udev); if (ret) { @@ -856,7 +860,9 @@ static int sh_ether_probe(struct udevice *udev) return 0;
err_phy_config: +#if CONFIG_IS_ENABLED(CLK) clk_disable(&priv->clk); +#endif err_mdio_register: mdio_free(mdiodev); return ret; @@ -868,7 +874,9 @@ static int sh_ether_remove(struct udevice *udev) struct sh_eth_dev *eth = &priv->shdev; struct sh_eth_info *port_info = ð->port_info[eth->port];
+#if CONFIG_IS_ENABLED(CLK) clk_disable(&priv->clk); +#endif free(port_info->phydev); mdio_unregister(priv->bus); mdio_free(priv->bus); @@ -917,6 +925,7 @@ int sh_ether_ofdata_to_platdata(struct udevice *dev) }
static const struct udevice_id sh_ether_ids[] = { + { .compatible = "renesas,ether-r7s72100" }, { .compatible = "renesas,ether-r8a7790" }, { .compatible = "renesas,ether-r8a7791" }, { .compatible = "renesas,ether-r8a7793" },
On Sat, May 4, 2019 at 12:28 PM Marek Vasut marek.vasut@gmail.com wrote:
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org
Acked-by: Joe Hershberger joe.hershberger@ni.com
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Jagan Teki jagan@amarulasolutions.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/spi/Kconfig | 2 +- drivers/spi/renesas_rpc_spi.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fb794adae7..9138425d40 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -173,7 +173,7 @@ config PL022_SPI
config RENESAS_RPC_SPI bool "Renesas RPC SPI driver" - depends on RCAR_GEN3 + depends on RCAR_GEN3 || RZA1 imply SPI_FLASH_BAR help Enable the Renesas RPC SPI driver, used to access SPI NOR flash diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index bec9095ff4..bb2e7748fe 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -409,27 +409,30 @@ static int rpc_spi_probe(struct udevice *dev)
priv->regs = plat->regs; priv->extr = plat->extr; - +#if CONFIG_IS_ENABLED(CLK) clk_enable(&priv->clk); - +#endif return 0; }
static int rpc_spi_ofdata_to_platdata(struct udevice *bus) { struct rpc_spi_platdata *plat = dev_get_platdata(bus); - struct rpc_spi_priv *priv = dev_get_priv(bus); - int ret;
plat->regs = dev_read_addr_index(bus, 0); plat->extr = dev_read_addr_index(bus, 1);
+#if CONFIG_IS_ENABLED(CLK) + struct rpc_spi_priv *priv = dev_get_priv(bus); + int ret; + ret = clk_get_by_index(bus, 0, &priv->clk); if (ret < 0) { printf("%s: Could not get clock for %s: %d\n", __func__, bus->name, ret); return ret; } +#endif
plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
@@ -448,6 +451,7 @@ static const struct udevice_id rpc_spi_ids[] = { { .compatible = "renesas,rpc-r8a77965" }, { .compatible = "renesas,rpc-r8a77970" }, { .compatible = "renesas,rpc-r8a77995" }, + { .compatible = "renesas,rpc-r7s72100" }, { } };
From: Chris Brandt chris.brandt@renesas.com
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM).
The DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/Kconfig | 2 +- arch/arm/dts/r7s72100.dtsi | 705 ++++++++++++++++++ arch/arm/mach-rmobile/Kconfig | 5 + arch/arm/mach-rmobile/Kconfig.rza1 | 21 + arch/arm/mach-rmobile/cpu_info.c | 8 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + include/dt-bindings/clock/r7s72100-clock.h | 112 +++ .../dt-bindings/pinctrl/r7s72100-pinctrl.h | 18 + 8 files changed, 871 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r7s72100.dtsi create mode 100644 arch/arm/mach-rmobile/Kconfig.rza1 create mode 100644 include/dt-bindings/clock/r7s72100-clock.h create mode 100644 include/dt-bindings/pinctrl/r7s72100-pinctrl.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49f01f1ff1..70a14eef48 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -785,7 +785,7 @@ config ARCH_QEMU
config ARCH_RMOBILE bool "Renesas ARM SoCs" - select BOARD_EARLY_INIT_F + select BOARD_EARLY_INIT_F if !RZA1 select DM select DM_SERIAL imply CMD_DM diff --git a/arch/arm/dts/r7s72100.dtsi b/arch/arm/dts/r7s72100.dtsi new file mode 100644 index 0000000000..2211f88ede --- /dev/null +++ b/arch/arm/dts/r7s72100.dtsi @@ -0,0 +1,705 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r7s72100 SoC + * + * Copyright (C) 2013-14 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering wsa@sang-engineering.com + */ + +#include <dt-bindings/clock/r7s72100-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "renesas,r7s72100"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + + /* Fixed factor clocks */ + b_clk: b { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <3>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; + next-level-cache = <&L2>; + }; + }; + + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; + + p0_clk: p0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <12>; + }; + + p1_clk: p1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <6>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 32678 */ + clock-frequency = <0>; + }; + + rtc_x3_clk: rtc_x3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board to 4000000 */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + L2: cache-controller@3ffff000 { + compatible = "arm,pl310-cache"; + reg = <0x3ffff000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007000 64>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007800 64>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008000 64>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008800 64>; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009000 64>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e8009800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009800 64>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif6: serial@e800a000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a000 64>; + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif7: serial@e800a800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a800 64>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + spi0: spi@e800c800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800c800 0x24>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@e800d000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d000 0x24>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@e800d800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d800 0x24>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@e800e000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e000 0x24>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@e800e800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e800 0x24>; + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + power-domains = <&cpg_clocks>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usbhs0: usb@e8010000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8010000 0x1a0>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R7S72100_CLK_USB0>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + usbhs1: usb@e8207000 { + compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; + reg = <0xe8207000 0x1a0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R7S72100_CLK_USB1>; + renesas,buswait = <4>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + mmcif: mmc@e804c800 { + compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; + reg = <0xe804c800 0x80>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + power-domains = <&cpg_clocks>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; + }; + + sdhi0: sd@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e804e800 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e800 0x100>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, + <&mstp12_clks R7S72100_CLK_SDHI11>; + clock-names = "core", "cd"; + power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + gic: interrupt-controller@e8201000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8201000 0x1000>, + <0xe8202000 0x1000>; + }; + + ether: ethernet@e8203000 { + compatible = "renesas,ether-r7s72100"; + reg = <0xe8203000 0x800>, + <0xe8204800 0x200>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R7S72100_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ceu: camera@e8210000 { + reg = <0xe8210000 0x3000>; + compatible = "renesas,r7s72100-ceu"; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp6_clks R7S72100_CLK_CEU>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + wdt: watchdog@fcfe0000 { + compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; + reg = <0xfcfe0000 0x6>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&p0_clk>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-cpg-clocks", + "renesas,rz-cpg-clocks"; + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; + #power-domain-cells = <0>; + }; + + /* MSTP clocks */ + mstp3_clks: mstp3_clks@fcfe0420 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0420 4>; + clocks = <&p0_clk>; + clock-indices = <R7S72100_CLK_MTU2>; + clock-output-names = "mtu2"; + }; + + mstp4_clks: mstp4_clks@fcfe0424 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0424 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 + R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 + >; + clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; + }; + + mstp5_clks: mstp5_clks@fcfe0428 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0428 4>; + clocks = <&p0_clk>, <&p0_clk>; + clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; + clock-output-names = "ostm0", "ostm1"; + }; + + mstp6_clks: mstp6_clks@fcfe042c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe042c 4>; + clocks = <&b_clk>, <&p0_clk>; + clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>; + clock-output-names = "ceu", "rtc"; + }; + + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; + clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>; + clock-output-names = "ether", "usb0", "usb1"; + }; + + mstp8_clks: mstp8_clks@fcfe0434 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0434 4>; + clocks = <&p1_clk>; + clock-indices = <R7S72100_CLK_MMCIF>; + clock-output-names = "mmcif"; + }; + + mstp9_clks: mstp9_clks@fcfe0438 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0438 4>; + clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; + clock-indices = < + R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 + >; + clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; + }; + + mstp10_clks: mstp10_clks@fcfe043c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe043c 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>; + clock-indices = < + R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 + R7S72100_CLK_SPI4 + >; + clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; + }; + mstp12_clks: mstp12_clks@fcfe0444 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0444 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 + R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 + >; + clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; + }; + + pinctrl: pin-controller@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + port0: gpio-0 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 6>; + }; + + port1: gpio-1 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + port2: gpio-2 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + port4: gpio-4 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + port5: gpio-5 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 80 11>; + }; + + port6: gpio-6 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + port7: gpio-7 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + port8: gpio-8 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + port9: gpio-9 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 144 8>; + }; + + port10: gpio-10 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 160 16>; + }; + + port11: gpio-11 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 176 16>; + }; + }; + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c1: i2c@fcfee400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee400 0x44>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c2: i2c@fcfee800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee800 0x44>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + i2c3: i2c@fcfeec00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfeec00 0x44>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + rtc: rtc@fcff1000 { + compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; + reg = <0xfcff1000 0x2e>; + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "alarm", "period", "carry"; + clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, + <&rtc_x3_clk>, <&extal_clk>; + clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + }; + + usb_x1_clk: usb_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index c6e5f75daf..bba02b3273 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -19,9 +19,14 @@ config RCAR_GEN3 imply CMD_MMC_SWRITE if MMC imply SUPPORT_EMMC_RPMB if MMC
+config RZA1 + prompt "Renesas ARM SoCs RZ/A1 (32bit)" + select CPU_V7A + endchoice
source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.64" +source "arch/arm/mach-rmobile/Kconfig.rza1"
endif diff --git a/arch/arm/mach-rmobile/Kconfig.rza1 b/arch/arm/mach-rmobile/Kconfig.rza1 new file mode 100644 index 0000000000..efb703b92b --- /dev/null +++ b/arch/arm/mach-rmobile/Kconfig.rza1 @@ -0,0 +1,21 @@ +if RZA1 + +# required by the Ethernet driver +config R7S72100 + bool + default y + +# required by serial and usb driver +config CPU_RZA1 + bool + default y + +choice + prompt "Renesas RZ/A1 board select" + +endchoice + +config SYS_SOC + default "rmobile" + +endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index aa5be52dfd..b0686ed203 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -26,6 +26,7 @@ void enable_caches(void) #endif
#ifdef CONFIG_DISPLAY_CPUINFO +#ifndef CONFIG_RZA1 static u32 __rmobile_get_cpu_type(void) { return 0x0; @@ -105,4 +106,11 @@ int print_cpuinfo(void)
return 0; } +#else +int print_cpuinfo(void) +{ + printf("CPU: Renesas Electronics RZ/A1\n"); + return 0; +} +#endif #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index c94b3ff509..aa8d43e59b 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -18,6 +18,7 @@ #include <asm/arch/r8a7794.h> #elif defined(CONFIG_RCAR_GEN3) #include <asm/arch/rcar-gen3-base.h> +#elif defined(CONFIG_R7S72100) #else #error "SOC Name not defined" #endif diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h new file mode 100644 index 0000000000..a267ac2501 --- /dev/null +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2014 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering wsa@sang-engineering.com + */ + +#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ +#define __DT_BINDINGS_CLOCK_R7S72100_H__ + +#define R7S72100_CLK_PLL 0 +#define R7S72100_CLK_I 1 +#define R7S72100_CLK_G 2 + +/* MSTP2 */ +#define R7S72100_CLK_CORESIGHT 0 + +/* MSTP3 */ +#define R7S72100_CLK_IEBUS 7 +#define R7S72100_CLK_IRDA 6 +#define R7S72100_CLK_LIN0 5 +#define R7S72100_CLK_LIN1 4 +#define R7S72100_CLK_MTU2 3 +#define R7S72100_CLK_CAN 2 +#define R7S72100_CLK_ADCPWR 1 +#define R7S72100_CLK_PWM 0 + +/* MSTP4 */ +#define R7S72100_CLK_SCIF0 7 +#define R7S72100_CLK_SCIF1 6 +#define R7S72100_CLK_SCIF2 5 +#define R7S72100_CLK_SCIF3 4 +#define R7S72100_CLK_SCIF4 3 +#define R7S72100_CLK_SCIF5 2 +#define R7S72100_CLK_SCIF6 1 +#define R7S72100_CLK_SCIF7 0 + +/* MSTP5 */ +#define R7S72100_CLK_SCI0 7 +#define R7S72100_CLK_SCI1 6 +#define R7S72100_CLK_SG0 5 +#define R7S72100_CLK_SG1 4 +#define R7S72100_CLK_SG2 3 +#define R7S72100_CLK_SG3 2 +#define R7S72100_CLK_OSTM0 1 +#define R7S72100_CLK_OSTM1 0 + +/* MSTP6 */ +#define R7S72100_CLK_ADC 7 +#define R7S72100_CLK_CEU 6 +#define R7S72100_CLK_DOC0 5 +#define R7S72100_CLK_DOC1 4 +#define R7S72100_CLK_DRC0 3 +#define R7S72100_CLK_DRC1 2 +#define R7S72100_CLK_JCU 1 +#define R7S72100_CLK_RTC 0 + +/* MSTP7 */ +#define R7S72100_CLK_VDEC0 7 +#define R7S72100_CLK_VDEC1 6 +#define R7S72100_CLK_ETHER 4 +#define R7S72100_CLK_NAND 3 +#define R7S72100_CLK_USB0 1 +#define R7S72100_CLK_USB1 0 + +/* MSTP8 */ +#define R7S72100_CLK_IMR0 7 +#define R7S72100_CLK_IMR1 6 +#define R7S72100_CLK_IMRDISP 5 +#define R7S72100_CLK_MMCIF 4 +#define R7S72100_CLK_MLB 3 +#define R7S72100_CLK_ETHAVB 2 +#define R7S72100_CLK_SCUX 1 + +/* MSTP9 */ +#define R7S72100_CLK_I2C0 7 +#define R7S72100_CLK_I2C1 6 +#define R7S72100_CLK_I2C2 5 +#define R7S72100_CLK_I2C3 4 +#define R7S72100_CLK_SPIBSC0 3 +#define R7S72100_CLK_SPIBSC1 2 +#define R7S72100_CLK_VDC50 1 /* and LVDS */ +#define R7S72100_CLK_VDC51 0 + +/* MSTP10 */ +#define R7S72100_CLK_SPI0 7 +#define R7S72100_CLK_SPI1 6 +#define R7S72100_CLK_SPI2 5 +#define R7S72100_CLK_SPI3 4 +#define R7S72100_CLK_SPI4 3 +#define R7S72100_CLK_CDROM 2 +#define R7S72100_CLK_SPDIF 1 +#define R7S72100_CLK_RGPVG2 0 + +/* MSTP11 */ +#define R7S72100_CLK_SSI0 5 +#define R7S72100_CLK_SSI1 4 +#define R7S72100_CLK_SSI2 3 +#define R7S72100_CLK_SSI3 2 +#define R7S72100_CLK_SSI4 1 +#define R7S72100_CLK_SSI5 0 + +/* MSTP12 */ +#define R7S72100_CLK_SDHI00 3 +#define R7S72100_CLK_SDHI01 2 +#define R7S72100_CLK_SDHI10 1 +#define R7S72100_CLK_SDHI11 0 + +/* MSTP13 */ +#define R7S72100_CLK_PIX1 2 +#define R7S72100_CLK_PIX0 1 + +#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h new file mode 100644 index 0000000000..31ee37610e --- /dev/null +++ b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/A1 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H +#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H + +#define RZA1_PINS_PER_PORT 16 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZA1_PINMUX(b, p, f) \ + ((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16)) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
From: Chris Brandt chris.brandt@renesas.com
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/dts/Makefile | 3 + arch/arm/dts/r7s72100-gr-peach-u-boot.dts | 78 +++++++++++++ arch/arm/dts/r7s72100-gr-peach.dts | 134 ++++++++++++++++++++++ arch/arm/mach-rmobile/Kconfig.rza1 | 7 ++ board/renesas/grpeach/Kconfig | 12 ++ board/renesas/grpeach/MAINTAINERS | 6 + board/renesas/grpeach/Makefile | 8 ++ board/renesas/grpeach/grpeach.c | 52 +++++++++ board/renesas/grpeach/lowlevel_init.S | 107 +++++++++++++++++ configs/grpeach_defconfig | 53 +++++++++ include/configs/grpeach.h | 53 +++++++++ 11 files changed, 513 insertions(+) create mode 100644 arch/arm/dts/r7s72100-gr-peach-u-boot.dts create mode 100644 arch/arm/dts/r7s72100-gr-peach.dts create mode 100644 board/renesas/grpeach/Kconfig create mode 100644 board/renesas/grpeach/MAINTAINERS create mode 100644 board/renesas/grpeach/Makefile create mode 100644 board/renesas/grpeach/grpeach.c create mode 100644 board/renesas/grpeach/lowlevel_init.S create mode 100644 configs/grpeach_defconfig create mode 100644 include/configs/grpeach.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8e082f2840..a199f3f988 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -603,6 +603,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77990-ebisu-u-boot.dtb \ r8a77995-draak-u-boot.dtb
+dtb-$(CONFIG_RZA1) += \ + r7s72100-gr-peach-u-boot.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts new file mode 100644 index 0000000000..28247d19d7 --- /dev/null +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the GR Peach board + * + * Copyright (C) 2019 Marek Vasut marek.vasut@gmail.com + */ + +#include "r7s72100-gr-peach.dts" + +/ { + aliases { + spi0 = &rpc; + }; + + soc { + u-boot,dm-pre-reloc; + }; + + leds { + led1 { + label = "peach:bottom:red"; + }; + + led-red { + label = "peach:tri:red"; + gpios = <&port6 13 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "peach:tri:green"; + gpios = <&port6 14 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "peach:tri:blue"; + gpios = <&port6 15 GPIO_ACTIVE_HIGH>; + }; + }; + + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r7s72100", "renesas,rpc"; + reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>; + bank-width = <2>; + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; + }; +}; + +&ostm0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&scif2 { + u-boot,dm-pre-reloc; + clock = <66666666>; /* ToDo: Replace by DM clock driver */ +}; + +&scif2_pins { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts new file mode 100644 index 0000000000..fe1a4aa4d7 --- /dev/null +++ b/arch/arm/dts/r7s72100-gr-peach.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the GR-Peach board + * + * Copyright (C) 2017 Jacopo Mondi jacopo+renesas@jmondi.org + * Copyright (C) 2016 Renesas Electronics + */ + +/dts-v1/; +#include "r7s72100.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> + +/ { + model = "GR-Peach"; + compatible = "renesas,gr-peach", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x00a00000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + flash@18000000 { + compatible = "mtd-rom"; + probe-type = "map_rom"; + reg = <0x18000000 0x00800000>; + bank-width = <4>; + device-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + + rootfs@600000 { + label = "rootfs"; + reg = <0x00600000 0x00200000>; + }; + }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port6 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + scif2_pins: serial2 { + /* P6_2 as RxD2; P6_3 as TxD2 */ + pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>; + }; + + ether_pins: ether { + /* Ethernet on Ports 1,3,5,10 */ + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */ + <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */ + <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */ + <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */ + <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */ + <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */ + <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */ + <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */ + <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */ + <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */ + <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */ + <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */ + <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */ + <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */ + <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */ + <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */ + <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */ + <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */ + }; +}; + +&extal_clk { + clock-frequency = <13333000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&mtu2 { + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + + phy0: ethernet-phy@0 { + reg = <0>; + + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <5>; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.rza1 b/arch/arm/mach-rmobile/Kconfig.rza1 index efb703b92b..8cf033fb13 100644 --- a/arch/arm/mach-rmobile/Kconfig.rza1 +++ b/arch/arm/mach-rmobile/Kconfig.rza1 @@ -13,9 +13,16 @@ config CPU_RZA1 choice prompt "Renesas RZ/A1 board select"
+# Renesas Supported Boards +config TARGET_GRPEACH + bool "GR-PEACH board" + endchoice
config SYS_SOC default "rmobile"
+# Renesas Supported Boards +source "board/renesas/grpeach/Kconfig" + endif diff --git a/board/renesas/grpeach/Kconfig b/board/renesas/grpeach/Kconfig new file mode 100644 index 0000000000..00dc496b86 --- /dev/null +++ b/board/renesas/grpeach/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GRPEACH + +config SYS_BOARD + default "grpeach" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "grpeach" + +endif diff --git a/board/renesas/grpeach/MAINTAINERS b/board/renesas/grpeach/MAINTAINERS new file mode 100644 index 0000000000..4ab7773b0a --- /dev/null +++ b/board/renesas/grpeach/MAINTAINERS @@ -0,0 +1,6 @@ +GRPEACH BOARD +M: Marek Vasut marek.vasut@gmail.com +S: Maintained +F: board/renesas/grpeach/ +F: include/configs/grpeach.h +F: configs/grpeach_defconfig diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile new file mode 100644 index 0000000000..48e185ce3e --- /dev/null +++ b/board/renesas/grpeach/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Renesas Electronics +# Copyright (C) 2017 Chris Brandt +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := grpeach.o +obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c new file mode 100644 index 0000000000..4f901eea71 --- /dev/null +++ b/board/renesas/grpeach/grpeach.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +void reset_cpu(ulong addr) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/grpeach/lowlevel_init.S new file mode 100644 index 0000000000..9a66dfa6c6 --- /dev/null +++ b/board/renesas/grpeach/lowlevel_init.S @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) 2017 Chris Brandt + */ +#include <config.h> +#include <version.h> +#include <asm/macro.h> + +/* Watchdog Registers */ +#define RZA1_WDT_BASE 0xFCFE0000 +#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ +#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */ +#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */ + +/* Standby controller registers (chapter 55) */ +#define RZA1_STBCR_BASE 0xFCFE0020 +#define STBCR1 (RZA1_STBCR_BASE + 0x00) +#define STBCR2 (RZA1_STBCR_BASE + 0x04) +#define STBCR3 (RZA1_STBCR_BASE + 0x400) +#define STBCR4 (RZA1_STBCR_BASE + 0x404) +#define STBCR5 (RZA1_STBCR_BASE + 0x408) +#define STBCR6 (RZA1_STBCR_BASE + 0x40c) +#define STBCR7 (RZA1_STBCR_BASE + 0x410) +#define STBCR8 (RZA1_STBCR_BASE + 0x414) +#define STBCR9 (RZA1_STBCR_BASE + 0x418) +#define STBCR10 (RZA1_STBCR_BASE + 0x41c) +#define STBCR11 (RZA1_STBCR_BASE + 0x420) +#define STBCR12 (RZA1_STBCR_BASE + 0x424) +#define STBCR13 (RZA1_STBCR_BASE + 0x450) + +/* Clock Registers */ +#define RZA1_FRQCR_BASE 0xFCFE0010 +#define FRQCR (RZA1_FRQCR_BASE + 0x00) +#define FRQCR2 (RZA1_FRQCR_BASE + 0x04) + +#define SYSCR1 0xFCFE0400 /* System control register 1 */ +#define SYSCR2 0xFCFE0404 /* System control register 2 */ +#define SYSCR3 0xFCFE0408 /* System control register 3 */ + +/* Disable WDT */ +#define WTCSR_D 0xA518 +#define WTCNT_D 0x5A00 + +/* Enable all peripheral clocks */ +#define STBCR3_D 0x00000000 +#define STBCR4_D 0x00000000 +#define STBCR5_D 0x00000000 +#define STBCR6_D 0x00000000 +#define STBCR7_D 0x00000024 +#define STBCR8_D 0x00000005 +#define STBCR9_D 0x00000000 +#define STBCR10_D 0x00000000 +#define STBCR11_D 0x000000c0 +#define STBCR12_D 0x000000f0 + +/* + * Set all system clocks to full speed. + * On reset, the CPU will be running at 1/2 speed. + * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges + */ +#define FRQCR_D 0x0035 +#define FRQCR2_D 0x0001 + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* PL310 init */ + write32 0x3fffff80, 0x00000001 + + /* Disable WDT */ + write16 WTCSR, WTCSR_D + write16 WTCNT, WTCNT_D + + /* Set clocks */ + write16 FRQCR, FRQCR_D + write16 FRQCR2, FRQCR2_D + + /* Enable all peripherals(Standby Control) */ + write8 STBCR3, STBCR3_D + write8 STBCR4, STBCR4_D + write8 STBCR5, STBCR5_D + write8 STBCR6, STBCR6_D + write8 STBCR7, STBCR7_D + write8 STBCR8, STBCR8_D + write8 STBCR9, STBCR9_D + write8 STBCR10, STBCR10_D + write8 STBCR11, STBCR11_D + write8 STBCR12, STBCR12_D + + /* For serial booting, enable read ahead caching to speed things up */ +#define DRCR_0 0x3FEFA00C + write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */ + + /* Enable all internal RAM */ + write8 SYSCR1, 0xFF + write8 SYSCR2, 0xFF + write8 SYSCR3, 0xFF + + nop + /* back to arch calling code */ + mov pc, lr + + .align 4 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig new file mode 100644 index 0000000000..32254b3b0e --- /dev/null +++ b/configs/grpeach_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +# CONFIG_SPL_SYS_THUMB_BUILD is not set +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x18000000 +CONFIG_RZA1=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=50000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_DM_GPIO=y +CONFIG_RZA1_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +CONFIG_SH_ETHER=y +CONFIG_PINCTRL=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_TIMER=y +CONFIG_RENESAS_OSTM_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h new file mode 100644 index 0000000000..01704d84c2 --- /dev/null +++ b/include/configs/grpeach.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Renesas GRPEACH board + * + * Copyright (C) 2017-2019 Renesas Electronics + */ + +#ifndef __GRPEACH_H +#define __GRPEACH_H + +/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* Serial Console */ +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous */ +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH +#define CONFIG_CMDLINE_TAG +#define CONFIG_ARCH_CPU_INIT + +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) +#define CONFIG_SYS_LOAD_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET 0xc0000 + +/* Malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +/* Kernel Boot */ +#define CONFIG_BOOTARGS "ignore_loglevel" + +/* Network interface */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +#endif /* __GRPEACH_H */
participants (2)
-
Joe Hershberger -
Marek Vasut