Currently sunxi Makefile manually specifies full path to dw-hdmi common code. However, that is not needed because it can be selected in Kconfig instead.

Select proper symbol in Kconfig and drop path from Makefile.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/Makefile | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 0135575ca1eb..9149196b223e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -972,6 +972,7 @@ config VIDEO_DE2 depends on SUNXI_DE2 select DM_VIDEO select DISPLAY + select VIDEO_DW_HDMI imply VIDEO_DT_SIMPLEFB default y ---help--- diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile index 147e18799229..4321673312bf 100644 --- a/drivers/video/sunxi/Makefile +++ b/drivers/video/sunxi/Makefile @@ -4,4 +4,4 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.

obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o simplefb_common.o lcdc.o tve_common.o ../videomodes.o -obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o sunxi_lcd.o +obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o sunxi_lcd.o

Currently driver accepts all resolution which won't work on 4k screens. Add validation callback which limits acceptable resolutions to 297 MHz.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_dw_hdmi.c | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0b8cefc311ef..e3811a2ec15f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -305,6 +305,12 @@ static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); }

+static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, + const struct display_timing *timing) +{ + return timing->pixelclock.typ <= 297000000; +} + static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { @@ -388,6 +394,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) static const struct dm_display_ops sunxi_dw_hdmi_ops = { .read_edid = sunxi_dw_hdmi_read_edid, .enable = sunxi_dw_hdmi_enable, + .mode_valid = sunxi_dw_hdmi_mode_valid, };

U_BOOT_DRIVER(sunxi_dw_hdmi) = {

When searching for detailed timing in EDID, check for digital display earlier. There is no point parsing other parameters if this flag is not present.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- common/edid.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/common/edid.c b/common/edid.c index 553ab8fd01a1..1cb7177742e8 100644 --- a/common/edid.c +++ b/common/edid.c @@ -185,6 +185,11 @@ int edid_get_timing_validate(u8 *buf, int buf_size, return -EINVAL; }

+ if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { + debug("%s: Not a digital display\n", __func__); + return -ENOSYS; + } + if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { debug("%s: No preferred timing\n", __func__); return -ENOENT; @@ -211,10 +216,6 @@ int edid_get_timing_validate(u8 *buf, int buf_size, if (!timing_done) return -EINVAL;

- if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { - debug("%s: Not a digital display\n", __func__); - return -ENOSYS; - } if (edid->version != 1 || edid->revision < 4) { debug("%s: EDID version %d.%d does not have required info\n", __func__, edid->version, edid->revision);

Code which searches for valid detailed timing entry will be used in more places. Extract it.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- common/edid.c | 49 ++++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 21 deletions(-)

diff --git a/common/edid.c b/common/edid.c index 1cb7177742e8..a6c875d9c8e8 100644 --- a/common/edid.c +++ b/common/edid.c @@ -169,6 +169,29 @@ static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) return false; }

+static bool edid_find_valid_timing(void *buf, int count, + struct display_timing *timing, + bool (*mode_valid)(void *priv, + const struct display_timing *timing), + void *mode_valid_priv) +{ + struct edid_detailed_timing *t = buf; + bool found = false; + int i; + + for (i = 0; i < count && !found; i++, t++) + if (EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) != 0) { + decode_timing((u8 *)t, timing); + if (mode_valid) + found = mode_valid(mode_valid_priv, + timing); + else + found = true; + } + + return found; +} + int edid_get_timing_validate(u8 *buf, int buf_size, struct display_timing *timing, int *panel_bits_per_colourp, @@ -177,8 +200,7 @@ int edid_get_timing_validate(u8 *buf, int buf_size, void *mode_valid_priv) { struct edid1_info *edid = (struct edid1_info *)buf; - bool timing_done; - int i; + bool found;

if (buf_size < sizeof(*edid) || edid_check_info(edid)) { debug("%s: Invalid buffer\n", __func__); @@ -195,25 +217,10 @@ int edid_get_timing_validate(u8 *buf, int buf_size, return -ENOENT; }

- /* Look for detailed timing */ - timing_done = false; - for (i = 0; i < 4; i++) { - struct edid_monitor_descriptor *desc; - - desc = &edid->monitor_details.descriptor[i]; - if (desc->zero_flag_1 != 0) { - decode_timing((u8 *)desc, timing); - if (mode_valid) - timing_done = mode_valid(mode_valid_priv, - timing); - else - timing_done = true; - - if (timing_done) - break; - } - } - if (!timing_done) + /* Look for detailed timing in base EDID */ + found = edid_find_valid_timing(edid->monitor_details.descriptor, 4, + timing, mode_valid, mode_valid_priv); + if (!found) return -EINVAL;

if (edid->version != 1 || edid->revision < 4) {

It turns out that even though A64, H3 and H5 have custom PHY, standard hot plug detection for DW-HDMI works just fine.

Remove custom hpd method to reduce amount of custom code.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_dw_hdmi.c | 34 +++++------------------------ 1 file changed, 6 insertions(+), 28 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index e3811a2ec15f..37e78ff24111 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -114,28 +114,6 @@ static void sunxi_dw_hdmi_phy_init(void) writel(0x42494E47, &phy->unscramble); }

-static int sunxi_dw_hdmi_get_plug_in_status(void) -{ - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); - - return !!(readl(&phy->status) & (1 << 19)); -} - -static int sunxi_dw_hdmi_wait_for_hpd(void) -{ - ulong start; - - start = get_timer(0); - do { - if (sunxi_dw_hdmi_get_plug_in_status()) - return 0; - udelay(100); - } while (get_timer(start) < 300); - - return -1; -} - static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) { struct sunxi_hdmi_phy * const phy = @@ -370,12 +348,6 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)

sunxi_dw_hdmi_phy_init();

- ret = sunxi_dw_hdmi_wait_for_hpd(); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } - priv->hdmi.ioaddr = SUNXI_HDMI_BASE; priv->hdmi.i2c_clk_high = 0xd8; priv->hdmi.i2c_clk_low = 0xfe; @@ -383,6 +355,12 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; priv->mux = uc_plat->source_id;

+ ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); + if (ret < 0) { + debug("hdmi can not get hpd signal\n"); + return -1; + } + uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", &priv->hdmi.ddc_bus);

TV driver was never fully implemented. Remove search for it from DE2 driver.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_de2.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index a3e21aa5f13e..6b836a011944 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -281,20 +281,7 @@ static int sunxi_de2_probe(struct udevice *dev)

debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);

- ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_tve", &disp); - if (ret) { - debug("%s: tv not found (ret=%d)\n", __func__, ret); - return ret; - } - - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); - if (ret) - return ret; - - video_set_flush_dcache(dev, 1); - - return 0; + return -ENODEV; }

static int sunxi_de2_bind(struct udevice *dev)

Currently sunxi dw-hdmi driver is probed unconditionally, even if there is no such device.

Switch driver to probing via compatible string. This brings many benefits - driver can read DT node and allows driver to be always enabled.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_dw_hdmi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 6d2bc206fc2c..6f77b2a43b40 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -372,14 +372,16 @@ static const struct dm_display_ops sunxi_dw_hdmi_ops = { .mode_valid = sunxi_dw_hdmi_mode_valid, };

+static const struct udevice_id sunxi_dw_hdmi_ids[] = { + { .compatible = "allwinner,sun8i-a83t-dw-hdmi" }, + { } +}; + U_BOOT_DRIVER(sunxi_dw_hdmi) = { .name = "sunxi_dw_hdmi", .id = UCLASS_DISPLAY, + .of_match = sunxi_dw_hdmi_ids, .ops = &sunxi_dw_hdmi_ops, .probe = sunxi_dw_hdmi_probe, .priv_auto = sizeof(struct sunxi_dw_hdmi_priv), }; - -U_BOOT_DRVINFO(sunxi_dw_hdmi) = { - .name = "sunxi_dw_hdmi" -};

Currently PHY init callback has only pixel clock as a parameter, but other timing parameters may be needed for custom PHYs. Modify callback signature to include full timings.

Cc: Neil Armstrong narmstrong@baylibre.com Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/dw_hdmi.c | 6 +++--- drivers/video/meson/meson_dw_hdmi.c | 5 +++-- drivers/video/sunxi/sunxi_dw_hdmi.c | 7 ++++--- include/dw_hdmi.h | 4 ++-- 4 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index c4fbb1829446..8d71f713f99f 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -901,7 +901,7 @@ static const u8 pre_buf[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, };

-int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid) { int i, ret;

@@ -912,7 +912,7 @@ int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) hdmi_phy_enable_tmds(hdmi, 0); hdmi_phy_enable_power(hdmi, 0);

- ret = hdmi_phy_configure(hdmi, mpixelclock); + ret = hdmi_phy_configure(hdmi, edid->pixelclock.typ); if (ret) { debug("hdmi phy config failure %d\n", ret); return ret; @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)

hdmi_av_composer(hdmi, edid);

- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); + ret = hdmi->phy_set(hdmi, edid); if (ret) return ret;

diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index e5f281320534..7558814b3491 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -292,7 +292,8 @@ static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv, } }

-static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) +static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, + const struct display_timing *edid) { struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi, hdmi); @@ -322,7 +323,7 @@ static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);

/* Setup PHY parameters */ - meson_dw_hdmi_phy_setup_mode(priv, pixel_clock); + meson_dw_hdmi_phy_setup_mode(priv, edid->pixelclock.typ);

/* Setup PHY */ dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0744954fa15f..483d57293155 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -266,12 +266,13 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, lcdc_enable(lcdc, bpp); }

-static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, + const struct display_timing *edid) { int phy_div;

- sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div); + sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div); + sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div);

return 0; } diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index 8acae3839fb3..46b87916b8bb 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -544,12 +544,12 @@ struct dw_hdmi { struct hdmi_data_info hdmi_data; struct udevice *ddc_bus;

- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); + int (*phy_set)(struct dw_hdmi *hdmi, const struct display_timing *edid); void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); };

-int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid); int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); void dw_hdmi_phy_init(struct dw_hdmi *hdmi);

Now that bit meanings are somewhat known, rework PHY initialization. This is modelled after Linux driver.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_dw_hdmi.c | 411 +++++++++++++++++++--------- 1 file changed, 279 insertions(+), 132 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 4cc175d714ea..c4cded569bfb 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -18,100 +18,200 @@ #include <linux/bitops.h> #include <linux/delay.h>

+#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9) +#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16) +#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16) + +#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31) + +#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545 + +#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47 + +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x) ((x) << 26) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x) ((x) << 24) +#define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23) +#define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT BIT(22) +#define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT BIT(21) +#define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT BIT(20) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL BIT(19) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG BIT(18) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS BIT(17) +#define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN BIT(16) +#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK GENMASK(15, 12) +#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL (0xf << 12) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK BIT(11) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 BIT(10) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 BIT(9) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 BIT(8) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK BIT(7) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 BIT(6) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 BIT(5) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 BIT(4) +#define SUN8I_HDMI_PHY_ANA_CFG1_CKEN BIT(3) +#define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN BIT(2) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS BIT(1) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENBI BIT(0) + +#define SUN8I_HDMI_PHY_ANA_CFG2_M_EN BIT(31) +#define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN BIT(30) +#define SUN8I_HDMI_PHY_ANA_CFG2_SEN BIT(29) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD BIT(28) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN BIT(27) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK BIT(26) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x) ((x) << 23) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK BIT(22) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN BIT(21) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x) ((x) << 19) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x) ((x) << 17) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK BIT(16) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW BIT(15) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x) ((x) << 13) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x) ((x) << 10) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x) ((x) << 8) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x) ((x) << 6) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x) ((x) << 0) + +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x) ((x) << 30) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x) ((x) << 28) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x) ((x) << 18) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x) ((x) << 14) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x) ((x) << 11) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x) ((x) << 7) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x) ((x) << 4) +#define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD BIT(3) +#define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN BIT(2) +#define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD BIT(1) +#define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN BIT(0) + +#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 BIT(31) +#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD BIT(30) +#define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29) +#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28) +#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27) +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26) +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26 +#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25) +#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22) +#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20) +#define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN BIT(19) +#define SUN8I_HDMI_PHY_PLL_CFG1_CS BIT(18) +#define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x) ((x) << 13) +#define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x) ((x) << 7) +#define SUN8I_HDMI_PHY_PLL_CFG1_BWS BIT(6) +#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK GENMASK(5, 0) +#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT 0 + +#define SUN8I_HDMI_PHY_PLL_CFG2_SV_H BIT(31) +#define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x) ((x) << 29) +#define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x) ((x) << 27) +#define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x) ((x) << 24) +#define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL BIT(23) +#define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS BIT(22) +#define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN BIT(21) +#define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN BIT(20) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN BIT(19) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x) ((x) << 16) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x) ((x) << 12) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN BIT(11) +#define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC BIT(10) +#define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2 BIT(9) +#define SUN8I_HDMI_PHY_PLL_CFG2_S(x) ((x) << 6) +#define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5 BIT(5) +#define SUN8I_HDMI_PHY_PLL_CFG2_S5_7 BIT(4) +#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK GENMASK(3, 0) +#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT 0 +#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x) (((x) - 1) << 0) + +#define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2 BIT(0) + +#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT 11 +#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK GENMASK(16, 11) +#define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D BIT(7) +#define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0) + struct sunxi_dw_hdmi_priv { struct dw_hdmi hdmi; int mux; + uint rcal; };

struct sunxi_hdmi_phy { - u32 pol; - u32 res1[3]; + u32 dbg_ctrl; + u32 rext_ctrl; + u32 res1[2]; u32 read_en; u32 unscramble; u32 res2[2]; - u32 ctrl; - u32 unk1; - u32 unk2; - u32 pll; - u32 clk; - u32 unk3; - u32 status; + u32 ana_cfg1; + u32 ana_cfg2; + u32 ana_cfg3; + u32 pll_cfg1; + u32 pll_cfg2; + u32 pll_cfg3; + u32 ana_sts; };

#define HDMI_PHY_OFFS 0x10000

-static int sunxi_dw_hdmi_get_divider(uint clock) -{ - /* - * Due to missing documentaion of HDMI PHY, we know correct - * settings only for following four PHY dividers. Select one - * based on clock speed. - */ - if (clock <= 27000000) - return 11; - else if (clock <= 74250000) - return 4; - else if (clock <= 148500000) - return 2; - else - return 1; -} - -static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) +static void sunxi_dw_hdmi_phy_init(struct sunxi_dw_hdmi_priv *priv) { struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); + (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS); unsigned long tmo; - u32 tmp;

- /* - * HDMI PHY settings are taken as-is from Allwinner BSP code. - * There is no documentation. - */ - writel(0, &phy->ctrl); - setbits_le32(&phy->ctrl, BIT(0)); + /* enable read access to HDMI controller */ + writel(SUN8I_HDMI_PHY_READ_EN_MAGIC, &phy->read_en); + /* descramble register offsets */ + writel(SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC, &phy->unscramble); + + writel(0, &phy->ana_cfg1); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENBI); udelay(5); - setbits_le32(&phy->ctrl, BIT(16)); - setbits_le32(&phy->ctrl, BIT(1)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENVBS); udelay(10); - setbits_le32(&phy->ctrl, BIT(2)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_LDOEN); udelay(5); - setbits_le32(&phy->ctrl, BIT(3)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_CKEN); udelay(40); - setbits_le32(&phy->ctrl, BIT(19)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL); udelay(100); - setbits_le32(&phy->ctrl, BIT(18)); - setbits_le32(&phy->ctrl, 7 << 4); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG); + setbits_le32(&phy->ana_cfg1, + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2);

/* Note that Allwinner code doesn't fail in case of timeout */ tmo = timer_get_us() + 2000; - while ((readl(&phy->status) & 0x80) == 0) { + while ((readl(&phy->ana_sts) & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D) == 0) { if (timer_get_us() > tmo) { printf("Warning: HDMI PHY init timeout!\n"); break; } }

- setbits_le32(&phy->ctrl, 0xf << 8); - setbits_le32(&phy->ctrl, BIT(7)); + setbits_le32(&phy->ana_cfg1, + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK);

- writel(0x39dc5040, &phy->pll); - writel(0x80084343, &phy->clk); - udelay(10000); - writel(1, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - udelay(100000); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FF0F7F, &phy->ctrl); - writel(0x80639000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); + /* enable DDC communication */ + writel(SUN8I_HDMI_PHY_ANA_CFG3_SCLEN | + SUN8I_HDMI_PHY_ANA_CFG3_SDAEN, &phy->ana_cfg3);

- /* enable read access to HDMI controller */ - writel(0x54524545, &phy->read_en); - /* descramble register offsets */ - writel(0x42494E47, &phy->unscramble); + priv->rcal = readl(&phy->ana_sts) & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK; + priv->rcal >>= 2; }

static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, @@ -120,83 +220,130 @@ static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, { struct sunxi_hdmi_phy * const phy = (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); - int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); - u32 tmp; + struct sunxi_dw_hdmi_priv *priv = + container_of(hdmi, struct sunxi_dw_hdmi_priv, hdmi); + u32 pll_cfg1, pll_cfg2, ana_cfg1, ana_cfg2, ana_cfg3; + u32 tmp, b_offset = 0;

- /* - * Unfortunately, we don't know much about those magic - * numbers. They are taken from Allwinner BSP driver. - */ - switch (div) { - case 1: - writel(0x30dc5fc0, &phy->pll); - writel(0x800863C0 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(200); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - if (tmp < 0x3d) - setbits_le32(&phy->pll, tmp + 2); - else - setbits_le32(&phy->pll, 0x3f); - mdelay(100); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F8246B5, &phy->unk2); - break; - case 2: - writel(0x39dc5040, &phy->pll); - writel(0x80084380 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063a800, &phy->unk1); - writel(0x0F81C485, &phy->unk2); - break; - case 4: - writel(0x39dc5040, &phy->pll); - writel(0x80084340 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - break; - case 11: - writel(0x39dc5040, &phy->pll); - writel(0x80084300 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - break; + /* bandwidth / frequency independent settings */ + + pll_cfg1 = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN | + SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN | + SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) | + SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) | + SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN | + SUN8I_HDMI_PHY_PLL_CFG1_CS | + SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) | + SUN8I_HDMI_PHY_PLL_CFG1_BWS; + + pll_cfg2 = SUN8I_HDMI_PHY_PLL_CFG2_SV_H | + SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN | + SUN8I_HDMI_PHY_PLL_CFG2_SDIV2; + + ana_cfg1 = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) | + SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL | + SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG | + SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS | + SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN | + SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_CKEN | + SUN8I_HDMI_PHY_ANA_CFG1_LDOEN | + SUN8I_HDMI_PHY_ANA_CFG1_ENVBS | + SUN8I_HDMI_PHY_ANA_CFG1_ENBI; + + ana_cfg2 = SUN8I_HDMI_PHY_ANA_CFG2_M_EN | + SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK | + SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN | + SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) | + SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1); + + ana_cfg3 = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) | + SUN8I_HDMI_PHY_ANA_CFG3_SDAEN | + SUN8I_HDMI_PHY_ANA_CFG3_SCLEN; + + /* bandwidth / frequency dependent settings */ + if (edid->pixelclock.typ <= 27000000) { + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | + SUN8I_HDMI_PHY_PLL_CFG2_S(4); + ana_cfg1 |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW; + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) | + SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(priv->rcal); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5); + } else if (edid->pixelclock.typ <= 74250000) { + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | + SUN8I_HDMI_PHY_PLL_CFG2_S(5); + ana_cfg1 |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW; + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) | + SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(priv->rcal); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7); + } else if (edid->pixelclock.typ <= 148500000) { + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | + SUN8I_HDMI_PHY_PLL_CFG2_S(6); + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK | + SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | + SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9); + } else { + b_offset = 2; + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) | + SUN8I_HDMI_PHY_PLL_CFG2_S(7); + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK | + SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | + SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3); }

+ writel(pll_cfg1, &phy->pll_cfg1); + writel(pll_cfg2 | (phy_div - 1), &phy->pll_cfg2); + mdelay(10); + writel(SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2, &phy->pll_cfg3); + setbits_le32(&phy->pll_cfg1, SUN8I_HDMI_PHY_PLL_CFG1_PLLEN); + mdelay(100); + tmp = readl(&phy->ana_sts) & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK; + tmp >>= SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT; + tmp = min(tmp + b_offset, (u32)0x3f); + setbits_le32(&phy->pll_cfg1, + SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 | + SUN8I_HDMI_PHY_PLL_CFG1_REG_OD); + setbits_le32(&phy->pll_cfg1, tmp); + mdelay(100); + writel(ana_cfg1, &phy->ana_cfg1); + writel(ana_cfg2, &phy->ana_cfg2); + writel(ana_cfg3, &phy->ana_cfg3); + if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) - setbits_le32(&phy->pol, 0x200); + setbits_le32(&phy->dbg_ctrl, + SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC);

if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) - setbits_le32(&phy->pol, 0x100); + setbits_le32(&phy->dbg_ctrl, + SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC);

- setbits_le32(&phy->ctrl, 0xf << 12); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL); }

static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) @@ -363,7 +510,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) /* Clock on */ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);

- sunxi_dw_hdmi_phy_init(&priv->hdmi); + sunxi_dw_hdmi_phy_init(priv);

priv->mux = uc_plat->source_id;

Currently DE2 driver is probed via driver info. Switch probing to device tree compatible string method.

Display is now searched via driver name which has same limitation as previous method. This can be improved only when all drivers in chain are probed via device tree compatible strings.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_de2.c | 88 +++++++++++++++++++-------------- 1 file changed, 52 insertions(+), 36 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index e02d359cd259..81576e45e9ef 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -31,6 +31,11 @@ enum { LCD_MAX_LOG2_BPP = VIDEO_BPP32, };

+struct sunxi_de2_data { + int id; + const char *disp_drv_name; +}; + static void sunxi_de2_composer_init(void) { struct sunxi_ccm_reg * const ccm = @@ -228,51 +233,34 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase,

static int sunxi_de2_probe(struct udevice *dev) { + const struct sunxi_de2_data *data = + (const struct sunxi_de2_data *)dev_get_driver_data(dev); struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct udevice *disp; - int ret; + int ret, index = 0;

/* Before relocation we don't need to do anything */ if (!(gd->flags & GD_FLG_RELOC)) return 0;

- ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(sunxi_lcd), &disp); - if (!ret) { - int mux; + while (!(ret = uclass_get_device(UCLASS_DISPLAY, index++, &disp))) { + if (strcmp(disp->driver->name, data->disp_drv_name)) + continue;

- mux = 0; + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, + data->id, false); + if (ret) + return ret;

- ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, - false); - if (!ret) { - video_set_flush_dcache(dev, 1); - return 0; - } - } - - debug("%s: lcd display not found (ret=%d)\n", __func__, ret); - - ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(sunxi_dw_hdmi), &disp); - if (!ret) { - int mux; - if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) - mux = 0; - else - mux = 1; + video_set_flush_dcache(dev, 1);

- ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, - false); - if (!ret) { - video_set_flush_dcache(dev, 1); - return 0; - } + return 0; }

- debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); + debug("%s: %s not found (ret=%d)\n", __func__, + data->disp_drv_name, ret);

- return -ENODEV; + return ret; }

static int sunxi_de2_bind(struct udevice *dev) @@ -285,22 +273,50 @@ static int sunxi_de2_bind(struct udevice *dev) return 0; }

+const struct sunxi_de2_data h3_mixer_0 = { + .id = 0, + .disp_drv_name = "sunxi_dw_hdmi", +}; + +const struct sunxi_de2_data a64_mixer_0 = { + .id = 0, + .disp_drv_name = "sunxi_lcd", +}; + +const struct sunxi_de2_data a64_mixer_1 = { + .id = 1, + .disp_drv_name = "sunxi_dw_hdmi", +}; + +static const struct udevice_id sunxi_de2_ids[] = { + { + .compatible = "allwinner,sun8i-h3-de2-mixer-0", + .data = (ulong)&h3_mixer_0, + }, + { + .compatible = "allwinner,sun50i-a64-de2-mixer-0", + .data = (ulong)&a64_mixer_0, + }, + { + .compatible = "allwinner,sun50i-a64-de2-mixer-1", + .data = (ulong)&a64_mixer_1, + }, + { } +}; + static const struct video_ops sunxi_de2_ops = { };

U_BOOT_DRIVER(sunxi_de2) = { .name = "sunxi_de2", .id = UCLASS_VIDEO, + .of_match = sunxi_de2_ids, .ops = &sunxi_de2_ops, .bind = sunxi_de2_bind, .probe = sunxi_de2_probe, .flags = DM_FLAG_PRE_RELOC, };

-U_BOOT_DRVINFO(sunxi_de2) = { - .name = "sunxi_de2" -}; - /* * Simplefb support. */

With the next commit another clock and reset driver will be implemented which requires DE2 related clocks and resets. Add them.

Cc: Lukasz Majewski lukma@denx.de Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 0553ffa4399a..c7cf88ce3436 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -26,6 +26,8 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),

+ [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -41,6 +43,8 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)), [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), + + [CLK_DE] = GATE(0x104, BIT(31)), };

static const struct ccu_reset a64_resets[] = { @@ -60,6 +64,8 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),

+ [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f81633b92d5a..bf8d963d18b6 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -30,6 +30,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),

+ [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -48,6 +50,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)), + + [CLK_DE] = GATE(0x104, BIT(31)), };

static struct ccu_reset h3_resets[] = { @@ -72,6 +76,8 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),

+ [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),

[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),

Now that proper DM clock and reset driver exists for Display Engine 2 and 3, remove all clock and reset related code and use appropriate framework instead.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/sunxi_de2.c | 67 +++++++++++---------------------- 2 files changed, 23 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9149196b223e..34ef1f4b030f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -970,6 +970,7 @@ config SUNXI_DE2 config VIDEO_DE2 bool "Display Engine 2 video driver" depends on SUNXI_DE2 + select CLK_SUN8I_DE2 select DM_VIDEO select DISPLAY select VIDEO_DW_HDMI diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index f6c8ca075aba..cee9b46b1259 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -6,6 +6,7 @@ */

#include <common.h> +#include <clk.h> #include <display.h> #include <dm.h> #include <edid.h> @@ -14,10 +15,10 @@ #include <fdt_support.h> #include <log.h> #include <part.h> +#include <reset.h> #include <video.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/arch/clock.h> #include <asm/arch/display2.h> #include <linux/bitops.h> #include "simplefb_common.h" @@ -36,40 +37,10 @@ struct sunxi_de2_data { const char *disp_drv_name; };

-static void sunxi_de2_composer_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - -#ifdef CONFIG_MACH_SUN50I - u32 reg_value; - - /* set SRAM for video use (A64 only) */ - reg_value = readl(SUNXI_SRAMC_BASE + 0x04); - reg_value &= ~(0x01 << 24); - writel(reg_value, SUNXI_SRAMC_BASE + 0x04); -#endif - - clock_set_pll10(432000000); - - /* Set DE parent to pll10 */ - clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, - CCM_DE2_CTRL_PLL10); - - /* Set ahb gating to pass */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); - - /* Clock on */ - setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); -} - -static void sunxi_de2_mode_set(ulong de_mux_base, int mux, +static void sunxi_de2_mode_set(ulong de_mux_base, const struct display_timing *mode, int bpp, ulong address, bool is_composite) { - struct de_clk * const de_clk_regs = - (struct de_clk *)(SUNXI_DE2_BASE); struct de_glb * const de_glb_regs = (struct de_glb *)(de_mux_base + SUNXI_DE2_MUX_GLB_REGS); @@ -87,17 +58,6 @@ static void sunxi_de2_mode_set(ulong de_mux_base, int mux, int channel; u32 format;

- /* enable clock */ -#ifdef CONFIG_MACH_SUN8I_H3 - setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); -#else - setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); -#endif - setbits_le32(&de_clk_regs->gate_cfg, BIT(mux)); - setbits_le32(&de_clk_regs->bus_cfg, BIT(mux)); - - clrbits_le32(&de_clk_regs->sel_cfg, 1); - writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl); writel(0, &de_glb_regs->status); writel(1, &de_glb_regs->dbuff); @@ -189,6 +149,8 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct display_timing timing; struct display_plat *disp_uc_plat; + struct reset_ctl_bulk resets; + struct clk_bulk clocks; int ret;

disp_uc_plat = dev_get_uclass_plat(disp); @@ -206,8 +168,23 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, return ret; }

- sunxi_de2_composer_init(); - sunxi_de2_mode_set((ulong)dev_read_addr(dev), mux, &timing, + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret; + + sunxi_de2_mode_set((ulong)dev_read_addr(dev), &timing, 1 << l2bpp, fbbase, is_composite);

ret = display_enable(disp, 1 << l2bpp, &timing);